About the Execution of LoLA for DLCround-PT-12a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16220.539 | 718295.00 | 804783.00 | 11775.30 | ??????????F??T?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477300762.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCround-PT-12a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477300762
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 6.9K Feb 25 19:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 19:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 19:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 61K Feb 25 19:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.3K Feb 25 20:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 98K Feb 25 20:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Feb 25 20:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 70K Feb 25 20:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 871K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-12a-CTLFireability-00
FORMULA_NAME DLCround-PT-12a-CTLFireability-01
FORMULA_NAME DLCround-PT-12a-CTLFireability-02
FORMULA_NAME DLCround-PT-12a-CTLFireability-03
FORMULA_NAME DLCround-PT-12a-CTLFireability-04
FORMULA_NAME DLCround-PT-12a-CTLFireability-05
FORMULA_NAME DLCround-PT-12a-CTLFireability-06
FORMULA_NAME DLCround-PT-12a-CTLFireability-07
FORMULA_NAME DLCround-PT-12a-CTLFireability-08
FORMULA_NAME DLCround-PT-12a-CTLFireability-09
FORMULA_NAME DLCround-PT-12a-CTLFireability-10
FORMULA_NAME DLCround-PT-12a-CTLFireability-11
FORMULA_NAME DLCround-PT-12a-CTLFireability-12
FORMULA_NAME DLCround-PT-12a-CTLFireability-13
FORMULA_NAME DLCround-PT-12a-CTLFireability-14
FORMULA_NAME DLCround-PT-12a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678325555920
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-12a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCround-PT-12a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DLCround-PT-12a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678326274215
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: LAUNCH task # 42 (type EXCL) for 37 DLCround-PT-12a-CTLFireability-11
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 58 (type FNDP) for 37 DLCround-PT-12a-CTLFireability-11
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lola: LAUNCH task # 59 (type EQUN) for 37 DLCround-PT-12a-CTLFireability-11
lola: time limit : 32000000 sec
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 61 (type SRCH) for 37 DLCround-PT-12a-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: CANCELED task # 59 (type EQUN) for DLCround-PT-12a-CTLFireability-11 (obsolete)
lola: FINISHED task # 59 (type EQUN) for DLCround-PT-12a-CTLFireability-11
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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DLCround-PT-12a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-11: DISJ 0 0 1 0 5 0 0 1
DLCround-PT-12a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-11: DISJ 0 0 1 0 5 0 0 1
DLCround-PT-12a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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42 AGEF EXCL 9/211 1/32 DLCround-PT-12a-CTLFireability-11 263782 m, 29930 m/sec, 17752225 t fired, .
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DLCround-PT-12a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-11: DISJ 0 0 1 0 5 0 0 1
DLCround-PT-12a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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42 AGEF EXCL 14/211 2/32 DLCround-PT-12a-CTLFireability-11 414179 m, 30079 m/sec, 27844483 t fired, .
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DLCround-PT-12a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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42 AGEF EXCL 19/211 3/32 DLCround-PT-12a-CTLFireability-11 561156 m, 29395 m/sec, 37736027 t fired, .
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DLCround-PT-12a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-11: DISJ 0 0 1 0 5 0 0 1
DLCround-PT-12a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-11: DISJ 0 0 1 0 5 0 0 1
DLCround-PT-12a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
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DLCround-PT-12a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
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DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-12a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-12a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
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42 AGEF EXCL 5/3383 1/5 DLCround-PT-12a-CTLFireability-11 153582 m, -1160182 m/sec, 10337740 t fired, .
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42 AGEF EXCL 10/3383 2/5 DLCround-PT-12a-CTLFireability-11 302458 m, 29775 m/sec, 20305802 t fired, .
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42 AGEF EXCL 15/3383 2/5 DLCround-PT-12a-CTLFireability-11 450260 m, 29560 m/sec, 30237550 t fired, .
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42 AGEF EXCL 25/3383 3/5 DLCround-PT-12a-CTLFireability-11 737520 m, 28463 m/sec, 49628707 t fired, .
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42 AGEF EXCL 30/3383 4/5 DLCround-PT-12a-CTLFireability-11 879043 m, 28304 m/sec, 59254008 t fired, .
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42 AGEF EXCL 35/3383 4/5 DLCround-PT-12a-CTLFireability-11 1019257 m, 28042 m/sec, 68851491 t fired, .
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42 AGEF EXCL 40/3383 5/5 DLCround-PT-12a-CTLFireability-11 1159538 m, 28056 m/sec, 78380849 t fired, .
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42 AGEF EXCL 45/3383 5/5 DLCround-PT-12a-CTLFireability-11 1299138 m, 27920 m/sec, 87866685 t fired, .
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54 CTL EXCL 195/211 18/32 DLCround-PT-12a-CTLFireability-15 4057937 m, 20645 m/sec, 296864342 t fired, .
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54 CTL EXCL 210/211 19/32 DLCround-PT-12a-CTLFireability-15 4357019 m, 20616 m/sec, 318856222 t fired, .
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51 CTL EXCL 5/211 2/32 DLCround-PT-12a-CTLFireability-14 274018 m, 54803 m/sec, 5750831 t fired, .
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51 CTL EXCL 10/211 3/32 DLCround-PT-12a-CTLFireability-14 550813 m, 55359 m/sec, 11462701 t fired, .
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51 CTL EXCL 15/211 4/32 DLCround-PT-12a-CTLFireability-14 874161 m, 64669 m/sec, 16958957 t fired, .
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51 CTL EXCL 20/211 5/32 DLCround-PT-12a-CTLFireability-14 1125011 m, 50170 m/sec, 22370654 t fired, .
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51 CTL EXCL 25/211 6/32 DLCround-PT-12a-CTLFireability-14 1332453 m, 41488 m/sec, 27744628 t fired, .
54 CTL EXCL 25/198 3/5 DLCround-PT-12a-CTLFireability-15 488538 m, 22106 m/sec, 40769055 t fired, .
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51 CTL EXCL 30/211 7/32 DLCround-PT-12a-CTLFireability-14 1556518 m, 44813 m/sec, 32992017 t fired, .
54 CTL EXCL 30/198 3/5 DLCround-PT-12a-CTLFireability-15 597951 m, 21882 m/sec, 48770758 t fired, .
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51 CTL EXCL 35/211 8/32 DLCround-PT-12a-CTLFireability-14 1781647 m, 45025 m/sec, 38757033 t fired, .
54 CTL EXCL 35/198 3/5 DLCround-PT-12a-CTLFireability-15 707636 m, 21937 m/sec, 57096591 t fired, .
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51 CTL EXCL 45/211 10/32 DLCround-PT-12a-CTLFireability-14 2165905 m, 37124 m/sec, 48797230 t fired, .
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/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 373 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-12a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCround-PT-12a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477300762"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-12a.tgz
mv DLCround-PT-12a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;