Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477300740.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCround-PT-10b, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477300740
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.9M
-rw-r--r-- 1 mcc users 5.4K Feb 25 18:52 CTLCardinality.txt
-rw-r--r-- 1 mcc users 52K Feb 25 18:52 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 25 18:52 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 18:52 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.9K Feb 25 18:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 103K Feb 25 18:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.3K Feb 25 18:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Feb 25 18:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.5M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-10b-LTLFireability-00
FORMULA_NAME DLCround-PT-10b-LTLFireability-01
FORMULA_NAME DLCround-PT-10b-LTLFireability-02
FORMULA_NAME DLCround-PT-10b-LTLFireability-03
FORMULA_NAME DLCround-PT-10b-LTLFireability-04
FORMULA_NAME DLCround-PT-10b-LTLFireability-05
FORMULA_NAME DLCround-PT-10b-LTLFireability-06
FORMULA_NAME DLCround-PT-10b-LTLFireability-07
FORMULA_NAME DLCround-PT-10b-LTLFireability-08
FORMULA_NAME DLCround-PT-10b-LTLFireability-09
FORMULA_NAME DLCround-PT-10b-LTLFireability-10
FORMULA_NAME DLCround-PT-10b-LTLFireability-11
FORMULA_NAME DLCround-PT-10b-LTLFireability-12
FORMULA_NAME DLCround-PT-10b-LTLFireability-13
FORMULA_NAME DLCround-PT-10b-LTLFireability-14
FORMULA_NAME DLCround-PT-10b-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1678323053943

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-10b
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT DLCround-PT-10b
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA DLCround-PT-10b-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10b-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678324026784

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:490
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:490
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-LTLFireability-00: F 0 0 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-07: CONJ 0 0 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
DLCround-PT-10b-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
DLCround-PT-10b-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
DLCround-PT-10b-LTLFireability-13: CONJ 0 0 0 0 0 0 0 0
DLCround-PT-10b-LTLFireability-14: F 0 0 0 0 0 0 0 0
DLCround-PT-10b-LTLFireability-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 8 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 56 (type EXCL) for 0 DLCround-PT-10b-LTLFireability-00
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 58 (type FNDP) for 21 DLCround-PT-10b-LTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 21 DLCround-PT-10b-LTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 61 (type SRCH) for 21 DLCround-PT-10b-LTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 61 (type SRCH) for DLCround-PT-10b-LTLFireability-07
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/LTLFireability-59.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 59 (type EQUN) for DLCround-PT-10b-LTLFireability-07
lola: result : true
lola: CANCELED task # 58 (type FNDP) for DLCround-PT-10b-LTLFireability-07 (obsolete)
lola: FINISHED task # 56 (type EXCL) for DLCround-PT-10b-LTLFireability-00
lola: result : true
lola: markings : 200
lola: fired transitions : 200
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 DLCround-PT-10b-LTLFireability-03
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for DLCround-PT-10b-LTLFireability-03
lola: result : false
lola: markings : 205
lola: fired transitions : 206
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 DLCround-PT-10b-LTLFireability-09
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type FNDP) for DLCround-PT-10b-LTLFireability-07
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 32 (type EXCL) for DLCround-PT-10b-LTLFireability-09
lola: result : false
lola: markings : 204
lola: fired transitions : 204
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 DLCround-PT-10b-LTLFireability-11
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10b-LTLFireability-00: F false state space / EG
DLCround-PT-10b-LTLFireability-03: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-07: CONJ false state equation
DLCround-PT-10b-LTLFireability-09: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-10b-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-10b-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 LTL EXCL 4/276 1/32 DLCround-PT-10b-LTLFireability-11 10017 m, 2003 m/sec, 15676 t fired, .

Time elapsed: 13 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 38 (type EXCL) for DLCround-PT-10b-LTLFireability-11
lola: result : false
lola: markings : 10359
lola: fired transitions : 16218
lola: time used : 4.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 43 DLCround-PT-10b-LTLFireability-13
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for DLCround-PT-10b-LTLFireability-13
lola: result : false
lola: markings : 114
lola: fired transitions : 114
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 DLCround-PT-10b-LTLFireability-12
lola: time limit : 358 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for DLCround-PT-10b-LTLFireability-12
lola: result : false
lola: markings : 1794
lola: fired transitions : 1889
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 DLCround-PT-10b-LTLFireability-10
lola: time limit : 398 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10b-LTLFireability-00: F false state space / EG
DLCround-PT-10b-LTLFireability-03: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-07: CONJ false state equation
DLCround-PT-10b-LTLFireability-09: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-11: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-12: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-13: CONJ false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCround-PT-10b-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-10b-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 LTL EXCL 5/398 4/32 DLCround-PT-10b-LTLFireability-10 285500 m, 57100 m/sec, 371685 t fired, .

Time elapsed: 18 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10b-LTLFireability-00: F false state space / EG
DLCround-PT-10b-LTLFireability-03: LTL false LTL model checker
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DLCround-PT-10b-LTLFireability-05: LTL true LTL model checker
DLCround-PT-10b-LTLFireability-06: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-07: CONJ false state equation
DLCround-PT-10b-LTLFireability-09: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-11: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-12: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-13: CONJ false LTL model checker
DLCround-PT-10b-LTLFireability-14: F false state space / EG
DLCround-PT-10b-LTLFireability-15: LTL false LTL model checker

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DLCround-PT-10b-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
DLCround-PT-10b-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
DLCround-PT-10b-LTLFireability-10: LTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 845/3497 32/32 DLCround-PT-10b-LTLFireability-01 4557817 m, 6281 m/sec, 6814549 t fired, .

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DLCround-PT-10b-LTLFireability-00: F false state space / EG
DLCround-PT-10b-LTLFireability-02: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-03: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-04: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-05: LTL true LTL model checker
DLCround-PT-10b-LTLFireability-06: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-07: CONJ false state equation
DLCround-PT-10b-LTLFireability-09: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-11: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-12: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-13: CONJ false LTL model checker
DLCround-PT-10b-LTLFireability-14: F false state space / EG
DLCround-PT-10b-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
DLCround-PT-10b-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
DLCround-PT-10b-LTLFireability-10: LTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 850/3497 32/32 DLCround-PT-10b-LTLFireability-01 4589322 m, 6301 m/sec, 6860858 t fired, .

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DLCround-PT-10b-LTLFireability-02: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-03: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-04: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-05: LTL true LTL model checker
DLCround-PT-10b-LTLFireability-06: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-07: CONJ false state equation
DLCround-PT-10b-LTLFireability-09: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-11: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-12: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-13: CONJ false LTL model checker
DLCround-PT-10b-LTLFireability-14: F false state space / EG
DLCround-PT-10b-LTLFireability-15: LTL false LTL model checker

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DLCround-PT-10b-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
DLCround-PT-10b-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
DLCround-PT-10b-LTLFireability-10: LTL 0 0 0 0 1 0 1 0

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4 LTL EXCL 855/3497 32/32 DLCround-PT-10b-LTLFireability-01 4619037 m, 5943 m/sec, 6904570 t fired, .

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DLCround-PT-10b-LTLFireability-02: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-03: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-04: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-05: LTL true LTL model checker
DLCround-PT-10b-LTLFireability-06: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-07: CONJ false state equation
DLCround-PT-10b-LTLFireability-09: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-11: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-12: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-13: CONJ false LTL model checker
DLCround-PT-10b-LTLFireability-14: F false state space / EG
DLCround-PT-10b-LTLFireability-15: LTL false LTL model checker

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DLCround-PT-10b-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
DLCround-PT-10b-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
DLCround-PT-10b-LTLFireability-10: LTL 0 0 0 0 1 0 1 0

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4 LTL EXCL 860/3497 32/32 DLCround-PT-10b-LTLFireability-01 4648623 m, 5917 m/sec, 6947911 t fired, .

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DLCround-PT-10b-LTLFireability-00: F false state space / EG
DLCround-PT-10b-LTLFireability-02: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-03: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-04: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-05: LTL true LTL model checker
DLCround-PT-10b-LTLFireability-06: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-07: CONJ false state equation
DLCround-PT-10b-LTLFireability-09: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-11: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-12: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-13: CONJ false LTL model checker
DLCround-PT-10b-LTLFireability-14: F false state space / EG
DLCround-PT-10b-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
DLCround-PT-10b-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
DLCround-PT-10b-LTLFireability-10: LTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 865/3497 32/32 DLCround-PT-10b-LTLFireability-01 4678049 m, 5885 m/sec, 6991057 t fired, .

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DLCround-PT-10b-LTLFireability-00: F false state space / EG
DLCround-PT-10b-LTLFireability-02: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-03: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-04: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-05: LTL true LTL model checker
DLCround-PT-10b-LTLFireability-06: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-07: CONJ false state equation
DLCround-PT-10b-LTLFireability-09: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-11: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-12: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-13: CONJ false LTL model checker
DLCround-PT-10b-LTLFireability-14: F false state space / EG
DLCround-PT-10b-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
DLCround-PT-10b-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
DLCround-PT-10b-LTLFireability-10: LTL 0 0 0 0 1 0 1 0

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10b-LTLFireability-00: F false state space / EG
DLCround-PT-10b-LTLFireability-01: LTL unknown AGGR
DLCround-PT-10b-LTLFireability-02: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-03: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-04: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-05: LTL true LTL model checker
DLCround-PT-10b-LTLFireability-06: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-07: CONJ false state equation
DLCround-PT-10b-LTLFireability-08: LTL unknown AGGR
DLCround-PT-10b-LTLFireability-09: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-10: LTL unknown AGGR
DLCround-PT-10b-LTLFireability-11: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-12: LTL false LTL model checker
DLCround-PT-10b-LTLFireability-13: CONJ false LTL model checker
DLCround-PT-10b-LTLFireability-14: F false state space / EG
DLCround-PT-10b-LTLFireability-15: LTL false LTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-10b"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCround-PT-10b, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477300740"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-10b.tgz
mv DLCround-PT-10b execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;