fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r102-tall-167814477200698
Last Updated
May 14, 2023

About the Execution of LoLA for DLCround-PT-08a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16223.951 819903.00 812516.00 13488.70 ????????F?F??T?F normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477200698.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCround-PT-08a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477200698
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 948K
-rw-r--r-- 1 mcc users 6.4K Feb 25 19:02 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 19:02 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 18:44 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 25 18:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 19:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 151K Feb 25 19:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 25 19:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Feb 25 19:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 479K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-08a-CTLFireability-00
FORMULA_NAME DLCround-PT-08a-CTLFireability-01
FORMULA_NAME DLCround-PT-08a-CTLFireability-02
FORMULA_NAME DLCround-PT-08a-CTLFireability-03
FORMULA_NAME DLCround-PT-08a-CTLFireability-04
FORMULA_NAME DLCround-PT-08a-CTLFireability-05
FORMULA_NAME DLCround-PT-08a-CTLFireability-06
FORMULA_NAME DLCround-PT-08a-CTLFireability-07
FORMULA_NAME DLCround-PT-08a-CTLFireability-08
FORMULA_NAME DLCround-PT-08a-CTLFireability-09
FORMULA_NAME DLCround-PT-08a-CTLFireability-10
FORMULA_NAME DLCround-PT-08a-CTLFireability-11
FORMULA_NAME DLCround-PT-08a-CTLFireability-12
FORMULA_NAME DLCround-PT-08a-CTLFireability-13
FORMULA_NAME DLCround-PT-08a-CTLFireability-14
FORMULA_NAME DLCround-PT-08a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678317580123

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-08a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCround-PT-08a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA DLCround-PT-08a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-08a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-08a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-08a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678318400026

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 60 (type SKEL/SRCH) for 43 DLCround-PT-08a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 60 (type SKEL/SRCH) for DLCround-PT-08a-CTLFireability-13
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:746
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 7 (type EXCL) for 6 DLCround-PT-08a-CTLFireability-02
lola: time limit : 150 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 63 (type FNDP) for 53 DLCround-PT-08a-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type EQUN) for 53 DLCround-PT-08a-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SRCH) for 53 DLCround-PT-08a-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 63 (type FNDP) for DLCround-PT-08a-CTLFireability-15
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 64 (type EQUN) for DLCround-PT-08a-CTLFireability-15 (obsolete)
lola: CANCELED task # 67 (type SRCH) for DLCround-PT-08a-CTLFireability-15 (obsolete)
lola: FINISHED task # 67 (type SRCH) for DLCround-PT-08a-CTLFireability-15
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: try reading problem file /home/mcc/execution/CTLFireability-64.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 64 (type EQUN) for DLCround-PT-08a-CTLFireability-15
lola: result : true
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-CTLFireability-15: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/225 2/32 DLCround-PT-08a-CTLFireability-02 368294 m, 73658 m/sec, 5782014 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/225 3/32 DLCround-PT-08a-CTLFireability-02 716127 m, 69566 m/sec, 12192406 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/225 5/32 DLCround-PT-08a-CTLFireability-02 1000692 m, 56913 m/sec, 18544294 t fired, .

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DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/225 6/32 DLCround-PT-08a-CTLFireability-02 1300776 m, 60016 m/sec, 24900166 t fired, .

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DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/225 7/32 DLCround-PT-08a-CTLFireability-02 1574233 m, 54691 m/sec, 31207694 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 30/225 8/32 DLCround-PT-08a-CTLFireability-02 1922948 m, 69743 m/sec, 37559223 t fired, .

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DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 35/225 10/32 DLCround-PT-08a-CTLFireability-02 2282543 m, 71919 m/sec, 43819731 t fired, .

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DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 40/225 11/32 DLCround-PT-08a-CTLFireability-02 2584555 m, 60402 m/sec, 49997777 t fired, .

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DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 45/225 12/32 DLCround-PT-08a-CTLFireability-02 2854262 m, 53941 m/sec, 56168063 t fired, .

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DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 50/225 14/32 DLCround-PT-08a-CTLFireability-02 3143888 m, 57925 m/sec, 62518142 t fired, .

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DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 55/225 15/32 DLCround-PT-08a-CTLFireability-02 3414905 m, 54203 m/sec, 68771902 t fired, .

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DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 60/225 16/32 DLCround-PT-08a-CTLFireability-02 3659227 m, 48864 m/sec, 74974580 t fired, .

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DLCround-PT-08a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 1
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 135/225 31/32 DLCround-PT-08a-CTLFireability-02 7393760 m, 70272 m/sec, 169075134 t fired, .

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7 CTL EXCL 140/225 32/32 DLCround-PT-08a-CTLFireability-02 7715073 m, 64262 m/sec, 175732288 t fired, .

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DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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41 CTL EXCL 5/246 2/32 DLCround-PT-08a-CTLFireability-12 337517 m, 67503 m/sec, 7749559 t fired, .

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41 CTL EXCL 10/246 3/32 DLCround-PT-08a-CTLFireability-12 666199 m, 65736 m/sec, 15305962 t fired, .

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41 CTL EXCL 15/246 5/32 DLCround-PT-08a-CTLFireability-12 990482 m, 64856 m/sec, 22677923 t fired, .

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41 CTL EXCL 20/246 6/32 DLCround-PT-08a-CTLFireability-12 1308924 m, 63688 m/sec, 29983284 t fired, .

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41 CTL EXCL 25/246 7/32 DLCround-PT-08a-CTLFireability-12 1622055 m, 62626 m/sec, 37201309 t fired, .

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41 CTL EXCL 30/246 8/32 DLCround-PT-08a-CTLFireability-12 1864319 m, 48452 m/sec, 44822753 t fired, .

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41 CTL EXCL 35/246 9/32 DLCround-PT-08a-CTLFireability-12 2064095 m, 39955 m/sec, 52497388 t fired, .

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41 CTL EXCL 40/246 10/32 DLCround-PT-08a-CTLFireability-12 2260474 m, 39275 m/sec, 60105187 t fired, .

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41 CTL EXCL 45/246 11/32 DLCround-PT-08a-CTLFireability-12 2460373 m, 39979 m/sec, 67670164 t fired, .

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41 CTL EXCL 50/246 11/32 DLCround-PT-08a-CTLFireability-12 2653545 m, 38634 m/sec, 75199118 t fired, .

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41 CTL EXCL 55/246 12/32 DLCround-PT-08a-CTLFireability-12 2843161 m, 37923 m/sec, 82674555 t fired, .

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41 CTL EXCL 165/246 32/32 DLCround-PT-08a-CTLFireability-12 7619035 m, 38101 m/sec, 250287701 t fired, .

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38 CTL EXCL 5/252 1/32 DLCround-PT-08a-CTLFireability-11 12790 m, 2558 m/sec, 434588 t fired, .

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38 CTL EXCL 30/252 7/32 DLCround-PT-08a-CTLFireability-11 1678637 m, 100704 m/sec, 27721916 t fired, .

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38 CTL EXCL 35/252 9/32 DLCround-PT-08a-CTLFireability-11 2165222 m, 97317 m/sec, 35677066 t fired, .

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38 CTL EXCL 40/252 12/32 DLCround-PT-08a-CTLFireability-11 2667063 m, 100368 m/sec, 43852106 t fired, .

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32 CTL EXCL 5/290 3/32 DLCround-PT-08a-CTLFireability-09 514871 m, 102974 m/sec, 8270994 t fired, .

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32 CTL EXCL 10/290 3/32 DLCround-PT-08a-CTLFireability-09 644737 m, 25973 m/sec, 15763861 t fired, .

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32 CTL EXCL 15/290 4/32 DLCround-PT-08a-CTLFireability-09 764429 m, 23938 m/sec, 22767329 t fired, .

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32 CTL EXCL 20/290 4/32 DLCround-PT-08a-CTLFireability-09 883911 m, 23896 m/sec, 29853019 t fired, .

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32 CTL EXCL 25/290 5/32 DLCround-PT-08a-CTLFireability-09 1020323 m, 27282 m/sec, 36694643 t fired, .

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32 CTL EXCL 30/290 5/32 DLCround-PT-08a-CTLFireability-09 1173378 m, 30611 m/sec, 43655086 t fired, .

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32 CTL EXCL 35/290 7/32 DLCround-PT-08a-CTLFireability-09 1460237 m, 57371 m/sec, 50954250 t fired, .

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32 CTL EXCL 40/290 9/32 DLCround-PT-08a-CTLFireability-09 1944086 m, 96769 m/sec, 58930432 t fired, .

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32 CTL EXCL 75/290 23/32 DLCround-PT-08a-CTLFireability-09 5343788 m, 96989 m/sec, 114395672 t fired, .

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32 CTL EXCL 80/290 24/32 DLCround-PT-08a-CTLFireability-09 5810756 m, 93393 m/sec, 122164840 t fired, .

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32 CTL EXCL 95/290 30/32 DLCround-PT-08a-CTLFireability-09 7180549 m, 90021 m/sec, 145149852 t fired, .

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32 CTL EXCL 100/290 32/32 DLCround-PT-08a-CTLFireability-09 7650247 m, 93939 m/sec, 152866108 t fired, .

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29 CTL EXCL 5/308 3/32 DLCround-PT-08a-CTLFireability-08 519876 m, 103975 m/sec, 8721719 t fired, .

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29 CTL EXCL 10/308 5/32 DLCround-PT-08a-CTLFireability-08 991891 m, 94403 m/sec, 16760827 t fired, .

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29 CTL EXCL 40/308 16/32 DLCround-PT-08a-CTLFireability-08 3794411 m, 90576 m/sec, 64759850 t fired, .

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29 CTL EXCL 45/308 18/32 DLCround-PT-08a-CTLFireability-08 4264053 m, 93928 m/sec, 72703456 t fired, .

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4 CTL EXCL 51/360 14/32 DLCround-PT-08a-CTLFireability-01 3220675 m, 59478 m/sec, 75759265 t fired, .

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4 CTL EXCL 56/360 15/32 DLCround-PT-08a-CTLFireability-01 3541704 m, 64205 m/sec, 82203337 t fired, .

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4 CTL EXCL 61/360 17/32 DLCround-PT-08a-CTLFireability-01 3890636 m, 69786 m/sec, 89371140 t fired, .

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/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 376 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-08a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCround-PT-08a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477200698"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-08a.tgz
mv DLCround-PT-08a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;