fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r102-tall-167814477100618
Last Updated
May 14, 2023

About the Execution of LoLA for DLCround-PT-03a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5175.991 215036.00 218161.00 986.80 FTFF?FTTTTTFFTT? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477100618.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCround-PT-03a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477100618
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 580K
-rw-r--r-- 1 mcc users 6.2K Feb 25 18:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 25 18:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 18:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K Feb 25 18:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.1K Feb 25 18:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 25 18:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 18:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 108K Feb 25 18:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 148K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-03a-CTLFireability-00
FORMULA_NAME DLCround-PT-03a-CTLFireability-01
FORMULA_NAME DLCround-PT-03a-CTLFireability-02
FORMULA_NAME DLCround-PT-03a-CTLFireability-03
FORMULA_NAME DLCround-PT-03a-CTLFireability-04
FORMULA_NAME DLCround-PT-03a-CTLFireability-05
FORMULA_NAME DLCround-PT-03a-CTLFireability-06
FORMULA_NAME DLCround-PT-03a-CTLFireability-07
FORMULA_NAME DLCround-PT-03a-CTLFireability-08
FORMULA_NAME DLCround-PT-03a-CTLFireability-09
FORMULA_NAME DLCround-PT-03a-CTLFireability-10
FORMULA_NAME DLCround-PT-03a-CTLFireability-11
FORMULA_NAME DLCround-PT-03a-CTLFireability-12
FORMULA_NAME DLCround-PT-03a-CTLFireability-13
FORMULA_NAME DLCround-PT-03a-CTLFireability-14
FORMULA_NAME DLCround-PT-03a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678309036076

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-03a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCround-PT-03a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA DLCround-PT-03a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678309251112

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: LAUNCH task # 80 (type SKEL/SRCH) for 6 DLCround-PT-03a-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 80 (type SKEL/SRCH) for DLCround-PT-03a-CTLFireability-02
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 81 (type SKEL/SRCH) for 48 DLCround-PT-03a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 81 (type SKEL/SRCH) for DLCround-PT-03a-CTLFireability-08
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 40 (type EXCL) for 19 DLCround-PT-03a-CTLFireability-05
lola: time limit : 116 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for DLCround-PT-03a-CTLFireability-05
lola: result : false
lola: markings : 1
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 DLCround-PT-03a-CTLFireability-03
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 83 (type FNDP) for 19 DLCround-PT-03a-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type EQUN) for 19 DLCround-PT-03a-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 86 (type SRCH) for 19 DLCround-PT-03a-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 83 (type FNDP) for DLCround-PT-03a-CTLFireability-05
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 84 (type EQUN) for DLCround-PT-03a-CTLFireability-05 (obsolete)
lola: CANCELED task # 86 (type SRCH) for DLCround-PT-03a-CTLFireability-05 (obsolete)
lola: FINISHED task # 14 (type EXCL) for DLCround-PT-03a-CTLFireability-03
lola: result : false
lola: markings : 4
lola: fired transitions : 29
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 86 (type SRCH) for DLCround-PT-03a-CTLFireability-05
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: try reading problem file /home/mcc/execution/CTLFireability-84.sara.
lola: planning for (null) stopped (result already fixed).
sara: place or transition ordering is non-deterministic

lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 84 (type EQUN) for DLCround-PT-03a-CTLFireability-05
lola: result : true
lola: LAUNCH task # 60 (type EXCL) for 59 DLCround-PT-03a-CTLFireability-09
lola: time limit : 150 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for DLCround-PT-03a-CTLFireability-09
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 DLCround-PT-03a-CTLFireability-07
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 46 (type EXCL) for DLCround-PT-03a-CTLFireability-07
lola: result : true
lola: markings : 115
lola: fired transitions : 1718
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 55 (type EXCL) for 48 DLCround-PT-03a-CTLFireability-08
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 55 (type EXCL) for DLCround-PT-03a-CTLFireability-08
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 75 (type EXCL) for 74 DLCround-PT-03a-CTLFireability-14
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 75 (type EXCL) for DLCround-PT-03a-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 66 (type EXCL) for 65 DLCround-PT-03a-CTLFireability-11
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: NOTDEADLOCKFREE
lola: FINISHED task # 66 (type EXCL) for DLCround-PT-03a-CTLFireability-11
lola: result : false
lola: markings : 92792
lola: fired transitions : 1425565
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 78 (type EXCL) for 77 DLCround-PT-03a-CTLFireability-15
lola: time limit : 327 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03a-CTLFireability-03: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-05: CONJ false findpath
DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-03a-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 CTL EXCL 4/327 2/32 DLCround-PT-03a-CTLFireability-15 466574 m, 93314 m/sec, 7715720 t fired, .

Time elapsed: 5 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03a-CTLFireability-03: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-05: CONJ false findpath
DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-03a-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 CTL EXCL 9/327 5/32 DLCround-PT-03a-CTLFireability-15 967549 m, 100195 m/sec, 16426782 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03a-CTLFireability-03: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-05: CONJ false findpath
DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-03a-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 CTL EXCL 14/327 7/32 DLCround-PT-03a-CTLFireability-15 1448984 m, 96287 m/sec, 25082294 t fired, .

Time elapsed: 15 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03a-CTLFireability-03: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-05: CONJ false findpath
DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-03a-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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78 CTL EXCL 19/327 9/32 DLCround-PT-03a-CTLFireability-15 1918495 m, 93902 m/sec, 33581118 t fired, .

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78 CTL EXCL 24/327 10/32 DLCround-PT-03a-CTLFireability-15 2356579 m, 87616 m/sec, 41788613 t fired, .

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78 CTL EXCL 29/327 12/32 DLCround-PT-03a-CTLFireability-15 2787966 m, 86277 m/sec, 50010760 t fired, .

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78 CTL EXCL 34/327 14/32 DLCround-PT-03a-CTLFireability-15 3208181 m, 84043 m/sec, 58109830 t fired, .

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78 CTL EXCL 39/327 16/32 DLCround-PT-03a-CTLFireability-15 3628548 m, 84073 m/sec, 66099950 t fired, .

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78 CTL EXCL 44/327 17/32 DLCround-PT-03a-CTLFireability-15 4026334 m, 79557 m/sec, 73975421 t fired, .

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78 CTL EXCL 49/327 19/32 DLCround-PT-03a-CTLFireability-15 4435838 m, 81900 m/sec, 81957421 t fired, .

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78 CTL EXCL 54/327 21/32 DLCround-PT-03a-CTLFireability-15 4828540 m, 78540 m/sec, 89639116 t fired, .

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78 CTL EXCL 59/327 22/32 DLCround-PT-03a-CTLFireability-15 5202325 m, 74757 m/sec, 97324581 t fired, .

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17 CTL EXCL 10/438 4/32 DLCround-PT-03a-CTLFireability-04 916528 m, 91402 m/sec, 18037551 t fired, .

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17 CTL EXCL 15/438 6/32 DLCround-PT-03a-CTLFireability-04 1361040 m, 88902 m/sec, 26630552 t fired, .

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DLCround-PT-03a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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17 CTL EXCL 70/438 24/32 DLCround-PT-03a-CTLFireability-04 5741095 m, 74033 m/sec, 109513259 t fired, .

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DLCround-PT-03a-CTLFireability-05: CONJ false findpath
DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker

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17 CTL EXCL 75/438 26/32 DLCround-PT-03a-CTLFireability-04 6097988 m, 71378 m/sec, 116161765 t fired, .

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DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
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17 CTL EXCL 80/438 27/32 DLCround-PT-03a-CTLFireability-04 6462168 m, 72836 m/sec, 122884458 t fired, .

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DLCround-PT-03a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
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17 CTL EXCL 85/438 29/32 DLCround-PT-03a-CTLFireability-04 6818777 m, 71321 m/sec, 129421944 t fired, .

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DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker

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17 CTL EXCL 90/438 30/32 DLCround-PT-03a-CTLFireability-04 7152985 m, 66841 m/sec, 135400021 t fired, .

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DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
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17 CTL EXCL 95/438 31/32 DLCround-PT-03a-CTLFireability-04 7439881 m, 57379 m/sec, 141277665 t fired, .

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DLCround-PT-03a-CTLFireability-05: CONJ false findpath
DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker

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lola: result : false
lola: markings : 6
lola: fired transitions : 9
lola: time used : 0.000000
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DLCround-PT-03a-CTLFireability-05: CONJ false findpath
DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker

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1 CTL EXCL 5/567 3/32 DLCround-PT-03a-CTLFireability-00 648832 m, 129766 m/sec, 10635555 t fired, .

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DLCround-PT-03a-CTLFireability-05: CONJ false findpath
DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker

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1 CTL EXCL 10/567 6/32 DLCround-PT-03a-CTLFireability-00 1221822 m, 114598 m/sec, 20441984 t fired, .

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DLCround-PT-03a-CTLFireability-03: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-05: CONJ false findpath
DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker

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1 CTL EXCL 15/567 8/32 DLCround-PT-03a-CTLFireability-00 1762259 m, 108087 m/sec, 29972372 t fired, .

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lola: FINISHED task # 1 (type EXCL) for DLCround-PT-03a-CTLFireability-00
lola: result : false
lola: markings : 1934494
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lola: time used : 17.000000
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lola: FINISHED task # 87 (type EXCL) for DLCround-PT-03a-CTLFireability-10
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-03a-CTLFireability-01
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lola: FINISHED task # 4 (type EXCL) for DLCround-PT-03a-CTLFireability-01
lola: result : true
lola: markings : 280459
lola: fired transitions : 5782522
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 43 (type EXCL) for 42 DLCround-PT-03a-CTLFireability-06
lola: time limit : 1128 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for DLCround-PT-03a-CTLFireability-06
lola: result : true
lola: markings : 2
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 69 (type EXCL) for 68 DLCround-PT-03a-CTLFireability-12
lola: time limit : 1693 sec
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lola: FINISHED task # 69 (type EXCL) for DLCround-PT-03a-CTLFireability-12
lola: result : false
lola: markings : 2
lola: fired transitions : 5
lola: time used : 0.000000
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lola: time limit : 3386 sec
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lola: FINISHED task # 72 (type EXCL) for DLCround-PT-03a-CTLFireability-13
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03a-CTLFireability-00: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-01: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-02: DISJ false DISJ
DLCround-PT-03a-CTLFireability-03: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-04: CTL unknown AGGR
DLCround-PT-03a-CTLFireability-05: CONJ false findpath
DLCround-PT-03a-CTLFireability-06: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-07: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-03a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-10: F true state space / EG
DLCround-PT-03a-CTLFireability-11: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-03a-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-03a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCround-PT-03a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477100618"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-03a.tgz
mv DLCround-PT-03a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;