About the Execution of LoLA for DLCflexbar-PT-5b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16227.000 | 569599.00 | 1310767.00 | 15084.50 | ???????????T???? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477100562.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-5b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477100562
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 7.0M
-rw-r--r-- 1 mcc users 6.4K Feb 25 15:07 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 25 15:07 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 25 15:07 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 25 15:07 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 15:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 143K Feb 25 15:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 15:08 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 99K Feb 25 15:08 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 6.5M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-5b-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678300339202
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-5b
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-5b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DLCflexbar-PT-5b-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678300908801
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:448
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-11: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 186 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 6.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-11: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 191 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 6.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-11: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 196 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 6.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-11: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-11: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-11: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
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DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-11: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-11: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-11: DISJ 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-11: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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lola: result : true
lola: markings : 2
lola: fired transitions : 1
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lola: memory pages used : 1
lola: CANCELED task # 72 (type FNDP) for DLCflexbar-PT-5b-CTLFireability-11 (obsolete)
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DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-5b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 1 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-5b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 1 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 1 0 2 0 0 0
DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
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DLCflexbar-PT-5b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-5b-CTLFireability-08: CONJ 0 0 1 0 2 0 0 0
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DLCflexbar-PT-5b-CTLFireability-05: DISJ 0 0 0 0 3 0 0 0
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35 AGEF EXCL 100/175 3/32 DLCflexbar-PT-5b-CTLFireability-08 308056 m, 251 m/sec, 1992198 t fired, .
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35 AGEF EXCL 105/175 3/32 DLCflexbar-PT-5b-CTLFireability-08 309318 m, 252 m/sec, 2000373 t fired, .
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35 AGEF EXCL 114/175 3/32 DLCflexbar-PT-5b-CTLFireability-08 311532 m, 442 m/sec, 2015582 t fired, .
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/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 376 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-5b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-5b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477100562"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-5b.tgz
mv DLCflexbar-PT-5b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;