fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r102-tall-167814477000540
Last Updated
May 14, 2023

About the Execution of LoLA for DLCflexbar-PT-4a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
566.376 4409.00 11686.00 12.70 FFFTFFFFFFFFTTFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477000540.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-4a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477000540
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.1M
-rw-r--r-- 1 mcc users 7.3K Feb 25 16:05 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 16:05 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 25 15:30 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 25 15:30 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.1K Feb 25 16:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 25 16:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.6K Feb 25 16:32 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 25 16:32 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.7M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-00
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-01
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-02
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-03
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-04
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-05
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-06
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-07
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-08
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-09
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-10
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-11
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-12
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-13
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-14
FORMULA_NAME DLCflexbar-PT-4a-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1678298051798

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-4a
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-4a
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA DLCflexbar-PT-4a-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678298056207

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 70 (type SKEL/FNDP) for 0 DLCflexbar-PT-4a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SKEL/EQUN) for 0 DLCflexbar-PT-4a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 72 (type SKEL/SRCH) for 0 DLCflexbar-PT-4a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SKEL/SRCH) for 0 DLCflexbar-PT-4a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 70 (type SKEL/FNDP) for DLCflexbar-PT-4a-LTLFireability-00
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 71 (type EQUN) for DLCflexbar-PT-4a-LTLFireability-00 (obsolete)
lola: CANCELED task # 72 (type SRCH) for DLCflexbar-PT-4a-LTLFireability-00 (obsolete)
lola: CANCELED task # 73 (type SRCH) for DLCflexbar-PT-4a-LTLFireability-00 (obsolete)
lola: FINISHED task # 73 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/LTLFireability-71.sara.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
sara: place or transition ordering is non-deterministic

lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 71 (type SKEL/EQUN) for DLCflexbar-PT-4a-LTLFireability-00
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 76 (type SKEL/FNDP) for 23 DLCflexbar-PT-4a-LTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SKEL/EQUN) for 23 DLCflexbar-PT-4a-LTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 78 (type SKEL/SRCH) for 23 DLCflexbar-PT-4a-LTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 79 (type SKEL/SRCH) for 23 DLCflexbar-PT-4a-LTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 78 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLFireability-05
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 76 (type FNDP) for DLCflexbar-PT-4a-LTLFireability-05 (obsolete)
lola: CANCELED task # 77 (type EQUN) for DLCflexbar-PT-4a-LTLFireability-05 (obsolete)
lola: CANCELED task # 79 (type SRCH) for DLCflexbar-PT-4a-LTLFireability-05 (obsolete)
lola: FINISHED task # 79 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLFireability-05
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 76 (type SKEL/FNDP) for DLCflexbar-PT-4a-LTLFireability-05
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/LTLFireability-77.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 77 (type SKEL/EQUN) for DLCflexbar-PT-4a-LTLFireability-05
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 80 (type SKEL/SRCH) for 23 DLCflexbar-PT-4a-LTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 80 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLFireability-05
lola: result : false
lola: markings : 61
lola: fired transitions : 61
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 81 (type SKEL/SRCH) for 36 DLCflexbar-PT-4a-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 81 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLFireability-08
lola: result : false
lola: markings : 114
lola: fired transitions : 358
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 84 (type SKEL/FNDP) for 61 DLCflexbar-PT-4a-LTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SKEL/EQUN) for 61 DLCflexbar-PT-4a-LTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type SKEL/SRCH) for 61 DLCflexbar-PT-4a-LTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type SKEL/SRCH) for 61 DLCflexbar-PT-4a-LTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/LTLFireability-85.sara.
lola: FINISHED task # 84 (type SKEL/FNDP) for DLCflexbar-PT-4a-LTLFireability-15
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 85 (type EQUN) for DLCflexbar-PT-4a-LTLFireability-15 (obsolete)
lola: CANCELED task # 86 (type SRCH) for DLCflexbar-PT-4a-LTLFireability-15 (obsolete)
lola: CANCELED task # 87 (type SRCH) for DLCflexbar-PT-4a-LTLFireability-15 (obsolete)
lola: FINISHED task # 85 (type SKEL/EQUN) for DLCflexbar-PT-4a-LTLFireability-15
lola: result : unknown
lola: FINISHED task # 87 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLFireability-15
lola: result : unknown
lola: time used : 1.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 91 (type EXCL) for 23 DLCflexbar-PT-4a-LTLFireability-05
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 89 (type FNDP) for 23 DLCflexbar-PT-4a-LTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type EQUN) for 23 DLCflexbar-PT-4a-LTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 92 (type SRCH) for 23 DLCflexbar-PT-4a-LTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 92 (type SRCH) for DLCflexbar-PT-4a-LTLFireability-05
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 91 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-05
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 89 (type FNDP) for DLCflexbar-PT-4a-LTLFireability-05 (obsolete)
lola: CANCELED task # 90 (type EQUN) for DLCflexbar-PT-4a-LTLFireability-05 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 96 (type EXCL) for 0 DLCflexbar-PT-4a-LTLFireability-00
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 94 (type FNDP) for 0 DLCflexbar-PT-4a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 95 (type EQUN) for 0 DLCflexbar-PT-4a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 97 (type SRCH) for 0 DLCflexbar-PT-4a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 96 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-00
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 94 (type FNDP) for DLCflexbar-PT-4a-LTLFireability-00 (obsolete)
lola: CANCELED task # 95 (type EQUN) for DLCflexbar-PT-4a-LTLFireability-00 (obsolete)
lola: CANCELED task # 97 (type SRCH) for DLCflexbar-PT-4a-LTLFireability-00 (obsolete)
sara: try reading problem file /home/mcc/execution/LTLFireability-90.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 89 (type FNDP) for DLCflexbar-PT-4a-LTLFireability-05
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 90 (type EQUN) for DLCflexbar-PT-4a-LTLFireability-05
lola: result : true
lola: FINISHED task # 94 (type FNDP) for DLCflexbar-PT-4a-LTLFireability-00
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
sara: try reading problem file /home/mcc/execution/LTLFireability-95.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788

lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 95 (type EQUN) for DLCflexbar-PT-4a-LTLFireability-00
lola: result : true
lola: LAUNCH task # 101 (type EXCL) for 61 DLCflexbar-PT-4a-LTLFireability-15
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 99 (type FNDP) for 61 DLCflexbar-PT-4a-LTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 100 (type EQUN) for 61 DLCflexbar-PT-4a-LTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 102 (type SRCH) for 61 DLCflexbar-PT-4a-LTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 101 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-15
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 99 (type FNDP) for DLCflexbar-PT-4a-LTLFireability-15 (obsolete)
lola: CANCELED task # 100 (type EQUN) for DLCflexbar-PT-4a-LTLFireability-15 (obsolete)
lola: CANCELED task # 102 (type SRCH) for DLCflexbar-PT-4a-LTLFireability-15 (obsolete)
lola: FINISHED task # 99 (type FNDP) for DLCflexbar-PT-4a-LTLFireability-15
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/LTLFireability-100.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 100 (type EQUN) for DLCflexbar-PT-4a-LTLFireability-15
lola: result : true
lola: FINISHED task # 102 (type SRCH) for DLCflexbar-PT-4a-LTLFireability-15
lola: result : unknown
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 DLCflexbar-PT-4a-LTLFireability-08
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-08
lola: result : false
lola: markings : 37
lola: fired transitions : 304
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 6 DLCflexbar-PT-4a-LTLFireability-02
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:735
lola: rewrite Frontend/Parser/formula_rewrite.k:695
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 11 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-02
lola: result : false
lola: markings : 33
lola: fired transitions : 279
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 103 (type EXCL) for 42 DLCflexbar-PT-4a-LTLFireability-10
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 103 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 104 (type EXCL) for 49 DLCflexbar-PT-4a-LTLFireability-11
lola: time limit : 326 sec
lola: memory limit: 32 pages
lola: planning for (null) stopped (result already fixed).
lola: FINISHED task # 104 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-11
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 DLCflexbar-PT-4a-LTLFireability-07
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-07
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 DLCflexbar-PT-4a-LTLFireability-01
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-01
lola: result : false
lola: markings : 51
lola: fired transitions : 546
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 58 DLCflexbar-PT-4a-LTLFireability-14
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-14
lola: result : false
lola: markings : 37
lola: fired transitions : 305
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 16 DLCflexbar-PT-4a-LTLFireability-04
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-04
lola: result : false
lola: markings : 5
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 53 (type EXCL) for 52 DLCflexbar-PT-4a-LTLFireability-12
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-12
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 DLCflexbar-PT-4a-LTLFireability-03
lola: time limit : 898 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-03
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 55 DLCflexbar-PT-4a-LTLFireability-13
lola: time limit : 1198 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-13
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 DLCflexbar-PT-4a-LTLFireability-09
lola: time limit : 1797 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-09
lola: result : false
lola: markings : 5
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 DLCflexbar-PT-4a-LTLFireability-06
lola: time limit : 3595 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for DLCflexbar-PT-4a-LTLFireability-06
lola: result : false
lola: markings : 4
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-LTLFireability-00: AG false state space
DLCflexbar-PT-4a-LTLFireability-01: LTL false LTL model checker
DLCflexbar-PT-4a-LTLFireability-02: CONJ false LTL model checker
DLCflexbar-PT-4a-LTLFireability-03: LTL true LTL model checker
DLCflexbar-PT-4a-LTLFireability-04: CONJ false LTL model checker
DLCflexbar-PT-4a-LTLFireability-05: CONJ false state space
DLCflexbar-PT-4a-LTLFireability-06: LTL false LTL model checker
DLCflexbar-PT-4a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-4a-LTLFireability-08: LTL false LTL model checker
DLCflexbar-PT-4a-LTLFireability-09: LTL false LTL model checker
DLCflexbar-PT-4a-LTLFireability-10: CONJ false state space /ER
DLCflexbar-PT-4a-LTLFireability-11: F false state space / EG
DLCflexbar-PT-4a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-4a-LTLFireability-13: LTL true LTL model checker
DLCflexbar-PT-4a-LTLFireability-14: LTL false LTL model checker
DLCflexbar-PT-4a-LTLFireability-15: CONJ false state space


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-4a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-4a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477000540"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-4a.tgz
mv DLCflexbar-PT-4a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;