About the Execution of LoLA for DLCflexbar-PT-3a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 13007.976 | 736262.00 | 736626.00 | 4101.90 | FTT??FFFTFFFTTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477000524.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-3a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477000524
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 6.7K Feb 25 16:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 25 16:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 16:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 37K Feb 25 16:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 31K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 18:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 157K Feb 25 18:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.4K Feb 25 17:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 25 17:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 996K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-00
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-01
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-02
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-03
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-04
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-05
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-06
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-07
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-08
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-09
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-10
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-11
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-12
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-13
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-14
FORMULA_NAME DLCflexbar-PT-3a-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1678297190609
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-3a
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-3a
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability
FORMULA DLCflexbar-PT-3a-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678297926871
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:427
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:490
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 68 (type SKEL/SRCH) for 0 DLCflexbar-PT-3a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 68 (type SKEL/SRCH) for DLCflexbar-PT-3a-LTLFireability-00
lola: result : false
lola: markings : 84
lola: fired transitions : 278
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 69 (type SKEL/SRCH) for 0 DLCflexbar-PT-3a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 69 (type SKEL/SRCH) for DLCflexbar-PT-3a-LTLFireability-00
lola: result : false
lola: markings : 21
lola: fired transitions : 87
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 76 (type SKEL/FNDP) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SKEL/EQUN) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type SKEL/SRCH) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SKEL/SRCH) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 76 (type SKEL/FNDP) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 77 (type EQUN) for DLCflexbar-PT-3a-LTLFireability-10 (obsolete)
lola: CANCELED task # 78 (type SRCH) for DLCflexbar-PT-3a-LTLFireability-10 (obsolete)
lola: CANCELED task # 79 (type SRCH) for DLCflexbar-PT-3a-LTLFireability-10 (obsolete)
lola: LAUNCH task # 72 (type SKEL/FNDP) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SKEL/EQUN) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type SKEL/SRCH) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SKEL/SRCH) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 79 (type SKEL/SRCH) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 81 (type SKEL/SRCH) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
sara: try reading problem file /home/mcc/execution/LTLFireability-77.sara.
sara: try reading problem file /home/mcc/execution/LTLFireability-73.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 73 (type SKEL/EQUN) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : true
lola: CANCELED task # 72 (type FNDP) for DLCflexbar-PT-3a-LTLFireability-10 (obsolete)
lola: CANCELED task # 80 (type SRCH) for DLCflexbar-PT-3a-LTLFireability-10 (obsolete)
lola: FINISHED task # 72 (type SKEL/FNDP) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 80 (type SKEL/SRCH) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 77 (type SKEL/EQUN) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 85 (type EXCL) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 83 (type FNDP) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type EQUN) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type SRCH) for 42 DLCflexbar-PT-3a-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 85 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 83 (type FNDP) for DLCflexbar-PT-3a-LTLFireability-10 (obsolete)
lola: CANCELED task # 84 (type EQUN) for DLCflexbar-PT-3a-LTLFireability-10 (obsolete)
lola: CANCELED task # 86 (type SRCH) for DLCflexbar-PT-3a-LTLFireability-10 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
sara: try reading problem file /home/mcc/execution/LTLFireability-84.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 86 (type SRCH) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : unknown
lola: time used : 1.000000
lola: memory pages used : 1
lola: FINISHED task # 83 (type FNDP) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 92 (type EXCL) for 22 DLCflexbar-PT-3a-LTLFireability-06
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 88 (type FNDP) for 22 DLCflexbar-PT-3a-LTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 91 (type EQUN) for 22 DLCflexbar-PT-3a-LTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 93 (type SRCH) for 22 DLCflexbar-PT-3a-LTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 84 (type EQUN) for DLCflexbar-PT-3a-LTLFireability-10
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 92 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-06
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 88 (type FNDP) for DLCflexbar-PT-3a-LTLFireability-06 (obsolete)
lola: CANCELED task # 91 (type EQUN) for DLCflexbar-PT-3a-LTLFireability-06 (obsolete)
lola: CANCELED task # 93 (type SRCH) for DLCflexbar-PT-3a-LTLFireability-06 (obsolete)
lola: LAUNCH task # 34 (type EXCL) for 33 DLCflexbar-PT-3a-LTLFireability-07
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 93 (type SRCH) for DLCflexbar-PT-3a-LTLFireability-06
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 34 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-07
lola: result : false
lola: markings : 41
lola: fired transitions : 875
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/LTLFireability-91.sara.
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 3 (type EXCL) for 0 DLCflexbar-PT-3a-LTLFireability-00
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 91 (type EQUN) for DLCflexbar-PT-3a-LTLFireability-06
lola: result : true
lola: FINISHED task # 88 (type FNDP) for DLCflexbar-PT-3a-LTLFireability-06
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 3/257 1/32 DLCflexbar-PT-3a-LTLFireability-00 97956 m, 19591 m/sec, 4076257 t fired, .
Time elapsed: 5 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 8/257 2/32 DLCflexbar-PT-3a-LTLFireability-00 255970 m, 31602 m/sec, 9655631 t fired, .
Time elapsed: 10 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 13/257 3/32 DLCflexbar-PT-3a-LTLFireability-00 381337 m, 25073 m/sec, 15101413 t fired, .
Time elapsed: 15 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 18/257 4/32 DLCflexbar-PT-3a-LTLFireability-00 503917 m, 24516 m/sec, 20560685 t fired, .
Time elapsed: 20 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 23/257 5/32 DLCflexbar-PT-3a-LTLFireability-00 626058 m, 24428 m/sec, 26113915 t fired, .
Time elapsed: 25 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 28/257 6/32 DLCflexbar-PT-3a-LTLFireability-00 747447 m, 24277 m/sec, 31707743 t fired, .
Time elapsed: 30 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 33/257 7/32 DLCflexbar-PT-3a-LTLFireability-00 872605 m, 25031 m/sec, 37358890 t fired, .
Time elapsed: 35 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 38/257 8/32 DLCflexbar-PT-3a-LTLFireability-00 992079 m, 23894 m/sec, 42832654 t fired, .
Time elapsed: 40 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 43/257 9/32 DLCflexbar-PT-3a-LTLFireability-00 1113602 m, 24304 m/sec, 48243518 t fired, .
Time elapsed: 45 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 48/257 10/32 DLCflexbar-PT-3a-LTLFireability-00 1238013 m, 24882 m/sec, 53688142 t fired, .
Time elapsed: 50 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 53/257 11/32 DLCflexbar-PT-3a-LTLFireability-00 1352982 m, 22993 m/sec, 59084201 t fired, .
Time elapsed: 55 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 58/257 12/32 DLCflexbar-PT-3a-LTLFireability-00 1475118 m, 24427 m/sec, 64571235 t fired, .
Time elapsed: 60 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 63/257 13/32 DLCflexbar-PT-3a-LTLFireability-00 1603444 m, 25665 m/sec, 69973303 t fired, .
Time elapsed: 65 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 68/257 14/32 DLCflexbar-PT-3a-LTLFireability-00 1723447 m, 24000 m/sec, 75421019 t fired, .
Time elapsed: 70 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 73/257 15/32 DLCflexbar-PT-3a-LTLFireability-00 1857749 m, 26860 m/sec, 80725948 t fired, .
Time elapsed: 75 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 78/257 16/32 DLCflexbar-PT-3a-LTLFireability-00 1984750 m, 25400 m/sec, 86268877 t fired, .
Time elapsed: 80 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 83/257 17/32 DLCflexbar-PT-3a-LTLFireability-00 2110039 m, 25057 m/sec, 91867988 t fired, .
Time elapsed: 85 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 88/257 18/32 DLCflexbar-PT-3a-LTLFireability-00 2231428 m, 24277 m/sec, 97290957 t fired, .
Time elapsed: 90 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 93/257 18/32 DLCflexbar-PT-3a-LTLFireability-00 2354794 m, 24673 m/sec, 102799591 t fired, .
Time elapsed: 95 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 98/257 19/32 DLCflexbar-PT-3a-LTLFireability-00 2476799 m, 24401 m/sec, 108239365 t fired, .
Time elapsed: 100 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 103/257 20/32 DLCflexbar-PT-3a-LTLFireability-00 2599760 m, 24592 m/sec, 113603930 t fired, .
Time elapsed: 105 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 108/257 21/32 DLCflexbar-PT-3a-LTLFireability-00 2722897 m, 24627 m/sec, 118959772 t fired, .
Time elapsed: 110 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 113/257 22/32 DLCflexbar-PT-3a-LTLFireability-00 2847107 m, 24842 m/sec, 124394311 t fired, .
Time elapsed: 115 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 118/257 23/32 DLCflexbar-PT-3a-LTLFireability-00 2976863 m, 25951 m/sec, 129861609 t fired, .
Time elapsed: 120 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 123/257 24/32 DLCflexbar-PT-3a-LTLFireability-00 3105926 m, 25812 m/sec, 135228356 t fired, .
Time elapsed: 125 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 128/257 25/32 DLCflexbar-PT-3a-LTLFireability-00 3230654 m, 24945 m/sec, 140628655 t fired, .
Time elapsed: 130 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 133/257 26/32 DLCflexbar-PT-3a-LTLFireability-00 3347971 m, 23463 m/sec, 146033371 t fired, .
Time elapsed: 135 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 138/257 27/32 DLCflexbar-PT-3a-LTLFireability-00 3468861 m, 24178 m/sec, 151179560 t fired, .
Time elapsed: 140 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 143/257 28/32 DLCflexbar-PT-3a-LTLFireability-00 3584683 m, 23164 m/sec, 156349912 t fired, .
Time elapsed: 145 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 148/257 29/32 DLCflexbar-PT-3a-LTLFireability-00 3699780 m, 23019 m/sec, 161608453 t fired, .
Time elapsed: 150 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 153/257 30/32 DLCflexbar-PT-3a-LTLFireability-00 3822037 m, 24451 m/sec, 166923448 t fired, .
Time elapsed: 155 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 158/257 31/32 DLCflexbar-PT-3a-LTLFireability-00 3942110 m, 24014 m/sec, 172245144 t fired, .
Time elapsed: 160 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 163/257 32/32 DLCflexbar-PT-3a-LTLFireability-00 4064290 m, 24436 m/sec, 177488866 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 168/257 32/32 DLCflexbar-PT-3a-LTLFireability-00 4184989 m, 24139 m/sec, 182976897 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 3 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 60 (type EXCL) for 59 DLCflexbar-PT-3a-LTLFireability-13
lola: time limit : 263 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-13
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 56 DLCflexbar-PT-3a-LTLFireability-12
lola: time limit : 285 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-12
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 DLCflexbar-PT-3a-LTLFireability-05
lola: time limit : 311 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-05
lola: result : false
lola: markings : 5
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 DLCflexbar-PT-3a-LTLFireability-04
lola: time limit : 342 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 5/342 1/32 DLCflexbar-PT-3a-LTLFireability-04 84825 m, 16965 m/sec, 6237329 t fired, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 10/342 2/32 DLCflexbar-PT-3a-LTLFireability-04 186500 m, 20335 m/sec, 12158969 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 15/342 3/32 DLCflexbar-PT-3a-LTLFireability-04 275022 m, 17704 m/sec, 18127288 t fired, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 20/342 3/32 DLCflexbar-PT-3a-LTLFireability-04 352141 m, 15423 m/sec, 23858058 t fired, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 25/342 4/32 DLCflexbar-PT-3a-LTLFireability-04 429398 m, 15451 m/sec, 29481385 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 31/342 4/32 DLCflexbar-PT-3a-LTLFireability-04 507638 m, 15648 m/sec, 35223290 t fired, .
Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 36/342 5/32 DLCflexbar-PT-3a-LTLFireability-04 586105 m, 15693 m/sec, 41056818 t fired, .
Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 41/342 6/32 DLCflexbar-PT-3a-LTLFireability-04 663450 m, 15469 m/sec, 46796077 t fired, .
Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 46/342 6/32 DLCflexbar-PT-3a-LTLFireability-04 743475 m, 16005 m/sec, 52694525 t fired, .
Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 51/342 7/32 DLCflexbar-PT-3a-LTLFireability-04 824634 m, 16231 m/sec, 58669180 t fired, .
Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 56/342 7/32 DLCflexbar-PT-3a-LTLFireability-04 907893 m, 16651 m/sec, 64667662 t fired, .
Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 61/342 8/32 DLCflexbar-PT-3a-LTLFireability-04 987831 m, 15987 m/sec, 70636337 t fired, .
Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 66/342 9/32 DLCflexbar-PT-3a-LTLFireability-04 1071586 m, 16751 m/sec, 76602922 t fired, .
Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 71/342 9/32 DLCflexbar-PT-3a-LTLFireability-04 1153972 m, 16477 m/sec, 82557032 t fired, .
Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 76/342 10/32 DLCflexbar-PT-3a-LTLFireability-04 1237520 m, 16709 m/sec, 88564142 t fired, .
Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 81/342 11/32 DLCflexbar-PT-3a-LTLFireability-04 1317450 m, 15986 m/sec, 94523266 t fired, .
Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 86/342 11/32 DLCflexbar-PT-3a-LTLFireability-04 1397073 m, 15924 m/sec, 100461341 t fired, .
Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 91/342 12/32 DLCflexbar-PT-3a-LTLFireability-04 1476697 m, 15924 m/sec, 106249073 t fired, .
Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 96/342 12/32 DLCflexbar-PT-3a-LTLFireability-04 1554866 m, 15633 m/sec, 111942444 t fired, .
Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 101/342 13/32 DLCflexbar-PT-3a-LTLFireability-04 1640419 m, 17110 m/sec, 117588632 t fired, .
Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 106/342 14/32 DLCflexbar-PT-3a-LTLFireability-04 1717518 m, 15419 m/sec, 123320720 t fired, .
Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 111/342 14/32 DLCflexbar-PT-3a-LTLFireability-04 1804466 m, 17389 m/sec, 128963842 t fired, .
Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 116/342 15/32 DLCflexbar-PT-3a-LTLFireability-04 1887827 m, 16672 m/sec, 134771090 t fired, .
Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 121/342 16/32 DLCflexbar-PT-3a-LTLFireability-04 1972688 m, 16972 m/sec, 140809955 t fired, .
Time elapsed: 296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 126/342 16/32 DLCflexbar-PT-3a-LTLFireability-04 2054768 m, 16416 m/sec, 146664605 t fired, .
Time elapsed: 301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 131/342 17/32 DLCflexbar-PT-3a-LTLFireability-04 2132146 m, 15475 m/sec, 152453250 t fired, .
Time elapsed: 306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 136/342 17/32 DLCflexbar-PT-3a-LTLFireability-04 2213797 m, 16330 m/sec, 158280629 t fired, .
Time elapsed: 311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 141/342 18/32 DLCflexbar-PT-3a-LTLFireability-04 2292307 m, 15702 m/sec, 164042187 t fired, .
Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 146/342 19/32 DLCflexbar-PT-3a-LTLFireability-04 2370814 m, 15701 m/sec, 169682483 t fired, .
Time elapsed: 321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 151/342 19/32 DLCflexbar-PT-3a-LTLFireability-04 2449335 m, 15704 m/sec, 175212657 t fired, .
Time elapsed: 326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 156/342 20/32 DLCflexbar-PT-3a-LTLFireability-04 2525243 m, 15181 m/sec, 180755797 t fired, .
Time elapsed: 331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 161/342 20/32 DLCflexbar-PT-3a-LTLFireability-04 2603369 m, 15625 m/sec, 186289521 t fired, .
Time elapsed: 336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 166/342 21/32 DLCflexbar-PT-3a-LTLFireability-04 2681345 m, 15595 m/sec, 191804791 t fired, .
Time elapsed: 341 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 171/342 22/32 DLCflexbar-PT-3a-LTLFireability-04 2759690 m, 15669 m/sec, 197508939 t fired, .
Time elapsed: 346 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 176/342 22/32 DLCflexbar-PT-3a-LTLFireability-04 2841824 m, 16426 m/sec, 203284348 t fired, .
Time elapsed: 351 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 181/342 23/32 DLCflexbar-PT-3a-LTLFireability-04 2930658 m, 17766 m/sec, 209292183 t fired, .
Time elapsed: 356 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 186/342 23/32 DLCflexbar-PT-3a-LTLFireability-04 3008724 m, 15613 m/sec, 215020569 t fired, .
Time elapsed: 361 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 191/342 24/32 DLCflexbar-PT-3a-LTLFireability-04 3093518 m, 16958 m/sec, 220625075 t fired, .
Time elapsed: 366 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 196/342 25/32 DLCflexbar-PT-3a-LTLFireability-04 3176564 m, 16609 m/sec, 226333651 t fired, .
Time elapsed: 371 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 201/342 25/32 DLCflexbar-PT-3a-LTLFireability-04 3256683 m, 16023 m/sec, 232246247 t fired, .
Time elapsed: 376 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 206/342 26/32 DLCflexbar-PT-3a-LTLFireability-04 3332899 m, 15243 m/sec, 237890720 t fired, .
Time elapsed: 381 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 211/342 27/32 DLCflexbar-PT-3a-LTLFireability-04 3412274 m, 15875 m/sec, 243548667 t fired, .
Time elapsed: 386 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 216/342 27/32 DLCflexbar-PT-3a-LTLFireability-04 3492666 m, 16078 m/sec, 249147144 t fired, .
Time elapsed: 391 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 221/342 28/32 DLCflexbar-PT-3a-LTLFireability-04 3572919 m, 16050 m/sec, 254934506 t fired, .
Time elapsed: 396 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 226/342 28/32 DLCflexbar-PT-3a-LTLFireability-04 3649983 m, 15412 m/sec, 260567020 t fired, .
Time elapsed: 401 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 231/342 29/32 DLCflexbar-PT-3a-LTLFireability-04 3728339 m, 15671 m/sec, 266251141 t fired, .
Time elapsed: 406 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 236/342 30/32 DLCflexbar-PT-3a-LTLFireability-04 3807538 m, 15839 m/sec, 272029012 t fired, .
Time elapsed: 411 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 241/342 30/32 DLCflexbar-PT-3a-LTLFireability-04 3888206 m, 16133 m/sec, 277778425 t fired, .
Time elapsed: 416 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 246/342 31/32 DLCflexbar-PT-3a-LTLFireability-04 3965223 m, 15403 m/sec, 283382910 t fired, .
Time elapsed: 421 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 251/342 31/32 DLCflexbar-PT-3a-LTLFireability-04 4042991 m, 15553 m/sec, 288791499 t fired, .
Time elapsed: 426 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 256/342 32/32 DLCflexbar-PT-3a-LTLFireability-04 4118798 m, 15161 m/sec, 294260057 t fired, .
Time elapsed: 431 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 17 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 436 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 14 (type EXCL) for 13 DLCflexbar-PT-3a-LTLFireability-03
lola: time limit : 351 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 5/351 1/32 DLCflexbar-PT-3a-LTLFireability-03 76675 m, 15335 m/sec, 5715745 t fired, .
Time elapsed: 441 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 10/351 2/32 DLCflexbar-PT-3a-LTLFireability-03 155439 m, 15752 m/sec, 11435455 t fired, .
Time elapsed: 446 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 15/351 2/32 DLCflexbar-PT-3a-LTLFireability-03 243211 m, 17554 m/sec, 16948278 t fired, .
Time elapsed: 451 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 20/351 3/32 DLCflexbar-PT-3a-LTLFireability-03 340109 m, 19379 m/sec, 22407270 t fired, .
Time elapsed: 456 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 25/351 3/32 DLCflexbar-PT-3a-LTLFireability-03 435459 m, 19070 m/sec, 27920891 t fired, .
Time elapsed: 461 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 30/351 4/32 DLCflexbar-PT-3a-LTLFireability-03 513753 m, 15658 m/sec, 33640670 t fired, .
Time elapsed: 466 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 35/351 5/32 DLCflexbar-PT-3a-LTLFireability-03 594712 m, 16191 m/sec, 39554359 t fired, .
Time elapsed: 471 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 40/351 5/32 DLCflexbar-PT-3a-LTLFireability-03 673193 m, 15696 m/sec, 45418025 t fired, .
Time elapsed: 476 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 45/351 6/32 DLCflexbar-PT-3a-LTLFireability-03 753624 m, 16086 m/sec, 51232100 t fired, .
Time elapsed: 481 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 50/351 6/32 DLCflexbar-PT-3a-LTLFireability-03 831649 m, 15605 m/sec, 56983611 t fired, .
Time elapsed: 486 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 55/351 7/32 DLCflexbar-PT-3a-LTLFireability-03 911247 m, 15919 m/sec, 62771497 t fired, .
Time elapsed: 491 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 60/351 7/32 DLCflexbar-PT-3a-LTLFireability-03 990551 m, 15860 m/sec, 68602890 t fired, .
Time elapsed: 496 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 65/351 8/32 DLCflexbar-PT-3a-LTLFireability-03 1068827 m, 15655 m/sec, 74455632 t fired, .
Time elapsed: 501 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 70/351 8/32 DLCflexbar-PT-3a-LTLFireability-03 1143245 m, 14883 m/sec, 80018184 t fired, .
Time elapsed: 506 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 75/351 9/32 DLCflexbar-PT-3a-LTLFireability-03 1222269 m, 15804 m/sec, 85734669 t fired, .
Time elapsed: 511 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 80/351 9/32 DLCflexbar-PT-3a-LTLFireability-03 1295759 m, 14698 m/sec, 91281552 t fired, .
Time elapsed: 516 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 85/351 10/32 DLCflexbar-PT-3a-LTLFireability-03 1369915 m, 14831 m/sec, 96841171 t fired, .
Time elapsed: 521 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 90/351 10/32 DLCflexbar-PT-3a-LTLFireability-03 1445274 m, 15071 m/sec, 102409118 t fired, .
Time elapsed: 526 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 95/351 11/32 DLCflexbar-PT-3a-LTLFireability-03 1521365 m, 15218 m/sec, 107995101 t fired, .
Time elapsed: 531 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 100/351 11/32 DLCflexbar-PT-3a-LTLFireability-03 1600528 m, 15832 m/sec, 113620264 t fired, .
Time elapsed: 536 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 105/351 12/32 DLCflexbar-PT-3a-LTLFireability-03 1674135 m, 14721 m/sec, 119187378 t fired, .
Time elapsed: 541 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 110/351 13/32 DLCflexbar-PT-3a-LTLFireability-03 1752509 m, 15674 m/sec, 124745208 t fired, .
Time elapsed: 546 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 115/351 13/32 DLCflexbar-PT-3a-LTLFireability-03 1828725 m, 15243 m/sec, 130292956 t fired, .
Time elapsed: 551 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 120/351 14/32 DLCflexbar-PT-3a-LTLFireability-03 1902675 m, 14790 m/sec, 135822022 t fired, .
Time elapsed: 556 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 125/351 14/32 DLCflexbar-PT-3a-LTLFireability-03 1977455 m, 14956 m/sec, 141382975 t fired, .
Time elapsed: 561 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 130/351 15/32 DLCflexbar-PT-3a-LTLFireability-03 2058535 m, 16216 m/sec, 146957172 t fired, .
Time elapsed: 566 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 135/351 15/32 DLCflexbar-PT-3a-LTLFireability-03 2133911 m, 15075 m/sec, 152513590 t fired, .
Time elapsed: 571 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 140/351 16/32 DLCflexbar-PT-3a-LTLFireability-03 2211131 m, 15444 m/sec, 158219136 t fired, .
Time elapsed: 576 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 145/351 16/32 DLCflexbar-PT-3a-LTLFireability-03 2291159 m, 16005 m/sec, 163896929 t fired, .
Time elapsed: 581 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 150/351 17/32 DLCflexbar-PT-3a-LTLFireability-03 2366731 m, 15114 m/sec, 169378578 t fired, .
Time elapsed: 586 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 155/351 17/32 DLCflexbar-PT-3a-LTLFireability-03 2444669 m, 15587 m/sec, 174912086 t fired, .
Time elapsed: 591 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 160/351 18/32 DLCflexbar-PT-3a-LTLFireability-03 2519475 m, 14961 m/sec, 180432550 t fired, .
Time elapsed: 596 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 165/351 18/32 DLCflexbar-PT-3a-LTLFireability-03 2595673 m, 15239 m/sec, 186020481 t fired, .
Time elapsed: 601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 170/351 19/32 DLCflexbar-PT-3a-LTLFireability-03 2668675 m, 14600 m/sec, 191551569 t fired, .
Time elapsed: 606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 175/351 19/32 DLCflexbar-PT-3a-LTLFireability-03 2740785 m, 14422 m/sec, 197025266 t fired, .
Time elapsed: 611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 180/351 20/32 DLCflexbar-PT-3a-LTLFireability-03 2817987 m, 15440 m/sec, 202559809 t fired, .
Time elapsed: 616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 185/351 20/32 DLCflexbar-PT-3a-LTLFireability-03 2895257 m, 15454 m/sec, 208116291 t fired, .
Time elapsed: 621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 190/351 21/32 DLCflexbar-PT-3a-LTLFireability-03 2969493 m, 14847 m/sec, 213637550 t fired, .
Time elapsed: 626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 195/351 21/32 DLCflexbar-PT-3a-LTLFireability-03 3043641 m, 14829 m/sec, 219166134 t fired, .
Time elapsed: 631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 200/351 22/32 DLCflexbar-PT-3a-LTLFireability-03 3122675 m, 15806 m/sec, 224719330 t fired, .
Time elapsed: 636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 205/351 23/32 DLCflexbar-PT-3a-LTLFireability-03 3210763 m, 17617 m/sec, 230143633 t fired, .
Time elapsed: 641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 210/351 23/32 DLCflexbar-PT-3a-LTLFireability-03 3289253 m, 15698 m/sec, 235794237 t fired, .
Time elapsed: 646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 215/351 24/32 DLCflexbar-PT-3a-LTLFireability-03 3364957 m, 15140 m/sec, 241455995 t fired, .
Time elapsed: 651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 220/351 24/32 DLCflexbar-PT-3a-LTLFireability-03 3441575 m, 15323 m/sec, 247132128 t fired, .
Time elapsed: 656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 225/351 25/32 DLCflexbar-PT-3a-LTLFireability-03 3531201 m, 17925 m/sec, 252653860 t fired, .
Time elapsed: 661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 230/351 25/32 DLCflexbar-PT-3a-LTLFireability-03 3614366 m, 16633 m/sec, 258229461 t fired, .
Time elapsed: 666 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 235/351 26/32 DLCflexbar-PT-3a-LTLFireability-03 3697719 m, 16670 m/sec, 263827559 t fired, .
Time elapsed: 671 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 240/351 26/32 DLCflexbar-PT-3a-LTLFireability-03 3775407 m, 15537 m/sec, 269503580 t fired, .
Time elapsed: 676 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 245/351 27/32 DLCflexbar-PT-3a-LTLFireability-03 3854067 m, 15732 m/sec, 275216155 t fired, .
Time elapsed: 681 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 250/351 28/32 DLCflexbar-PT-3a-LTLFireability-03 3936759 m, 16538 m/sec, 281031742 t fired, .
Time elapsed: 686 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 255/351 28/32 DLCflexbar-PT-3a-LTLFireability-03 4018323 m, 16312 m/sec, 286667012 t fired, .
Time elapsed: 691 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 260/351 29/32 DLCflexbar-PT-3a-LTLFireability-03 4096145 m, 15564 m/sec, 292261345 t fired, .
Time elapsed: 696 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 265/351 29/32 DLCflexbar-PT-3a-LTLFireability-03 4173271 m, 15425 m/sec, 297943727 t fired, .
Time elapsed: 701 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 270/351 30/32 DLCflexbar-PT-3a-LTLFireability-03 4246727 m, 14691 m/sec, 303554069 t fired, .
Time elapsed: 706 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 275/351 30/32 DLCflexbar-PT-3a-LTLFireability-03 4325941 m, 15842 m/sec, 309184416 t fired, .
Time elapsed: 711 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 280/351 31/32 DLCflexbar-PT-3a-LTLFireability-03 4403605 m, 15532 m/sec, 314794354 t fired, .
Time elapsed: 716 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 285/351 31/32 DLCflexbar-PT-3a-LTLFireability-03 4480143 m, 15307 m/sec, 320442399 t fired, .
Time elapsed: 721 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 290/351 32/32 DLCflexbar-PT-3a-LTLFireability-03 4558955 m, 15762 m/sec, 326142455 t fired, .
Time elapsed: 726 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 LTL EXCL 295/351 32/32 DLCflexbar-PT-3a-LTLFireability-03 4637673 m, 15743 m/sec, 331814873 t fired, .
Time elapsed: 731 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 14 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-3a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-11: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 736 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 8 (type EXCL) for 7 DLCflexbar-PT-3a-LTLFireability-01
lola: time limit : 358 sec
lola: memory limit: 32 pages
lola: FINISHED task # 8 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-01
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 97 (type EXCL) for 53 DLCflexbar-PT-3a-LTLFireability-11
lola: time limit : 409 sec
lola: memory limit: 32 pages
lola: FINISHED task # 97 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-11
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 63 (type EXCL) for 62 DLCflexbar-PT-3a-LTLFireability-14
lola: time limit : 477 sec
lola: memory limit: 32 pages
lola: FINISHED task # 63 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-14
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 5 (type EXCL) for 0 DLCflexbar-PT-3a-LTLFireability-00
lola: time limit : 572 sec
lola: memory limit: 32 pages
lola: FINISHED task # 5 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-00
lola: result : false
lola: markings : 43
lola: fired transitions : 659
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 DLCflexbar-PT-3a-LTLFireability-08
lola: time limit : 716 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-08
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 DLCflexbar-PT-3a-LTLFireability-02
lola: time limit : 954 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-02
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 66 (type EXCL) for 65 DLCflexbar-PT-3a-LTLFireability-15
lola: time limit : 1432 sec
lola: memory limit: 32 pages
lola: FINISHED task # 66 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-15
lola: result : false
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 DLCflexbar-PT-3a-LTLFireability-09
lola: time limit : 2864 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for DLCflexbar-PT-3a-LTLFireability-09
lola: result : false
lola: markings : 76
lola: fired transitions : 1829
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-LTLFireability-00: CONJ false LTL model checker
DLCflexbar-PT-3a-LTLFireability-01: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-02: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-03: LTL unknown AGGR
DLCflexbar-PT-3a-LTLFireability-04: LTL unknown AGGR
DLCflexbar-PT-3a-LTLFireability-05: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-06: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-07: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-08: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-09: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-10: CONJ false state space
DLCflexbar-PT-3a-LTLFireability-11: F false state space / EG
DLCflexbar-PT-3a-LTLFireability-12: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-13: LTL true LTL model checker
DLCflexbar-PT-3a-LTLFireability-14: LTL false LTL model checker
DLCflexbar-PT-3a-LTLFireability-15: LTL false LTL model checker
Time elapsed: 736 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-3a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-3a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477000524"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-3a.tgz
mv DLCflexbar-PT-3a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;