fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r070-smll-167814396600026
Last Updated
May 14, 2023

About the Execution of LoLA for CSRepetitions-COL-05

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
7764.352 627677.00 623532.00 6882.40 ??T??TFTF?FF?TTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r070-smll-167814396600026.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is CSRepetitions-COL-05, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r070-smll-167814396600026
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 524K
-rw-r--r-- 1 mcc users 8.6K Feb 25 11:59 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 25 11:59 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 11:56 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 25 11:56 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 15:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 15:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 12:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 95K Feb 25 12:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 18K Feb 25 12:09 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 136K Feb 25 12:09 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:41 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:41 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 15K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-00
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-01
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-02
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-03
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-04
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-05
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-06
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-07
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-08
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-09
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-10
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-11
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-12
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-13
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-14
FORMULA_NAME CSRepetitions-COL-05-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678226984877

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=CSRepetitions-COL-05
Not applying reductions.
Model is COL
CTLFireability PT
[2023-03-07 22:09:48] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, CTLFireability, --reduce-single, STATESPACE]
[2023-03-07 22:09:48] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-07 22:09:49] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-07 22:09:49] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-07 22:09:49] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 956 ms
[2023-03-07 22:09:50] [INFO ] Imported 6 HL places and 5 HL transitions for a total of 206 PT places and 325.0 transition bindings in 28 ms.
Parsed 16 properties from file ./CTLFireability.xml in 30 ms.
[2023-03-07 22:09:50] [INFO ] Unfolded HLPN to a Petri net with 206 places and 325 transitions 1175 arcs in 80 ms.
[2023-03-07 22:09:50] [INFO ] Unfolded 16 HLPN properties in 7 ms.
[2023-03-07 22:09:50] [INFO ] Export to MCC of 16 properties in file ./CTLFireability.STATESPACE.xml took 88 ms.
[2023-03-07 22:09:50] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 206 places, 325 transitions and 1175 arcs took 5 ms.
Total runtime 1568 ms.
starting LoLA
BK_INPUT CSRepetitions-COL-05
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfCTLFireability

FORMULA CSRepetitions-COL-05-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678227612554

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfCTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfCTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfCTLFireability/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:394
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CSRepetitions-COL-05-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-CTLFireability-13: EXEG 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/188 2/32 CSRepetitions-COL-05-CTLFireability-00 241456 m, 48291 m/sec, 2098966 t fired, .

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CSRepetitions-COL-05-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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1 CTL EXCL 10/188 3/32 CSRepetitions-COL-05-CTLFireability-00 491029 m, 49914 m/sec, 4481389 t fired, .

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CSRepetitions-COL-05-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-CTLFireability-13: EXEG 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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1 CTL EXCL 15/188 4/32 CSRepetitions-COL-05-CTLFireability-00 734979 m, 48790 m/sec, 6870001 t fired, .

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1 CTL EXCL 20/188 5/32 CSRepetitions-COL-05-CTLFireability-00 982422 m, 49488 m/sec, 9360454 t fired, .

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1 CTL EXCL 25/188 7/32 CSRepetitions-COL-05-CTLFireability-00 1224545 m, 48424 m/sec, 11854761 t fired, .

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CSRepetitions-COL-05-CTLFireability-11: CTL false CTL model checker
CSRepetitions-COL-05-CTLFireability-13: EXEG true state space /EXEG
CSRepetitions-COL-05-CTLFireability-14: CTL true CTL model checker
CSRepetitions-COL-05-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-05-CTLFireability-05: CONJ 0 1 0 0 3 0 0 0
CSRepetitions-COL-05-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-10: CONJ 0 1 0 0 2 0 1 0
CSRepetitions-COL-05-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/1001 22/32 CSRepetitions-COL-05-CTLFireability-04 4474610 m, 282696 m/sec, 6839153 t fired, .

Time elapsed: 610 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-CTLFireability-02: DISJ true CTL model checker
CSRepetitions-COL-05-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-05-CTLFireability-07: CTL true CTL model checker
CSRepetitions-COL-05-CTLFireability-08: CTL false CTL model checker
CSRepetitions-COL-05-CTLFireability-11: CTL false CTL model checker
CSRepetitions-COL-05-CTLFireability-13: EXEG true state space /EXEG
CSRepetitions-COL-05-CTLFireability-14: CTL true CTL model checker
CSRepetitions-COL-05-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-05-CTLFireability-05: CONJ 0 1 0 0 3 0 0 0
CSRepetitions-COL-05-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-10: CONJ 0 1 0 0 2 0 1 0
CSRepetitions-COL-05-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 20/1001 29/32 CSRepetitions-COL-05-CTLFireability-04 5915701 m, 288218 m/sec, 9046876 t fired, .

Time elapsed: 615 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 17 (type EXCL) for CSRepetitions-COL-05-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-CTLFireability-02: DISJ true CTL model checker
CSRepetitions-COL-05-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-05-CTLFireability-07: CTL true CTL model checker
CSRepetitions-COL-05-CTLFireability-08: CTL false CTL model checker
CSRepetitions-COL-05-CTLFireability-11: CTL false CTL model checker
CSRepetitions-COL-05-CTLFireability-13: EXEG true state space /EXEG
CSRepetitions-COL-05-CTLFireability-14: CTL true CTL model checker
CSRepetitions-COL-05-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-05: CONJ 0 1 0 0 3 0 0 0
CSRepetitions-COL-05-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-05-CTLFireability-10: CONJ 0 1 0 0 2 0 1 0
CSRepetitions-COL-05-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 620 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 22 (type EXCL) for 19 CSRepetitions-COL-05-CTLFireability-05
lola: time limit : 1490 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for CSRepetitions-COL-05-CTLFireability-05
lola: result : true
lola: markings : 51
lola: fired transitions : 53
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 38 CSRepetitions-COL-05-CTLFireability-10
lola: time limit : 2980 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for CSRepetitions-COL-05-CTLFireability-10
lola: result : false
lola: markings : 38
lola: fired transitions : 149
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-CTLFireability-00: CTL unknown AGGR
CSRepetitions-COL-05-CTLFireability-01: CTL unknown AGGR
CSRepetitions-COL-05-CTLFireability-02: DISJ true CTL model checker
CSRepetitions-COL-05-CTLFireability-03: CTL unknown AGGR
CSRepetitions-COL-05-CTLFireability-04: CTL unknown AGGR
CSRepetitions-COL-05-CTLFireability-05: CONJ true CONJ
CSRepetitions-COL-05-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-05-CTLFireability-07: CTL true CTL model checker
CSRepetitions-COL-05-CTLFireability-08: CTL false CTL model checker
CSRepetitions-COL-05-CTLFireability-09: CTL unknown AGGR
CSRepetitions-COL-05-CTLFireability-10: CONJ false CTL model checker
CSRepetitions-COL-05-CTLFireability-11: CTL false CTL model checker
CSRepetitions-COL-05-CTLFireability-12: CTL unknown AGGR
CSRepetitions-COL-05-CTLFireability-13: EXEG true state space /EXEG
CSRepetitions-COL-05-CTLFireability-14: CTL true CTL model checker
CSRepetitions-COL-05-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CSRepetitions-COL-05"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is CSRepetitions-COL-05, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r070-smll-167814396600026"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CSRepetitions-COL-05.tgz
mv CSRepetitions-COL-05 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;