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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r039-tajo-167813692100158
Last Updated
May 14, 2023

About the Execution of LoLa+red for BridgeAndVehicles-COL-V80P50N50

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3744.560 38683.00 129166.00 179.00 FFFTFTFFTTTFFFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2023-input.r039-tajo-167813692100158.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is BridgeAndVehicles-COL-V80P50N50, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r039-tajo-167813692100158
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 536K
-rw-r--r-- 1 mcc users 9.4K Feb 25 13:21 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K Feb 25 13:21 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 13:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 13:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 15:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 15:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 15:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 14:59 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 121K Feb 25 14:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.9K Feb 25 14:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 25 14:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 15:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 10 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 47K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1678483265371

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=BridgeAndVehicles-COL-V80P50N50
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 21:21:07] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-10 21:21:07] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 21:21:07] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-10 21:21:07] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-10 21:21:08] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 452 ms
[2023-03-10 21:21:08] [INFO ] Imported 15 HL places and 11 HL transitions for a total of 228 PT places and 1339138.0 transition bindings in 37 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 21 ms.
Working with output stream class java.io.PrintStream
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-10 21:21:08] [INFO ] Built PT skeleton of HLPN with 15 places and 11 transitions 56 arcs in 4 ms.
[2023-03-10 21:21:08] [INFO ] Skeletonized 15 HLPN properties in 2 ms.
Remains 15 properties that can be checked using skeleton over-approximation.
Reduce places removed 3 places and 0 transitions.
Computed a total of 9 stabilizing places and 6 stable transitions
Graph (complete) has 22 edges and 12 vertex of which 10 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.1 ms
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
[2023-03-10 21:21:08] [INFO ] Flatten gal took : 23 ms
[2023-03-10 21:21:08] [INFO ] Flatten gal took : 3 ms
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00 FALSE TECHNIQUES CPN_APPROX
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02 FALSE TECHNIQUES CPN_APPROX
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04 FALSE TECHNIQUES CPN_APPROX
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13 FALSE TECHNIQUES CPN_APPROX
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15 FALSE TECHNIQUES CPN_APPROX
Arc [1:1*[(MOD (ADD $cA 1) 81)]] contains successor/predecessor on variables of sort voitureA
Arc [6:1*[(MOD (ADD (MOD (MINUS $cB 1) 81) 81) 81)]] contains successor/predecessor on variables of sort voitureB
Arc [13:1*[(MOD (ADD $cpt 1) 51)]] contains successor/predecessor on variables of sort compteur
Arc [14:1*[(MOD (ADD $s 1) 2)]] contains successor/predecessor on variables of sort sens
[2023-03-10 21:21:08] [INFO ] Unfolded HLPN to a Petri net with 228 places and 8588 transitions 67470 arcs in 254 ms.
[2023-03-10 21:21:08] [INFO ] Unfolded 15 HLPN properties in 1 ms.
Incomplete random walk after 10000 steps, including 14 resets, run finished after 786 ms. (steps per millisecond=12 ) properties (out of 10) seen :3
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 182 ms. (steps per millisecond=54 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 177 ms. (steps per millisecond=56 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 6 resets, run finished after 211 ms. (steps per millisecond=47 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 6 resets, run finished after 314 ms. (steps per millisecond=31 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 351 ms. (steps per millisecond=28 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 332 ms. (steps per millisecond=30 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 244 ms. (steps per millisecond=40 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-10 21:21:11] [INFO ] Flow matrix only has 530 transitions (discarded 8058 similar events)
// Phase 1: matrix 530 rows 228 cols
[2023-03-10 21:21:11] [INFO ] Computed 7 place invariants in 74 ms
[2023-03-10 21:21:12] [INFO ] [Real]Absence check using 7 positive place invariants in 5 ms returned sat
[2023-03-10 21:21:12] [INFO ] After 376ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:5
[2023-03-10 21:21:12] [INFO ] [Nat]Absence check using 7 positive place invariants in 3 ms returned sat
[2023-03-10 21:21:12] [INFO ] After 252ms SMT Verify possible using all constraints in natural domain returned unsat :7 sat :0
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 7 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
All properties solved without resorting to model-checking.
Total runtime 5159 ms.
starting LoLA
BK_INPUT BridgeAndVehicles-COL-V80P50N50
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678483304054

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: TR BINDINGS
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 49 (type SKEL/FNDP) for 3 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type SKEL/EQUN) for 3 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SKEL/SRCH) for 3 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type SKEL/SRCH) for 3 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH INITIAL
lola: LAUNCH task # 35 (type SKEL/CNST) for 33 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 35 (type SKEL/CNST) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: result : false
lola: TR BINDINGS DONE
lola: Places: 228, Transitions: 8588
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: @ trans enregistrement_A
lola: @ trans decision
lola: @ trans altern_cpt
lola: @ trans autorisation_A
lola: @ trans liberation_A
lola: @ trans enregistrement_B
lola: @ trans timeout_A
lola: @ trans timeout_B
lola: @ trans liberation_B
lola: @ trans basculement
lola: @ trans autorisation_B
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-57.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF 0 1 4 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF 0 5 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 EF FNDP 5/189 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 10947332 t fired, 11 attempts, .
57 EF STEQ 5/189 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 sara is running.
81 EF SRCH 5/189 1/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 2040287 m, 408057 m/sec, 6011273 t fired, .
82 EF SRCH 5/200 1/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 1172250 m, 234450 m/sec, 2625521 t fired, .

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lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF 0 1 4 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF 0 5 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 EF FNDP 10/184 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 24640899 t fired, 25 attempts, .
57 EF STEQ 10/184 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 sara is running.
81 EF SRCH 10/184 1/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 3654265 m, 322795 m/sec, 10882978 t fired, .
82 EF SRCH 10/195 1/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 2109144 m, 187378 m/sec, 4777673 t fired, .

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lola: FINISHED task # 57 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: result : false
lola: CANCELED task # 49 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 81 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 82 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 (obsolete)
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lola: memory limit: 5 pages
lola: FINISHED task # 49 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: result : unknown
lola: fired transitions : 27492482
lola: tried executions : 29
lola: time used : 11.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: AG 0 1 4 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF 0 5 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
101 EF FNDP 4/199 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 3168810 t fired, 161695 attempts, .
102 EF STEQ 4/199 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 sara not yet started (preprocessing).
104 EF SRCH 4/211 1/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 2310754 m, 462150 m/sec, 4256554 t fired, .
105 EF SRCH 4/211 1/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 2104141 m, 420828 m/sec, 4820858 t fired, .

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lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: FINISHED task # 104 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
lola: result : false
lola: markings : 6366860
lola: fired transitions : 11652158
lola: time used : 8.000000
lola: memory pages used : 1
lola: CANCELED task # 101 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 102 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 105 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 118 (type SKEL/FNDP) for 0 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
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lola: LAUNCH task # 133 (type SKEL/EQUN) for 0 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
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lola: FINISHED task # 101 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
lola: result : unknown
lola: fired transitions : 10834486
lola: tried executions : 556576
lola: time used : 8.000000
lola: memory pages used : 0
lola: FINISHED task # 140 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: result : false
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lola: CANCELED task # 118 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00 (obsolete)
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lola: CANCELED task # 141 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 66 (type SKEL/FNDP) for 21 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
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lola: LAUNCH task # 67 (type SKEL/EQUN) for 21 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
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lola: LAUNCH task # 69 (type SKEL/SRCH) for 21 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
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lola: LAUNCH task # 70 (type SKEL/SRCH) for 21 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-67.sara.
sara: place or transition ordering is non-deterministic
lola: Rule S: 0 transitions removed,0 places removed

lola: FINISHED task # 67 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: result : false
lola: LAUNCH INITIAL
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lola: LAUNCH INITIAL
lola: LAUNCH task # 40 (type CNST) for 39 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
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lola: LAUNCH INITIAL
lola: LAUNCH task # 46 (type CNST) for 45 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15
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lola: CANCELED task # 70 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07 (obsolete)
lola: FINISHED task # 66 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: result : unknown
lola: fired transitions : 192291
lola: tried executions : 163
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 7 (type CNST) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
lola: result : false
lola: FINISHED task # 40 (type CNST) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: result : false
lola: FINISHED task # 13 (type CNST) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: result : false
lola: FINISHED task # 46 (type CNST) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15
lola: result : false
lola: LAUNCH task # 52 (type SKEL/FNDP) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SKEL/EQUN) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
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lola: LAUNCH task # 96 (type SKEL/SRCH) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
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lola: LAUNCH task # 97 (type SKEL/SRCH) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 97 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: result : true
lola: markings : 81
lola: fired transitions : 80
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lola: memory pages used : 1
lola: CANCELED task # 52 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 53 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 96 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 142 (type SKEL/FNDP) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
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lola: LAUNCH task # 143 (type SKEL/EQUN) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 145 (type SKEL/SRCH) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
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lola: LAUNCH task # 146 (type SKEL/SRCH) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
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lola: FINISHED task # 145 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: result : true
lola: markings : 161
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lola: FINISHED task # 146 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
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lola: memory pages used : 1
lola: CANCELED task # 142 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 (obsolete)
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lola: LAUNCH task # 55 (type SKEL/FNDP) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
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lola: LAUNCH task # 56 (type SKEL/EQUN) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
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lola: LAUNCH task # 85 (type SKEL/SRCH) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
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lola: LAUNCH task # 86 (type SKEL/SRCH) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 85 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: result : true
lola: markings : 23
lola: fired transitions : 22
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lola: memory pages used : 1
lola: CANCELED task # 55 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 56 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 86 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 135 (type SKEL/FNDP) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 138 (type SKEL/EQUN) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 148 (type SKEL/SRCH) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 149 (type SKEL/SRCH) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 52 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: result : true
lola: fired transitions : 79
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 55 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 21
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 149 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: result : false
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 135 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 138 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 148 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 153 (type SKEL/FNDP) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-143.sara.
lola: LAUNCH task # 155 (type SKEL/EQUN) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 157 (type SKEL/SRCH) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages

lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 158 (type SKEL/SRCH) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 143 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: result : true
lola: FINISHED task # 142 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 159
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-53.sara.
sara: place or transition ordering is non-deterministic

sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-56.sara.

lola: FINISHED task # 53 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: result : true
lola: FINISHED task # 56 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG true skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 1 4 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 4 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
153 EF FNDPsara: try reading problem file /home/mcc/execution/ReachabilityCardinality-138.sara.
sara: place or transition ordering is non-deterministic

1/894 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 122083 t fired, 193 attempts, .
155 EF STEQ 1/894 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 sara not yet started (preprocessing).
157 EF SRCH 1/894 1/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 62306 m, 12461 m/sec, 145858 t fired, .
158 EF SRCH 1/1192 1/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 13733 m, 2746 m/sec, 26282 t fired, .

Time elapsed: 20 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-155.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 138 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: result : false
lola: FINISHED task # 155 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: result : false
lola: CANCELED task # 153 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 157 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 158 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 90 (type SKEL/FNDP) for 30 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 91 (type SKEL/EQUN) for 30 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 93 (type SKEL/SRCH) for 30 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type SKEL/SRCH) for 30 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 153 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: result : unknown
lola: fired transitions : 124497
lola: tried executions : 198
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-91.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 93 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: result : false
lola: markings : 13122
lola: fired transitions : 26082
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 90 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 91 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 94 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 125 (type SKEL/FNDP) for 9 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 126 (type SKEL/EQUN) for 9 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 128 (type SKEL/SRCH) for 9 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 129 (type SKEL/SRCH) for 9 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 90 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 197
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 91 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: result : false
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-126.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 126 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03
lola: result : false
lola: CANCELED task # 125 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 128 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 129 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03 (obsolete)
lola: FINISHED task # 125 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 127340
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-102.sara.
sara: place or transition ordering is non-deterministic
lola: planning for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 stopped (result already fixed).
lola: FINISHED task # 133 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: result : unknown

lola: FINISHED task # 102 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
lola: result : false
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG true skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 4 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 25 secs. Pages in use: 3
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 165 (type EXCL) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: time limit : 1190 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 161 (type FNDP) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 162 (type EQUN) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 164 (type SRCH) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 164 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: result : true
lola: markings : 81
lola: fired transitions : 80
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 161 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 162 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 165 (type EXCL) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: FINISHED task # 161 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: result : unknown
lola: fired transitions : 36
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-162.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 172 (type EXCL) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 1785 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 168 (type FNDP) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 169 (type EQUN) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 171 (type SRCH) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 168 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 162
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 169 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 171 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 172 (type EXCL) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-169.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG false tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG true skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 30 secs. Pages in use: 3
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 178 (type EXCL) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 3570 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 174 (type FNDP) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 175 (type EQUN) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 177 (type SRCH) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 177 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: result : true
lola: markings : 23
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 174 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 175 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 178 (type EXCL) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF true tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG false tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: EF false preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG true skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false preprocessing


Time elapsed: 30 secs. Pages in use: 3

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V80P50N50"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is BridgeAndVehicles-COL-V80P50N50, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r039-tajo-167813692100158"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V80P50N50.tgz
mv BridgeAndVehicles-COL-V80P50N50 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;