About the Execution of LoLA for BridgeAndVehicles-COL-V50P50N10
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16220.792 | 86175.00 | 3852151.00 | 8902.50 | FFTFTT?FF???FT?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2023-input.r038-tajo-167813691000094.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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............................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is BridgeAndVehicles-COL-V50P50N10, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r038-tajo-167813691000094
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 488K
-rw-r--r-- 1 mcc users 7.2K Feb 25 12:10 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K Feb 25 12:10 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 25 12:08 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 25 12:08 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 15:36 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:36 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 15:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 12:25 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 113K Feb 25 12:25 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Feb 25 12:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 25 12:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 15:36 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 15:36 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 10 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 42K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14
FORMULA_NAME BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1678405770171
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=BridgeAndVehicles-COL-V50P50N10
Not applying reductions.
Model is COL
ReachabilityCardinality COL
starting LoLA
BK_INPUT BridgeAndVehicles-COL-V50P50N10
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678405856346
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393340 kB
MemFree: 15631212 kB
After kill :
MemTotal: 16393340 kB
MemFree: 15630604 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 50 (type SKEL/FNDP) for 15 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SKEL/EQUN) for 15 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 60 (type SKEL/SRCH) for 15 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 61 (type SKEL/SRCH) for 15 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: TR BINDINGS
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: TR BINDINGS DONE
lola: Places: 128, Transitions: 1328
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-58.sara.
lola: FINISHED task # 58 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05
lola: result : false
lola: CANCELED task # 50 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 60 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 61 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 72 (type SKEL/FNDP) for 0 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SKEL/EQUN) for 0 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type SKEL/SRCH) for 0 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 76 (type SKEL/SRCH) for 0 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 50 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05
lola: result : unknown
lola: fired transitions : 71700
lola: tried executions : 332
lola: time used : 0.000000
lola: memory pages used : 0
lola: @ trans enregistrement_A
lola: @ trans decision
lola: @ trans altern_cpt
lola: @ trans autorisation_A
lola: @ trans liberation_A
lola: @ trans enregistrement_B
lola: @ trans timeout_A
lola: @ trans timeout_B
lola: @ trans liberation_B
lola: @ trans basculement
lola: @ trans autorisation_B
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-73.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: FINISHED task # 73 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00
lola: result : false
lola: CANCELED task # 72 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 75 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 76 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 124 (type SKEL/FNDP) for 36 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 153 (type SKEL/EQUN) for 36 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 161 (type SKEL/SRCH) for 36 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 162 (type SKEL/SRCH) for 36 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 72 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00
lola: result : unknown
lola: fired transitions : 1585044
lola: tried executions : 4
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 161 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 124 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 153 (type EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 162 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 80 (type SKEL/FNDP) for 21 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SKEL/EQUN) for 21 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SKEL/SRCH) for 21 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SKEL/SRCH) for 21 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH INITIAL
lola: LAUNCH task # 25 (type CNST) for 24 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 40 (type CNST) for 39 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 25 (type CNST) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08
lola: result : false
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-153.sara.
lola: FINISHED task # 40 (type CNST) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13
lola: result : true
sara: error: :5: error: syntax error, unexpected $end, expecting KEY_TRANSITION
sara: error while reading Petri net from file -- aborting [#04]
sara: see manual for a documentation of this error
sara: last error message: No such file or directory
lola: Rule S: 0 transitions removed,0 places removed
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-81.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 153 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12
lola: result : unknown
lola: planning for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05 stopped (result already fixed).
lola: FINISHED task # 81 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07
lola: result : false
lola: CANCELED task # 80 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 83 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 84 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 102 (type SKEL/FNDP) for 30 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type SKEL/EQUN) for 30 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 105 (type SKEL/SRCH) for 30 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 106 (type SKEL/SRCH) for 30 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 80 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07
lola: result : unknown
lola: fired transitions : 1057645
lola: tried executions : 2217
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 105 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10
lola: result : true
lola: markings : 51
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 106 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10
lola: result : true
lola: markings : 51
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 102 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 103 (type EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 134 (type SKEL/FNDP) for 27 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 135 (type SKEL/EQUN) for 27 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 137 (type SKEL/SRCH) for 27 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 138 (type SKEL/SRCH) for 27 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 137 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09
lola: result : true
lola: markings : 107
lola: fired transitions : 106
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 134 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 135 (type EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 138 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 127 (type SKEL/FNDP) for 6 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 132 (type SKEL/EQUN) for 6 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 140 (type SKEL/SRCH) for 6 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 141 (type SKEL/SRCH) for 6 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 140 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
lola: result : true
lola: markings : 33
lola: fired transitions : 32
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 141 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
lola: result : true
lola: markings : 38
lola: fired transitions : 41
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 127 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 132 (type EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type SKEL/FNDP) for 12 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/EQUN) for 12 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SKEL/SRCH) for 12 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type SKEL/SRCH) for 12 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-135.sara.
lola: FINISHED task # 56 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04
lola: result : false
lola: markings : 51
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 134 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09
lola: result : true
lola: fired transitions : 105
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 102 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10
lola: result : true
lola: fired transitions : 49
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-132.sara.
lola: FINISHED task # 127 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
lola: result : true
lola: fired transitions : 31
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 53 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 54 (type EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 57 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-54.sara.
lola: LAUNCH task # 170 (type EXCL) for 9 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 130 (type SKEL/FNDP) for 9 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 145 (type SKEL/EQUN) for 9 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 147 (type SKEL/SRCH) for 9 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 57 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04
lola: result : false
lola: markings : 51
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-103.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 135 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09
lola: result : true
lola: FINISHED task # 53 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04
lola: result : unknown
lola: fired transitions : 321832
lola: tried executions : 6312
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 132 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
lola: result : true
lola: FINISHED task # 103 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10
lola: result : true
lola: FINISHED task # 54 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-145.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 145 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03
lola: result : false
lola: CANCELED task # 130 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 147 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 170 (type EXCL) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 182 (type EXCL) for 45 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 117 (type SKEL/FNDP) for 45 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type SKEL/EQUN) for 45 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 120 (type SKEL/SRCH) for 45 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 130 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 350517
lola: tried executions : 1745
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 120 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15
lola: result : false
lola: markings : 51
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 117 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 118 (type EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 182 (type EXCL) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 200 (type EXCL) for 3 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 79 (type SKEL/FNDP) for 3 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SKEL/EQUN) for 3 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type SKEL/SRCH) for 3 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 87 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01
lola: result : false
lola: markings : 51
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 79 (type FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 85 (type EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 200 (type EXCL) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-118.sara.
lola: LAUNCH task # 194 (type EXCL) for 6 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 110 (type SKEL/FNDP) for 42 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 111 (type SKEL/EQUN) for 42 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type SKEL/SRCH) for 42 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 118 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15
lola: result : false
lola: FINISHED task # 79 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01
lola: result : unknown
lola: fired transitions : 307
lola: tried executions : 8
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 110 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14
lola: result : true
lola: fired transitions : 15
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 111 (type EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 113 (type SRCH) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 143 (type SKEL/FNDP) for 18 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 150 (type SKEL/FNDP) for 33 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 151 (type SKEL/EQUN) for 33 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 150 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 45
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 151 (type EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 172 (type FNDP) for 27 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 173 (type EQUN) for 27 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-85.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-111.sara.
lola: FINISHED task # 85 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-151.sara.
lola: FINISHED task # 111 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14
lola: result : true
lola: FINISHED task # 151 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-173.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF 0 4 1 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 9 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 4/358 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 10327992 t fired, 202510 attempts, .
172 EF FNDP 4/358 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 120213 t fired, 554 attempts, .
173 EF STEQ 4/398 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
194 EF EXCL 4/599 1/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02 3282 m, 656 m/sec, 5289 t fired, .
Time elapsed: 5 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF 0 4 1 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 9 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 9/355 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 24256774 t fired, 475624 attempts, .
172 EF FNDP 9/355 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 284014 t fired, 1305 attempts, .
173 EF STEQ 9/395 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
194 EF EXCL 9/599 1/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02 8314 m, 1006 m/sec, 14095 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF 0 4 1 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 9 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 14/350 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 36892083 t fired, 723375 attempts, .
172 EF FNDP 14/350 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 446510 t fired, 2083 attempts, .
173 EF STEQ 14/390 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
194 EF EXCL 14/599 1/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02 13065 m, 950 m/sec, 22468 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF 0 4 1 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 9 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 19/345 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 49140879 t fired, 963547 attempts, .
172 EF FNDP 19/345 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 626107 t fired, 2950 attempts, .
173 EF STEQ 19/385 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
194 EF EXCL 19/599 1/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02 17803 m, 947 m/sec, 30801 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF 0 4 1 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 9 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 24/340 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 62828681 t fired, 1231935 attempts, .
172 EF FNDP 24/340 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 816169 t fired, 3878 attempts, .
173 EF STEQ 24/380 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
194 EF EXCL 24/599 1/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02 22647 m, 968 m/sec, 39610 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF 0 4 1 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 9 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 29/335 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 77234429 t fired, 1514401 attempts, .
172 EF FNDP 29/335 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 961421 t fired, 4622 attempts, .
173 EF STEQ 29/375 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
194 EF EXCL 29/599 1/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02 27615 m, 993 m/sec, 48835 t fired, .
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lola: FINISHED task # 194 (type EXCL) for BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02
lola: result : true
lola: markings : 27637
lola: fired transitions : 48865
lola: time used : 29.000000
lola: memory pages used : 1
lola: LAUNCH task # 228 (type EXCL) for 18 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06
lola: time limit : 714 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF true tandem / relaxed
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 34/370 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 88128357 t fired, 1728008 attempts, .
172 EF FNDP 34/420 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 1123068 t fired, 5461 attempts, .
173 EF STEQ 34/420 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
228 EF EXCL 5/714 1/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 127403 m, 25480 m/sec, 153560 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF true tandem / relaxed
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 39/365 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 102624503 t fired, 2012246 attempts, .
172 EF FNDP 39/415 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 1303981 t fired, 6423 attempts, .
173 EF STEQ 39/415 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
228 EF EXCL 10/714 1/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 192982 m, 13115 m/sec, 233969 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF true tandem / relaxed
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 44/360 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 117258211 t fired, 2299181 attempts, .
172 EF FNDP 44/410 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 1475782 t fired, 7339 attempts, .
173 EF STEQ 44/410 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
228 EF EXCL 15/714 2/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 224209 m, 6245 m/sec, 274168 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF true tandem / relaxed
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 49/355 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 124501920 t fired, 2441215 attempts, .
172 EF FNDP 49/405 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 1629648 t fired, 8182 attempts, .
173 EF STEQ 49/405 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
228 EF EXCL 20/714 2/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 237864 m, 2731 m/sec, 291943 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF true tandem / relaxed
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 54/350 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 131972769 t fired, 2587702 attempts, .
172 EF FNDP 54/400 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 1702736 t fired, 8581 attempts, .
173 EF STEQ 54/400 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
228 EF EXCL 25/714 2/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 253472 m, 3121 m/sec, 312037 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF true tandem / relaxed
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 59/345 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 138276351 t fired, 2711302 attempts, .
172 EF FNDP 59/395 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 1818615 t fired, 9228 attempts, .
173 EF STEQ 59/395 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
228 EF EXCL 31/714 2/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 265523 m, 2410 m/sec, 328089 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF true tandem / relaxed
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 65/339 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 144954444 t fired, 2842245 attempts, .
172 EF FNDP 65/389 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 1906820 t fired, 9713 attempts, .
173 EF STEQ 65/389 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
228 EF EXCL 36/714 2/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 288390 m, 4573 m/sec, 358921 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF true tandem / relaxed
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 70/334 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 154478209 t fired, 3028985 attempts, .
172 EF FNDP 70/384 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 2006406 t fired, 10271 attempts, .
173 EF STEQ 70/384 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
228 EF EXCL 41/714 2/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 313500 m, 5022 m/sec, 392464 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF true tandem / relaxed
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 75/329 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 163704403 t fired, 3209891 attempts, .
172 EF FNDP 75/379 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 2081800 t fired, 10695 attempts, .
173 EF STEQ 75/379 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
228 EF EXCL 46/714 2/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 334308 m, 4161 m/sec, 420253 t fired, .
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BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-00: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-02: EF true tandem / relaxed
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-04: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-05: AG true skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-07: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-08: EF false preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-13: AG true preprocessing
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09: EF 0 3 2 0 3 0 0 2
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-10: AG 0 5 0 0 4 0 0 1
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-11: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-14: AG 0 5 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
143 EF FNDP 80/324 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 178051404 t fired, 3491205 attempts, .
172 EF FNDP 80/374 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 2205620 t fired, 11394 attempts, .
173 EF STEQ 80/374 0/5 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-09 sara is running.
228 EF EXCL 52/714 2/32 BridgeAndVehicles-COL-V50P50N10-ReachabilityCardinality-06 363692 m, 5876 m/sec, 458967 t fired, .
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/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 378 Killed lola --conf=$BIN_DIR/configfiles/reachabilitycardinalityconf --formula=$DIR/ReachabilityCardinality.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V50P50N10"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-COL-V50P50N10, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r038-tajo-167813691000094"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V50P50N10.tgz
mv BridgeAndVehicles-COL-V50P50N10 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;