About the Execution of LoLA for BridgeAndVehicles-COL-V50P20N50
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 13828.056 | 43742.00 | 136293.00 | 211.20 | FTFFFTTTFFFFTTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2023-input.r038-tajo-167813691000086.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is BridgeAndVehicles-COL-V50P20N50, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r038-tajo-167813691000086
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 548K
-rw-r--r-- 1 mcc users 8.1K Feb 25 12:46 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Feb 25 12:46 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.0K Feb 25 12:42 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 25 12:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Feb 25 15:36 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:36 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 15:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 25 14:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 140K Feb 25 14:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 14:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 25 14:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 15:36 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:36 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 10 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 44K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14
FORMULA_NAME BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1678405610290
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=BridgeAndVehicles-COL-V50P20N50
Not applying reductions.
Model is COL
ReachabilityCardinality COL
starting LoLA
BK_INPUT BridgeAndVehicles-COL-V50P20N50
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678405654032
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: TR BINDINGS
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 75 (type SKEL/FNDP) for 36 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type SKEL/EQUN) for 36 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type SKEL/SRCH) for 36 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SKEL/SRCH) for 36 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 78 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: result : true
lola: markings : 21
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: TR BINDINGS DONE
lola: Places: 168, Transitions: 5408
lola: CANCELED task # 75 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 76 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 79 (type SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 49 (type SKEL/FNDP) for 6 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SKEL/EQUN) for 6 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type SKEL/SRCH) for 6 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type SKEL/SRCH) for 6 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 75 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 19
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH INITIAL
lola: LAUNCH task # 41 (type SKEL/CNST) for 39 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 87 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 49 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 50 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 86 (type SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 82 (type SKEL/FNDP) for 45 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SKEL/EQUN) for 45 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type SKEL/SRCH) for 45 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 41 (type SKEL/CNST) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 101 (type SKEL/FNDP) for 0 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 89 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 82 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 84 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 60 (type SKEL/FNDP) for 12 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SKEL/EQUN) for 12 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type SKEL/SRCH) for 12 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-76.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-50.sara.
sara: error: :5: error: syntax error, unexpected $end, expecting KEY_TRANSITION
sara: error while reading Petri net from file -- aborting [#04]
sara: see manual for a documentation of this error
sara: last error message: No such file or directory
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-84.sara.
sara: error: :5: error: syntax error, unexpected $end, expecting KEY_TRANSITION
sara: error while reading Petri net from file -- aborting [#04]
sara: see manual for a documentation of this error
sara: last error message: No such file or directory
lola: @ trans enregistrement_A
lola: @ trans decision
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-61.sara.
lola: FINISHED task # 76 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: result : true
lola: FINISHED task # 101 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 61
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: @ trans altern_cpt
lola: @ trans autorisation_A
lola: @ trans liberation_A
lola: @ trans enregistrement_B
lola: @ trans timeout_A
lola: LAUNCH task # 108 (type SKEL/FNDP) for 27 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 84 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15
lola: result : unknown
lola: FINISHED task # 50 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02
lola: result : unknown
lola: @ trans timeout_B
lola: FINISHED task # 61 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04
lola: result : false
lola: @ trans liberation_B
lola: CANCELED task # 60 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 63 (type SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 116 (type SKEL/FNDP) for 18 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 117 (type SKEL/EQUN) for 18 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 119 (type SKEL/SRCH) for 18 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: @ trans basculement
lola: @ trans autorisation_B
lola: FINISHED task # 60 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04
lola: result : unknown
lola: fired transitions : 26771
lola: tried executions : 80
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 119 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 116 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 117 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 134 (type SKEL/FNDP) for 24 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 135 (type SKEL/EQUN) for 24 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 140 (type SKEL/SRCH) for 24 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-117.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 117 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06
lola: result : false
lola: FINISHED task # 140 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08
lola: result : false
lola: markings : 310437
lola: fired transitions : 589196
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 134 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 135 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 152 (type SKEL/FNDP) for 30 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 153 (type SKEL/EQUN) for 30 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 155 (type SKEL/SRCH) for 30 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 134 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08
lola: result : unknown
lola: fired transitions : 854183
lola: tried executions : 2754
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 155 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 152 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 153 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 68 (type SKEL/FNDP) for 33 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type SKEL/EQUN) for 33 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SKEL/SRCH) for 33 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 71 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
lola: result : true
lola: markings : 1716
lola: fired transitions : 3355
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 68 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 69 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 53 (type SKEL/FNDP) for 3 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/EQUN) for 3 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SKEL/SRCH) for 3 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01: AG 0 2 3 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09: EF 0 4 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14: EF 0 5 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 4/449 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01 1265040 t fired, 2 attempts, .
54 EF STEQ 4/449 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01 sara not yet started (preprocessing).
56 EF SRCH 4/514 1/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01 2459428 m, 491885 m/sec, 7568168 t fired, .
108 EF FNDP 5/513 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09 7029960 t fired, 7029961 attempts, .
Time elapsed: 5 secs. Pages in use: 1
# running tasks: 4 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-135.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01: AG 0 2 3 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09: EF 0 4 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14: EF 0 5 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 9/445 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01 18661684 t fired, 19 attempts, .
54 EF STEQ 9/445 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01 sara not yet started (preprocessing).
56 EF SRCH 9/510 1/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01 4086342 m, 325382 m/sec, 12593117 t fired, .
108 EF FNDP 10/509 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09 13884224 t fired, 13884225 attempts, .
Time elapsed: 10 secs. Pages in use: 1
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 56 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01
lola: result : false
lola: markings : 4781698
lola: fired transitions : 14734484
lola: time used : 11.000000
lola: memory pages used : 1
lola: CANCELED task # 53 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 54 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 93 (type SKEL/FNDP) for 42 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type SKEL/EQUN) for 42 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 96 (type SKEL/SRCH) for 42 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01
lola: result : unknown
lola: fired transitions : 22621987
lola: tried executions : 24
lola: time used : 11.000000
lola: memory pages used : 0
lola: FINISHED task # 135 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08
lola: result : false
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09: EF 0 4 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14: EF 0 2 3 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
93 EF FNDP 3/511 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14 1352593 t fired, 181938 attempts, .
94 EF STEQ 3/597 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14 sara not yet started (preprocessing).
96 EF SRCH 3/597 1/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14 2023246 m, 404649 m/sec, 5785368 t fired, .
108 EF FNDP 15/587 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09 23204528 t fired, 23204529 attempts, .
Time elapsed: 15 secs. Pages in use: 1
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05: AG 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09: EF 0 4 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14: EF 0 2 3 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
93 EF FNDP 8/509 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14 3396743 t fired, 448413 attempts, .
94 EF STEQ 8/595 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14 sara not yet started (preprocessing).
96 EF SRCH 8/595 1/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14 4742767 m, 543904 m/sec, 14180460 t fired, .
108 EF FNDP 20/585 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09 31814052 t fired, 31814053 attempts, .
Time elapsed: 20 secs. Pages in use: 1
# running tasks: 4 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-54.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 54 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01
lola: result : false
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-94.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 94 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14
lola: result : false
lola: CANCELED task # 93 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 96 (type SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-153.sara.
sara: error: :5: error: syntax error, unexpected $end, expecting KEY_TRANSITION
sara: error while reading Petri net from file -- aborting [#04]
sara: see manual for a documentation of this error
sara: last error message: No such file or directory
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-69.sara.
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 128 (type SKEL/FNDP) for 21 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 129 (type SKEL/EQUN) for 21 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 131 (type SKEL/SRCH) for 21 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 93 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14
lola: result : unknown
lola: fired transitions : 5576874
lola: tried executions : 732824
lola: time used : 13.000000
lola: memory pages used : 0
lola: FINISHED task # 131 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: result : true
lola: markings : 39
lola: fired transitions : 38
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 128 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 129 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 139 (type SKEL/FNDP) for 15 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 144 (type SKEL/EQUN) for 15 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 148 (type SKEL/SRCH) for 15 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 148 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 139 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 144 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 126 (type SKEL/FNDP) for 9 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 137 (type SKEL/EQUN) for 9 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 142 (type SKEL/SRCH) for 9 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 153 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10
lola: result : unknown
lola: FINISHED task # 69 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
lola: result : true
lola: FINISHED task # 128 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: result : true
lola: fired transitions : 37
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03: EF 0 2 3 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09: EF 0 4 1 0 0 0 0 0
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 3 0 0 2
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF FNDP 25/1775 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09 47167503 t fired, 47167504 attempts, .
126 EF FNDP 0/1191 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03 136946 t fired, 682 attempts, .
137 EF STEQ 0/1787 0/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03 sara not yet started (preprocessing).
142 EF SRCH 0/1191 1/5 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03 109772 m, 21954 m/sec, 267722 t fired, .
Time elapsed: 25 secs. Pages in use: 1
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 142 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03
lola: result : false
lola: markings : 160559
lola: fired transitions : 392358
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 126 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 137 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 109 (type SKEL/EQUN) for 27 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 111 (type SKEL/SRCH) for 27 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 112 (type SKEL/SRCH) for 27 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 111 (type SKEL/SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 108 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 109 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 112 (type SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09 (obsolete)
lola: FINISHED task # 126 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 160217
lola: tried executions : 799
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 108 (type SKEL/FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09
lola: result : unknown
lola: fired transitions : 47286160
lola: tried executions : 47286161
lola: time used : 25.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-137.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: FINISHED task # 137 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03
lola: result : false
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-144.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: FINISHED task # 144 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05
lola: result : false
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-129.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-109.sara.
sara: error: :5: error: syntax error, unexpected $end, expecting KEY_TRANSITION
sara: error while reading Petri net from file -- aborting [#04]
sara: see manual for a documentation of this error
sara: last error message: No such file or directory
lola: FINISHED task # 129 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: result : true
lola: FINISHED task # 109 (type SKEL/EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 3 0 0 2
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 30 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Rule S: 0 transitions removed,0 places removed
lola: planning for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14 stopped (result already fixed).
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 3 0 0 2
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 35 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 162 (type EXCL) for 36 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: time limit : 890 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 158 (type FNDP) for 36 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 159 (type EQUN) for 36 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 161 (type SRCH) for 36 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 161 (type SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: result : true
lola: markings : 21
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 158 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 159 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 162 (type EXCL) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-159.sara.
lola: FINISHED task # 158 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 19
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12: EF true tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11: AG 0 0 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 40 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 169 (type EXCL) for 0 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00
lola: time limit : 1779 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 165 (type FNDP) for 0 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 166 (type EQUN) for 0 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 168 (type SRCH) for 0 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 165 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 61
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 166 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 168 (type SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 169 (type EXCL) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 175 (type EXCL) for 21 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: time limit : 1779 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 171 (type FNDP) for 21 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 172 (type EQUN) for 21 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 174 (type SRCH) for 21 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 171 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07
lola: result : true
lola: fired transitions : 57
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 172 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 174 (type SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 175 (type EXCL) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-166.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-172.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 182 (type EXCL) for 33 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
lola: time limit : 3557 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 178 (type FNDP) for 33 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 179 (type EQUN) for 33 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 181 (type SRCH) for 33 BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 178 (type FNDP) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 180
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 179 (type EQUN) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 181 (type SRCH) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 182 (type EXCL) for BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-00: AG false findpath
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-01: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-02: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-03: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-04: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-06: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-07: EF true findpath
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-08: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-09: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-11: AG false findpath
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-12: EF true tandem / insertion
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-13: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-14: EF false skeleton: state equation
BridgeAndVehicles-COL-V50P20N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
Time elapsed: 43 secs. Pages in use: 3
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V50P20N50"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-COL-V50P20N50, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r038-tajo-167813691000086"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V50P20N50.tgz
mv BridgeAndVehicles-COL-V50P20N50 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;