About the Execution of LoLa+red for BART-COL-060
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1118.275 | 38819.00 | 47305.00 | 42.80 | T?FFTFFFTTFTTTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813596000746.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is BART-COL-060, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813596000746
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 656K
-rw-r--r-- 1 mcc users 8.2K Feb 26 07:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 26 07:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 26 05:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 26 05:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 15:35 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:35 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:35 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:35 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 12:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 118K Feb 26 12:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 26 08:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 26 08:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:35 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:35 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 219K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BART-COL-060-CTLFireability-00
FORMULA_NAME BART-COL-060-CTLFireability-01
FORMULA_NAME BART-COL-060-CTLFireability-02
FORMULA_NAME BART-COL-060-CTLFireability-03
FORMULA_NAME BART-COL-060-CTLFireability-04
FORMULA_NAME BART-COL-060-CTLFireability-05
FORMULA_NAME BART-COL-060-CTLFireability-06
FORMULA_NAME BART-COL-060-CTLFireability-07
FORMULA_NAME BART-COL-060-CTLFireability-08
FORMULA_NAME BART-COL-060-CTLFireability-09
FORMULA_NAME BART-COL-060-CTLFireability-10
FORMULA_NAME BART-COL-060-CTLFireability-11
FORMULA_NAME BART-COL-060-CTLFireability-12
FORMULA_NAME BART-COL-060-CTLFireability-13
FORMULA_NAME BART-COL-060-CTLFireability-14
FORMULA_NAME BART-COL-060-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678355664786
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=BART-COL-060
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 09:54:27] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 09:54:27] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 09:54:27] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-09 09:54:27] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-09 09:54:28] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 899 ms
[2023-03-09 09:54:28] [INFO ] Detected 3 constant HL places corresponding to 10373 PT places.
[2023-03-09 09:54:28] [INFO ] Imported 4 HL places and 7 HL transitions for a total of 25133 PT places and 8.443377072E10 transition bindings in 131 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 19 ms.
[2023-03-09 09:54:28] [INFO ] Built PT skeleton of HLPN with 4 places and 7 transitions 26 arcs in 4 ms.
[2023-03-09 09:54:28] [INFO ] Skeletonized 0 HLPN properties in 1 ms. Removed 16 properties that had guard overlaps.
Symmetric sort wr.t. initial and guards and successors and join/free detected :trainid
Symmetric sort wr.t. initial detected :trainid
Symmetric sort wr.t. initial and guards detected :trainid
Applying symmetric unfolding of full symmetric sort :trainid domain size was 60
Domain [distance(41), speed(6), distance(41)] of place NewDistTable breaks symmetries in sort distance
Arc [3:1*[$db, (MOD (ADD $tsp 1) 6), $da2]] contains successor/predecessor on variables of sort speed
[2023-03-09 09:54:29] [INFO ] Unfolded HLPN to a Petri net with 10619 places and 323 transitions 601 arcs in 897 ms.
[2023-03-09 09:54:29] [INFO ] Unfolded 16 HLPN properties in 2 ms.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
[2023-03-09 09:54:29] [INFO ] Reduced 35 identical enabling conditions.
Deduced a syphon composed of 10215 places in 2 ms
Reduce places removed 10487 places and 121 transitions.
Support contains 132 out of 132 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Applied a total of 0 rules in 6 ms. Remains 132 /132 variables (removed 0) and now considering 202/202 (removed 0) transitions.
// Phase 1: matrix 202 rows 132 cols
[2023-03-09 09:54:29] [INFO ] Computed 1 place invariants in 16 ms
[2023-03-09 09:54:29] [INFO ] Implicit Places using invariants in 244 ms returned []
[2023-03-09 09:54:29] [INFO ] Invariant cache hit.
[2023-03-09 09:54:30] [INFO ] Implicit Places using invariants and state equation in 190 ms returned []
Implicit Place search using SMT with State Equation took 464 ms to find 0 implicit places.
[2023-03-09 09:54:30] [INFO ] Invariant cache hit.
[2023-03-09 09:54:30] [INFO ] Dead Transitions using invariants and state equation in 239 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 717 ms. Remains : 132/132 places, 202/202 transitions.
Support contains 132 out of 132 places after structural reductions.
[2023-03-09 09:54:30] [INFO ] Flatten gal took : 72 ms
[2023-03-09 09:54:30] [INFO ] Flatten gal took : 26 ms
[2023-03-09 09:54:30] [INFO ] Input system was already deterministic with 202 transitions.
Finished random walk after 2190 steps, including 0 resets, run visited all 21 properties in 29 ms. (steps per millisecond=75 )
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 18 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 23 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 202 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 132 transition count 201
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 131 transition count 201
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 10 place count 127 transition count 197
Applied a total of 10 rules in 24 ms. Remains 127 /132 variables (removed 5) and now considering 197/202 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 127/132 places, 197/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 6 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 6 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 197 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Applied a total of 0 rules in 1 ms. Remains 132 /132 variables (removed 0) and now considering 202/202 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 132/132 places, 202/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 6 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 6 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 202 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 123 transition count 193
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 123 transition count 193
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 24 place count 117 transition count 187
Iterating global reduction 0 with 6 rules applied. Total rules applied 30 place count 117 transition count 187
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 33 place count 114 transition count 184
Iterating global reduction 0 with 3 rules applied. Total rules applied 36 place count 114 transition count 184
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 39 place count 111 transition count 181
Iterating global reduction 0 with 3 rules applied. Total rules applied 42 place count 111 transition count 181
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 45 place count 108 transition count 178
Iterating global reduction 0 with 3 rules applied. Total rules applied 48 place count 108 transition count 178
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 51 place count 105 transition count 175
Iterating global reduction 0 with 3 rules applied. Total rules applied 54 place count 105 transition count 175
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 56 place count 103 transition count 173
Iterating global reduction 0 with 2 rules applied. Total rules applied 58 place count 103 transition count 173
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 60 place count 101 transition count 171
Iterating global reduction 0 with 2 rules applied. Total rules applied 62 place count 101 transition count 171
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 63 place count 100 transition count 170
Iterating global reduction 0 with 1 rules applied. Total rules applied 64 place count 100 transition count 170
Applied a total of 64 rules in 12 ms. Remains 100 /132 variables (removed 32) and now considering 170/202 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 100/132 places, 170/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 4 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 170 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 129 transition count 199
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 129 transition count 199
Applied a total of 6 rules in 3 ms. Remains 129 /132 variables (removed 3) and now considering 199/202 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 129/132 places, 199/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 6 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 199 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Performed 23 Post agglomeration using F-continuation condition.Transition count delta: 23
Iterating post reduction 0 with 23 rules applied. Total rules applied 23 place count 132 transition count 179
Reduce places removed 23 places and 0 transitions.
Iterating post reduction 1 with 23 rules applied. Total rules applied 46 place count 109 transition count 179
Applied a total of 46 rules in 7 ms. Remains 109 /132 variables (removed 23) and now considering 179/202 (removed 23) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 109/132 places, 179/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 4 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 179 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Applied a total of 0 rules in 1 ms. Remains 132 /132 variables (removed 0) and now considering 202/202 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 132/132 places, 202/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 6 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 6 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 202 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 123 transition count 193
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 123 transition count 193
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 24 place count 117 transition count 187
Iterating global reduction 0 with 6 rules applied. Total rules applied 30 place count 117 transition count 187
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 33 place count 114 transition count 184
Iterating global reduction 0 with 3 rules applied. Total rules applied 36 place count 114 transition count 184
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 39 place count 111 transition count 181
Iterating global reduction 0 with 3 rules applied. Total rules applied 42 place count 111 transition count 181
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 45 place count 108 transition count 178
Iterating global reduction 0 with 3 rules applied. Total rules applied 48 place count 108 transition count 178
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 51 place count 105 transition count 175
Iterating global reduction 0 with 3 rules applied. Total rules applied 54 place count 105 transition count 175
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 56 place count 103 transition count 173
Iterating global reduction 0 with 2 rules applied. Total rules applied 58 place count 103 transition count 173
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 60 place count 101 transition count 171
Iterating global reduction 0 with 2 rules applied. Total rules applied 62 place count 101 transition count 171
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 63 place count 100 transition count 170
Iterating global reduction 0 with 1 rules applied. Total rules applied 64 place count 100 transition count 170
Applied a total of 64 rules in 16 ms. Remains 100 /132 variables (removed 32) and now considering 170/202 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 100/132 places, 170/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 170 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Applied a total of 0 rules in 1 ms. Remains 132 /132 variables (removed 0) and now considering 202/202 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 132/132 places, 202/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 6 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 6 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 202 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 109 transition count 179
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 109 transition count 179
Discarding 19 places :
Symmetric choice reduction at 0 with 19 rule applications. Total rules 65 place count 90 transition count 160
Iterating global reduction 0 with 19 rules applied. Total rules applied 84 place count 90 transition count 160
Applied a total of 84 rules in 6 ms. Remains 90 /132 variables (removed 42) and now considering 160/202 (removed 42) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 90/132 places, 160/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 3 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 160 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Applied a total of 0 rules in 1 ms. Remains 132 /132 variables (removed 0) and now considering 202/202 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 132/132 places, 202/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 202 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 129 transition count 199
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 129 transition count 199
Applied a total of 6 rules in 2 ms. Remains 129 /132 variables (removed 3) and now considering 199/202 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 129/132 places, 199/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 4 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 199 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Applied a total of 0 rules in 1 ms. Remains 132 /132 variables (removed 0) and now considering 202/202 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 132/132 places, 202/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 202 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Applied a total of 0 rules in 1 ms. Remains 132 /132 variables (removed 0) and now considering 202/202 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 132/132 places, 202/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 202 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 123 transition count 193
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 123 transition count 193
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 24 place count 117 transition count 187
Iterating global reduction 0 with 6 rules applied. Total rules applied 30 place count 117 transition count 187
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 33 place count 114 transition count 184
Iterating global reduction 0 with 3 rules applied. Total rules applied 36 place count 114 transition count 184
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 39 place count 111 transition count 181
Iterating global reduction 0 with 3 rules applied. Total rules applied 42 place count 111 transition count 181
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 45 place count 108 transition count 178
Iterating global reduction 0 with 3 rules applied. Total rules applied 48 place count 108 transition count 178
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 51 place count 105 transition count 175
Iterating global reduction 0 with 3 rules applied. Total rules applied 54 place count 105 transition count 175
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 56 place count 103 transition count 173
Iterating global reduction 0 with 2 rules applied. Total rules applied 58 place count 103 transition count 173
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 60 place count 101 transition count 171
Iterating global reduction 0 with 2 rules applied. Total rules applied 62 place count 101 transition count 171
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 63 place count 100 transition count 170
Iterating global reduction 0 with 1 rules applied. Total rules applied 64 place count 100 transition count 170
Applied a total of 64 rules in 6 ms. Remains 100 /132 variables (removed 32) and now considering 170/202 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 100/132 places, 170/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 4 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 4 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 170 transitions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Applied a total of 0 rules in 1 ms. Remains 132 /132 variables (removed 0) and now considering 202/202 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 132/132 places, 202/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 5 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 202 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 132/132 places, 202/202 transitions.
Applied a total of 0 rules in 2 ms. Remains 132 /132 variables (removed 0) and now considering 202/202 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 132/132 places, 202/202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 8 ms
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 6 ms
[2023-03-09 09:54:31] [INFO ] Input system was already deterministic with 202 transitions.
[2023-03-09 09:54:31] [INFO ] Flatten gal took : 17 ms
[2023-03-09 09:54:32] [INFO ] Flatten gal took : 16 ms
[2023-03-09 09:54:32] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 16 ms.
[2023-03-09 09:54:32] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 132 places, 202 transitions and 404 arcs took 1 ms.
Total runtime 4738 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT BART-COL-060
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/380
CTLFireability
FORMULA BART-COL-060-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-060-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678355703605
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/380/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/380/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/380/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 7 (type EXCL) for 6 BART-COL-060-CTLFireability-02
lola: time limit : 143 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 56 (type FNDP) for 12 BART-COL-060-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 12 BART-COL-060-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type SRCH) for 12 BART-COL-060-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 59 (type SRCH) for BART-COL-060-CTLFireability-04
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 56 (type FNDP) for BART-COL-060-CTLFireability-04
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 57 (type EQUN) for BART-COL-060-CTLFireability-04 (obsolete)
lola: FINISHED task # 7 (type EXCL) for BART-COL-060-CTLFireability-02
lola: result : false
lola: markings : 3032
lola: fired transitions : 3032
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 47 (type EXCL) for 46 BART-COL-060-CTLFireability-14
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for BART-COL-060-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 BART-COL-060-CTLFireability-13
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 61 (type FNDP) for 49 BART-COL-060-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type EQUN) for 49 BART-COL-060-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SRCH) for 49 BART-COL-060-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 44 (type EXCL) for BART-COL-060-CTLFireability-13
lola: result : true
lola: markings : 1470
lola: fired transitions : 3318
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 BART-COL-060-CTLFireability-12
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type SRCH) for BART-COL-060-CTLFireability-15
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 41 (type EXCL) for BART-COL-060-CTLFireability-12
lola: result : true
lola: markings : 666
lola: fired transitions : 673
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 BART-COL-060-CTLFireability-09
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type FNDP) for BART-COL-060-CTLFireability-15
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 62 (type EQUN) for BART-COL-060-CTLFireability-15 (obsolete)
lola: FINISHED task # 62 (type EQUN) for BART-COL-060-CTLFireability-15
lola: result : unknown
sara: try reading problem file /home/mcc/execution/380/CTLFireability-57.sara.
lola: FINISHED task # 32 (type EXCL) for BART-COL-060-CTLFireability-09
lola: result : true
lola: markings : 41
lola: fired transitions : 152
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 24 BART-COL-060-CTLFireability-08
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for BART-COL-060-CTLFireability-08
lola: result : true
lola: markings : 678
lola: fired transitions : 1159
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 BART-COL-060-CTLFireability-06
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 57 (type EQUN) for BART-COL-060-CTLFireability-04
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 19 (type EXCL) for BART-COL-060-CTLFireability-06
lola: result : false
lola: markings : 2365
lola: fired transitions : 2365
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 65 (type EXCL) for 34 BART-COL-060-CTLFireability-10
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 65 (type EXCL) for BART-COL-060-CTLFireability-10
lola: result : true
lola: markings : 31
lola: fired transitions : 30
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 BART-COL-060-CTLFireability-11
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for BART-COL-060-CTLFireability-11
lola: result : true
lola: markings : 3299
lola: fired transitions : 4667
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 BART-COL-060-CTLFireability-07
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for BART-COL-060-CTLFireability-07
lola: result : false
lola: markings : 3299
lola: fired transitions : 4670
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 BART-COL-060-CTLFireability-05
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for BART-COL-060-CTLFireability-05
lola: result : false
lola: markings : 1333
lola: fired transitions : 2919
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 BART-COL-060-CTLFireability-03
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for BART-COL-060-CTLFireability-03
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 BART-COL-060-CTLFireability-01
lola: time limit : 1199 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-COL-060-CTLFireability-02: CTL false CTL model checker
BART-COL-060-CTLFireability-03: CTL false CTL model checker
BART-COL-060-CTLFireability-04: EF true findpath
BART-COL-060-CTLFireability-05: CTL false CTL model checker
BART-COL-060-CTLFireability-06: CTL false CTL model checker
BART-COL-060-CTLFireability-07: CTL false CTL model checker
BART-COL-060-CTLFireability-08: DISJ true CTL model checker
BART-COL-060-CTLFireability-09: CTL true CTL model checker
BART-COL-060-CTLFireability-10: AXAG false state space /EXEF
BART-COL-060-CTLFireability-11: CTL true CTL model checker
BART-COL-060-CTLFireability-12: CTL true CTL model checker
BART-COL-060-CTLFireability-13: CTL true CTL model checker
BART-COL-060-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-060-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-COL-060-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
BART-COL-060-CTLFireability-15: DISJ 0 1 0 0 5 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 4/1199 7/32 BART-COL-060-CTLFireability-01 1395464 m, 279092 m/sec, 3410500 t fired, .
Time elapsed: 6 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-COL-060-CTLFireability-02: CTL false CTL model checker
BART-COL-060-CTLFireability-03: CTL false CTL model checker
BART-COL-060-CTLFireability-04: EF true findpath
BART-COL-060-CTLFireability-05: CTL false CTL model checker
BART-COL-060-CTLFireability-06: CTL false CTL model checker
BART-COL-060-CTLFireability-07: CTL false CTL model checker
BART-COL-060-CTLFireability-08: DISJ true CTL model checker
BART-COL-060-CTLFireability-09: CTL true CTL model checker
BART-COL-060-CTLFireability-10: AXAG false state space /EXEF
BART-COL-060-CTLFireability-11: CTL true CTL model checker
BART-COL-060-CTLFireability-12: CTL true CTL model checker
BART-COL-060-CTLFireability-13: CTL true CTL model checker
BART-COL-060-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-060-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-COL-060-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
BART-COL-060-CTLFireability-15: DISJ 0 1 0 0 5 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 9/1199 13/32 BART-COL-060-CTLFireability-01 2794461 m, 279799 m/sec, 7502004 t fired, .
Time elapsed: 11 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-COL-060-CTLFireability-02: CTL false CTL model checker
BART-COL-060-CTLFireability-03: CTL false CTL model checker
BART-COL-060-CTLFireability-04: EF true findpath
BART-COL-060-CTLFireability-05: CTL false CTL model checker
BART-COL-060-CTLFireability-06: CTL false CTL model checker
BART-COL-060-CTLFireability-07: CTL false CTL model checker
BART-COL-060-CTLFireability-08: DISJ true CTL model checker
BART-COL-060-CTLFireability-09: CTL true CTL model checker
BART-COL-060-CTLFireability-10: AXAG false state space /EXEF
BART-COL-060-CTLFireability-11: CTL true CTL model checker
BART-COL-060-CTLFireability-12: CTL true CTL model checker
BART-COL-060-CTLFireability-13: CTL true CTL model checker
BART-COL-060-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-060-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-COL-060-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
BART-COL-060-CTLFireability-15: DISJ 0 1 0 0 5 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 14/1199 20/32 BART-COL-060-CTLFireability-01 4164985 m, 274104 m/sec, 11663578 t fired, .
Time elapsed: 16 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-COL-060-CTLFireability-02: CTL false CTL model checker
BART-COL-060-CTLFireability-03: CTL false CTL model checker
BART-COL-060-CTLFireability-04: EF true findpath
BART-COL-060-CTLFireability-05: CTL false CTL model checker
BART-COL-060-CTLFireability-06: CTL false CTL model checker
BART-COL-060-CTLFireability-07: CTL false CTL model checker
BART-COL-060-CTLFireability-08: DISJ true CTL model checker
BART-COL-060-CTLFireability-09: CTL true CTL model checker
BART-COL-060-CTLFireability-10: AXAG false state space /EXEF
BART-COL-060-CTLFireability-11: CTL true CTL model checker
BART-COL-060-CTLFireability-12: CTL true CTL model checker
BART-COL-060-CTLFireability-13: CTL true CTL model checker
BART-COL-060-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-060-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-COL-060-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
BART-COL-060-CTLFireability-15: DISJ 0 1 0 0 5 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 19/1199 26/32 BART-COL-060-CTLFireability-01 5440323 m, 255067 m/sec, 15766411 t fired, .
Time elapsed: 21 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-COL-060-CTLFireability-02: CTL false CTL model checker
BART-COL-060-CTLFireability-03: CTL false CTL model checker
BART-COL-060-CTLFireability-04: EF true findpath
BART-COL-060-CTLFireability-05: CTL false CTL model checker
BART-COL-060-CTLFireability-06: CTL false CTL model checker
BART-COL-060-CTLFireability-07: CTL false CTL model checker
BART-COL-060-CTLFireability-08: DISJ true CTL model checker
BART-COL-060-CTLFireability-09: CTL true CTL model checker
BART-COL-060-CTLFireability-10: AXAG false state space /EXEF
BART-COL-060-CTLFireability-11: CTL true CTL model checker
BART-COL-060-CTLFireability-12: CTL true CTL model checker
BART-COL-060-CTLFireability-13: CTL true CTL model checker
BART-COL-060-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-060-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-COL-060-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
BART-COL-060-CTLFireability-15: DISJ 0 1 0 0 5 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 24/1199 32/32 BART-COL-060-CTLFireability-01 6834054 m, 278746 m/sec, 19917195 t fired, .
Time elapsed: 26 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for BART-COL-060-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-COL-060-CTLFireability-02: CTL false CTL model checker
BART-COL-060-CTLFireability-03: CTL false CTL model checker
BART-COL-060-CTLFireability-04: EF true findpath
BART-COL-060-CTLFireability-05: CTL false CTL model checker
BART-COL-060-CTLFireability-06: CTL false CTL model checker
BART-COL-060-CTLFireability-07: CTL false CTL model checker
BART-COL-060-CTLFireability-08: DISJ true CTL model checker
BART-COL-060-CTLFireability-09: CTL true CTL model checker
BART-COL-060-CTLFireability-10: AXAG false state space /EXEF
BART-COL-060-CTLFireability-11: CTL true CTL model checker
BART-COL-060-CTLFireability-12: CTL true CTL model checker
BART-COL-060-CTLFireability-13: CTL true CTL model checker
BART-COL-060-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-060-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-COL-060-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
BART-COL-060-CTLFireability-15: DISJ 0 1 0 0 5 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 31 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 BART-COL-060-CTLFireability-00
lola: time limit : 1784 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for BART-COL-060-CTLFireability-00
lola: result : true
lola: markings : 670
lola: fired transitions : 2813
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 49 BART-COL-060-CTLFireability-15
lola: time limit : 3569 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for BART-COL-060-CTLFireability-15
lola: result : true
lola: markings : 26932
lola: fired transitions : 27916
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-COL-060-CTLFireability-00: CTL true CTL model checker
BART-COL-060-CTLFireability-01: CTL unknown AGGR
BART-COL-060-CTLFireability-02: CTL false CTL model checker
BART-COL-060-CTLFireability-03: CTL false CTL model checker
BART-COL-060-CTLFireability-04: EF true findpath
BART-COL-060-CTLFireability-05: CTL false CTL model checker
BART-COL-060-CTLFireability-06: CTL false CTL model checker
BART-COL-060-CTLFireability-07: CTL false CTL model checker
BART-COL-060-CTLFireability-08: DISJ true CTL model checker
BART-COL-060-CTLFireability-09: CTL true CTL model checker
BART-COL-060-CTLFireability-10: AXAG false state space /EXEF
BART-COL-060-CTLFireability-11: CTL true CTL model checker
BART-COL-060-CTLFireability-12: CTL true CTL model checker
BART-COL-060-CTLFireability-13: CTL true CTL model checker
BART-COL-060-CTLFireability-14: CTL true CTL model checker
BART-COL-060-CTLFireability-15: DISJ true CTL model checker
Time elapsed: 31 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-060"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is BART-COL-060, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813596000746"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-060.tgz
mv BART-COL-060 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;