Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595300338.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Angiogenesis-PT-15, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595300338
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 8.5K Feb 26 14:55 CTLCardinality.txt
-rw-r--r-- 1 mcc users 85K Feb 26 14:55 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 26 14:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 26 14:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:31 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:31 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:31 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:31 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.7K Feb 26 14:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 26 14:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Feb 26 14:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 89K Feb 26 14:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 33K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-00
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-01
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-02
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-03
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-04
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-05
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-06
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-07
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-08
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-09
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-10
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-11
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-12
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-13
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-14
FORMULA_NAME Angiogenesis-PT-15-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678347424017

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Angiogenesis-PT-15
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 07:37:06] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 07:37:06] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 07:37:06] [INFO ] Load time of PNML (sax parser for PT used): 36 ms
[2023-03-09 07:37:06] [INFO ] Transformed 39 places.
[2023-03-09 07:37:06] [INFO ] Transformed 64 transitions.
[2023-03-09 07:37:06] [INFO ] Parsed PT model containing 39 places and 64 transitions and 185 arcs in 116 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Initial state reduction rules removed 1 formulas.
FORMULA Angiogenesis-PT-15-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 36 out of 39 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 64/64 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 38 transition count 64
Applied a total of 1 rules in 16 ms. Remains 38 /39 variables (removed 1) and now considering 64/64 (removed 0) transitions.
// Phase 1: matrix 64 rows 38 cols
[2023-03-09 07:37:06] [INFO ] Computed 7 place invariants in 11 ms
[2023-03-09 07:37:06] [INFO ] Implicit Places using invariants in 276 ms returned []
[2023-03-09 07:37:06] [INFO ] Invariant cache hit.
[2023-03-09 07:37:06] [INFO ] Implicit Places using invariants and state equation in 116 ms returned []
Implicit Place search using SMT with State Equation took 428 ms to find 0 implicit places.
[2023-03-09 07:37:06] [INFO ] Invariant cache hit.
[2023-03-09 07:37:06] [INFO ] Dead Transitions using invariants and state equation in 95 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 38/39 places, 64/64 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 541 ms. Remains : 38/39 places, 64/64 transitions.
Support contains 36 out of 38 places after structural reductions.
[2023-03-09 07:37:07] [INFO ] Flatten gal took : 24 ms
[2023-03-09 07:37:07] [INFO ] Flatten gal took : 11 ms
[2023-03-09 07:37:07] [INFO ] Input system was already deterministic with 64 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 142 ms. (steps per millisecond=70 ) properties (out of 50) seen :29
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 21) seen :5
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 16) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 13) seen :0
Running SMT prover for 13 properties.
[2023-03-09 07:37:07] [INFO ] Invariant cache hit.
[2023-03-09 07:37:07] [INFO ] [Real]Absence check using 7 positive place invariants in 2 ms returned sat
[2023-03-09 07:37:07] [INFO ] After 29ms SMT Verify possible using state equation in real domain returned unsat :0 sat :5 real:8
[2023-03-09 07:37:07] [INFO ] After 50ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :5 real:8
Attempting to minimize the solution found.
Minimization took 15 ms.
[2023-03-09 07:37:07] [INFO ] After 132ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :3 real:10
[2023-03-09 07:37:07] [INFO ] [Nat]Absence check using 7 positive place invariants in 1 ms returned sat
[2023-03-09 07:37:07] [INFO ] After 45ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :13
[2023-03-09 07:37:07] [INFO ] After 106ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :13
Attempting to minimize the solution found.
Minimization took 50 ms.
[2023-03-09 07:37:07] [INFO ] After 208ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :13
Finished Parikh walk after 211 steps, including 2 resets, run visited all 2 properties in 3 ms. (steps per millisecond=70 )
Parikh walk visited 13 properties in 45 ms.
[2023-03-09 07:37:07] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:37:07] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:37:07] [INFO ] Input system was already deterministic with 64 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 2 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:07] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:37:07] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 5 place count 36 transition count 63
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 36 transition count 62
Applied a total of 6 rules in 10 ms. Remains 36 /38 variables (removed 2) and now considering 62/64 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 36/38 places, 62/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 6 times.
Drop transitions removed 6 transitions
Iterating global reduction 0 with 6 rules applied. Total rules applied 9 place count 36 transition count 63
Applied a total of 9 rules in 3 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 5 place count 36 transition count 63
Applied a total of 5 rules in 3 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 63 transitions.
Incomplete random walk after 10012 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=1251 ) properties (out of 1) seen :0
Finished Best-First random walk after 4766 steps, including 1 resets, run visited all 1 properties in 5 ms. (steps per millisecond=953 )
FORMULA Angiogenesis-PT-15-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 7 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 5 place count 36 transition count 63
Applied a total of 5 rules in 4 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Input system was already deterministic with 64 transitions.
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:37:08] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-09 07:37:08] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 38 places, 64 transitions and 184 arcs took 0 ms.
Total runtime 2074 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Angiogenesis-PT-15
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA Angiogenesis-PT-15-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-15-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-15-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-15-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-15-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-15-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-15-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678347583987

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
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lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: LAUNCH task # 79 (type EXCL) for 18 Angiogenesis-PT-15-CTLFireability-06
lola: time limit : 102 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 82 (type FNDP) for 49 Angiogenesis-PT-15-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type EQUN) for 49 Angiogenesis-PT-15-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
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lola: LAUNCH task # 86 (type SRCH) for 49 Angiogenesis-PT-15-CTLFireability-13
lola: time limit : 32000000 sec
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 82 (type FNDP) for Angiogenesis-PT-15-CTLFireability-13
lola: result : true
lola: fired transitions : 41
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 83 (type EQUN) for Angiogenesis-PT-15-CTLFireability-13 (obsolete)
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: try reading problem file /home/mcc/execution/373/CTLFireability-83.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.

lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 83 (type EQUN) for Angiogenesis-PT-15-CTLFireability-13
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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Angiogenesis-PT-15-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
Angiogenesis-PT-15-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-15: DISJ 0 5 0 0 5 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 LTL EXCL 5/171 15/32 Angiogenesis-PT-15-CTLFireability-06 2198412 m, 439682 m/sec, 3647663 t fired, .

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Angiogenesis-PT-15-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
Angiogenesis-PT-15-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-15: DISJ 0 5 0 0 5 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 LTL EXCL 10/171 28/32 Angiogenesis-PT-15-CTLFireability-06 4177118 m, 395741 m/sec, 7197028 t fired, .

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Angiogenesis-PT-15-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
Angiogenesis-PT-15-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0
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lola: result : false
lola: markings : 65011
lola: fired transitions : 164816
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 1 0 5 0 0 2
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/358 5/32 Angiogenesis-PT-15-CTLFireability-10 1097513 m, 219502 m/sec, 4243601 t fired, .

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Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 1 0 5 0 0 2
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/358 10/32 Angiogenesis-PT-15-CTLFireability-10 2175481 m, 215593 m/sec, 8449319 t fired, .

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Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 1 0 5 0 0 2
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/358 14/32 Angiogenesis-PT-15-CTLFireability-10 3258455 m, 216594 m/sec, 12656542 t fired, .

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Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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Angiogenesis-PT-15-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 1 0 5 0 0 2
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/358 19/32 Angiogenesis-PT-15-CTLFireability-10 4310681 m, 210445 m/sec, 16843515 t fired, .

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Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 0 0 5 0 1 2
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0

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lola: result : true
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-15-CTLFireability-01: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-04: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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Angiogenesis-PT-15-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 0 0 5 0 1 2
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 3/1161 7/32 Angiogenesis-PT-15-CTLFireability-00 1532966 m, 306593 m/sec, 5692413 t fired, .

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Angiogenesis-PT-15-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 8/1161 16/32 Angiogenesis-PT-15-CTLFireability-00 3663572 m, 426121 m/sec, 13587614 t fired, .

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Angiogenesis-PT-15-CTLFireability-01: CTL true CTL model checker
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Angiogenesis-PT-15-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 0 0 5 0 1 2
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 13/1161 25/32 Angiogenesis-PT-15-CTLFireability-00 5729269 m, 413139 m/sec, 21273531 t fired, .

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Angiogenesis-PT-15-CTLFireability-01: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-04: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 0 0 5 0 1 2
Angiogenesis-PT-15-CTLFireability-14: SP ACTL 0 1 0 0 1 0 0 0

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Angiogenesis-PT-15-CTLFireability-01: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-04: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-14: SP ACTL false LTL model checker
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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Angiogenesis-PT-15-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 0 0 5 0 1 2

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/3465 5/32 Angiogenesis-PT-15-CTLFireability-07 988491 m, 197698 m/sec, 7208546 t fired, .

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Angiogenesis-PT-15-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-14: SP ACTL false LTL model checker
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 0 0 5 0 1 2

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/3465 16/32 Angiogenesis-PT-15-CTLFireability-07 3616464 m, 525594 m/sec, 15282788 t fired, .

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Angiogenesis-PT-15-CTLFireability-01: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-04: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-14: SP ACTL false LTL model checker
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-06: SP ECTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-15-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-15-CTLFireability-10: DISJ 0 0 0 0 5 0 1 2

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/3465 27/32 Angiogenesis-PT-15-CTLFireability-07 6310243 m, 538755 m/sec, 22581247 t fired, .

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Angiogenesis-PT-15-CTLFireability-04: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-14: SP ACTL false LTL model checker
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker

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Angiogenesis-PT-15-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-15-CTLFireability-00: CTL unknown AGGR
Angiogenesis-PT-15-CTLFireability-01: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-02: CTL unknown AGGR
Angiogenesis-PT-15-CTLFireability-03: CTL unknown AGGR
Angiogenesis-PT-15-CTLFireability-04: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-15-CTLFireability-06: SP ECTL unknown AGGR
Angiogenesis-PT-15-CTLFireability-07: CTL unknown AGGR
Angiogenesis-PT-15-CTLFireability-09: CTL unknown AGGR
Angiogenesis-PT-15-CTLFireability-10: DISJ unknown DISJ
Angiogenesis-PT-15-CTLFireability-11: CONJ false CTL model checker
Angiogenesis-PT-15-CTLFireability-13: CONJ false findpath
Angiogenesis-PT-15-CTLFireability-14: SP ACTL false LTL model checker
Angiogenesis-PT-15-CTLFireability-15: DISJ true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Angiogenesis-PT-15"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Angiogenesis-PT-15, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595300338"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Angiogenesis-PT-15.tgz
mv Angiogenesis-PT-15 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;