Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595300314.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Angiogenesis-PT-01, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595300314
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 540K
-rw-r--r-- 1 mcc users 7.3K Feb 26 14:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K Feb 26 14:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Feb 26 14:53 CTLFireability.txt
-rw-r--r-- 1 mcc users 38K Feb 26 14:53 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Feb 25 15:31 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:31 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:31 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:31 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Feb 26 14:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 175K Feb 26 14:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Feb 26 14:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Feb 26 14:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 34K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-00
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-01
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-02
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-03
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-04
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-05
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-06
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-07
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-08
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-09
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-10
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-11
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-12
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-13
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-14
FORMULA_NAME Angiogenesis-PT-01-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678347006041

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Angiogenesis-PT-01
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 07:30:08] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 07:30:08] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 07:30:08] [INFO ] Load time of PNML (sax parser for PT used): 40 ms
[2023-03-09 07:30:08] [INFO ] Transformed 39 places.
[2023-03-09 07:30:08] [INFO ] Transformed 64 transitions.
[2023-03-09 07:30:08] [INFO ] Found NUPN structural information;
[2023-03-09 07:30:08] [INFO ] Parsed PT model containing 39 places and 64 transitions and 185 arcs in 116 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 1 formulas.
FORMULA Angiogenesis-PT-01-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 33 out of 39 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 64/64 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 38 transition count 64
Applied a total of 1 rules in 20 ms. Remains 38 /39 variables (removed 1) and now considering 64/64 (removed 0) transitions.
// Phase 1: matrix 64 rows 38 cols
[2023-03-09 07:30:08] [INFO ] Computed 7 place invariants in 5 ms
[2023-03-09 07:30:08] [INFO ] Implicit Places using invariants in 274 ms returned [4]
Discarding 1 places :
Implicit Place search using SMT only with invariants took 325 ms to find 1 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 37/39 places, 64/64 transitions.
Applied a total of 0 rules in 3 ms. Remains 37 /37 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 350 ms. Remains : 37/39 places, 64/64 transitions.
Support contains 33 out of 37 places after structural reductions.
[2023-03-09 07:30:09] [INFO ] Flatten gal took : 23 ms
[2023-03-09 07:30:09] [INFO ] Flatten gal took : 10 ms
[2023-03-09 07:30:09] [INFO ] Input system was already deterministic with 64 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 454 ms. (steps per millisecond=22 ) properties (out of 47) seen :29
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 18) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 17) seen :0
Running SMT prover for 17 properties.
// Phase 1: matrix 64 rows 37 cols
[2023-03-09 07:30:09] [INFO ] Computed 6 place invariants in 1 ms
[2023-03-09 07:30:10] [INFO ] [Real]Absence check using 6 positive place invariants in 2 ms returned sat
[2023-03-09 07:30:10] [INFO ] After 105ms SMT Verify possible using state equation in real domain returned unsat :11 sat :1 real:5
[2023-03-09 07:30:10] [INFO ] Deduced a trap composed of 23 places in 74 ms of which 5 ms to minimize.
[2023-03-09 07:30:10] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 1 trap constraints in 78 ms
[2023-03-09 07:30:10] [INFO ] After 186ms SMT Verify possible using trap constraints in real domain returned unsat :12 sat :0 real:5
[2023-03-09 07:30:10] [INFO ] After 341ms SMT Verify possible using all constraints in real domain returned unsat :12 sat :0 real:5
[2023-03-09 07:30:10] [INFO ] [Nat]Absence check using 6 positive place invariants in 1 ms returned sat
[2023-03-09 07:30:10] [INFO ] After 42ms SMT Verify possible using state equation in natural domain returned unsat :12 sat :5
[2023-03-09 07:30:10] [INFO ] Deduced a trap composed of 23 places in 28 ms of which 0 ms to minimize.
[2023-03-09 07:30:10] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 1 trap constraints in 31 ms
[2023-03-09 07:30:10] [INFO ] After 92ms SMT Verify possible using trap constraints in natural domain returned unsat :17 sat :0
[2023-03-09 07:30:10] [INFO ] After 140ms SMT Verify possible using all constraints in natural domain returned unsat :17 sat :0
Fused 17 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 17 atomic propositions for a total of 15 simplifications.
FORMULA Angiogenesis-PT-01-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 07:30:10] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 7 ms
[2023-03-09 07:30:10] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA Angiogenesis-PT-01-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Angiogenesis-PT-01-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 64 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Graph (trivial) has 11 edges and 37 vertex of which 2 / 37 are part of one of the 1 SCC in 1 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Applied a total of 1 rules in 15 ms. Remains 36 /37 variables (removed 1) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 36/37 places, 63/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 37 /37 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 37/37 places, 64/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Graph (trivial) has 8 edges and 37 vertex of which 2 / 37 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Partial Post-agglomeration rule applied 3 times.
Drop transitions removed 3 transitions
Iterating global reduction 0 with 3 rules applied. Total rules applied 4 place count 36 transition count 63
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 5 place count 36 transition count 62
Applied a total of 5 rules in 7 ms. Remains 36 /37 variables (removed 1) and now considering 62/64 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 36/37 places, 62/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 37 /37 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 37/37 places, 64/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 37 /37 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 37/37 places, 64/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Graph (trivial) has 11 edges and 37 vertex of which 2 / 37 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Applied a total of 1 rules in 2 ms. Remains 36 /37 variables (removed 1) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 36/37 places, 63/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 37 /37 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 37/37 places, 64/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 37 /37 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 37/37 places, 64/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Partial Post-agglomeration rule applied 4 times.
Drop transitions removed 4 transitions
Iterating global reduction 0 with 4 rules applied. Total rules applied 4 place count 37 transition count 64
Applied a total of 4 rules in 4 ms. Remains 37 /37 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 37/37 places, 64/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Graph (trivial) has 8 edges and 37 vertex of which 2 / 37 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Partial Post-agglomeration rule applied 6 times.
Drop transitions removed 6 transitions
Iterating global reduction 0 with 6 rules applied. Total rules applied 7 place count 36 transition count 63
Applied a total of 7 rules in 4 ms. Remains 36 /37 variables (removed 1) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 36/37 places, 63/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 37 /37 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 37/37 places, 64/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 37 /37 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 37/37 places, 64/64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:30:10] [INFO ] Input system was already deterministic with 64 transitions.
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:30:10] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-09 07:30:10] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 37 places, 64 transitions and 181 arcs took 0 ms.
Total runtime 2319 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Angiogenesis-PT-01
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/380
CTLFireability

FORMULA Angiogenesis-PT-01-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-01-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678347011224

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/380/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/380/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/380/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 70 (type EXCL) for 26 Angiogenesis-PT-01-CTLFireability-04
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 68 (type FNDP) for 26 Angiogenesis-PT-01-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type EQUN) for 26 Angiogenesis-PT-01-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SRCH) for 26 Angiogenesis-PT-01-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 71 (type SRCH) for Angiogenesis-PT-01-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 73 (type FNDP) for 3 Angiogenesis-PT-01-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 68 (type FNDP) for Angiogenesis-PT-01-CTLFireability-04
lola: result : true
lola: fired transitions : 18
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 69 (type EQUN) for Angiogenesis-PT-01-CTLFireability-04 (obsolete)
lola: CANCELED task # 70 (type EXCL) for Angiogenesis-PT-01-CTLFireability-04 (obsolete)
lola: LAUNCH task # 75 (type EXCL) for 3 Angiogenesis-PT-01-CTLFireability-02
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 74 (type EQUN) for 3 Angiogenesis-PT-01-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 76 (type SRCH) for 3 Angiogenesis-PT-01-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: FINISHED task # 76 (type SRCH) for Angiogenesis-PT-01-CTLFireability-02
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 77 (type FNDP) for 47 Angiogenesis-PT-01-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 75 (type EXCL) for Angiogenesis-PT-01-CTLFireability-02
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 73 (type FNDP) for Angiogenesis-PT-01-CTLFireability-02 (obsolete)
lola: CANCELED task # 74 (type EQUN) for Angiogenesis-PT-01-CTLFireability-02 (obsolete)
lola: LAUNCH task # 30 (type EXCL) for 29 Angiogenesis-PT-01-CTLFireability-05
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 79 (type EQUN) for 47 Angiogenesis-PT-01-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SRCH) for 47 Angiogenesis-PT-01-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 74 (type EQUN) for Angiogenesis-PT-01-CTLFireability-02
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 73 (type FNDP) for Angiogenesis-PT-01-CTLFireability-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
sara: try reading problem file /home/mcc/execution/380/CTLFireability-69.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: FINISHED task # 81 (type SRCH) for Angiogenesis-PT-01-CTLFireability-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 77 (type FNDP) for Angiogenesis-PT-01-CTLFireability-13
lola: result : true
lola: fired transitions : 20
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: CANCELED task # 79 (type EQUN) for Angiogenesis-PT-01-CTLFireability-13 (obsolete)
lola: FINISHED task # 30 (type EXCL) for Angiogenesis-PT-01-CTLFireability-05
lola: result : false
lola: markings : 44
lola: fired transitions : 81
lola: time used : 0.000000
lola: memory pages used : 1

lola: LAUNCH task # 66 (type EXCL) for 57 Angiogenesis-PT-01-CTLFireability-15
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 66 (type EXCL) for Angiogenesis-PT-01-CTLFireability-15
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 54 Angiogenesis-PT-01-CTLFireability-14
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for Angiogenesis-PT-01-CTLFireability-14
lola: result : true
lola: markings : 44
lola: fired transitions : 89
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 Angiogenesis-PT-01-CTLFireability-10
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for Angiogenesis-PT-01-CTLFireability-10
lola: result : true
lola: markings : 6
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 Angiogenesis-PT-01-CTLFireability-09
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 69 (type EQUN) for Angiogenesis-PT-01-CTLFireability-04
lola: result : true
lola: FINISHED task # 39 (type EXCL) for Angiogenesis-PT-01-CTLFireability-09
lola: result : false
lola: markings : 1
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/380/CTLFireability-79.sara.
lola: LAUNCH task # 6 (type EXCL) for 3 Angiogenesis-PT-01-CTLFireability-02
lola: time limit : 720 sec
lola: memory limit: 32 pages
lola: FINISHED task # 6 (type EXCL) for Angiogenesis-PT-01-CTLFireability-02
lola: result : true
lola: markings : 37
lola: fired transitions : 95
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 Angiogenesis-PT-01-CTLFireability-00
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for Angiogenesis-PT-01-CTLFireability-00
lola: result : false
lola: markings : 13
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 Angiogenesis-PT-01-CTLFireability-08
lola: time limit : 1200 sec
lola: memory limit: 32 pages
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 36 (type EXCL) for Angiogenesis-PT-01-CTLFireability-08
lola: result : true
lola: markings : 12
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 Angiogenesis-PT-01-CTLFireability-12
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for Angiogenesis-PT-01-CTLFireability-12
lola: result : true
lola: markings : 110
lola: fired transitions : 288
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 Angiogenesis-PT-01-CTLFireability-07
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for Angiogenesis-PT-01-CTLFireability-07

lola: result : true
lola: markings : 29
lola: fired transitions : 81
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-01-CTLFireability-00: AGEF false tscc_search
Angiogenesis-PT-01-CTLFireability-02: DISJ true CTL model checker
Angiogenesis-PT-01-CTLFireability-04: EF true findpath
Angiogenesis-PT-01-CTLFireability-05: CTL false CTL model checker
Angiogenesis-PT-01-CTLFireability-07: CTL true CTL model checker
Angiogenesis-PT-01-CTLFireability-08: EFEG true state space /EFEG
Angiogenesis-PT-01-CTLFireability-09: CTL false CTL model checker
Angiogenesis-PT-01-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-01-CTLFireability-12: AGEF true tscc_search
Angiogenesis-PT-01-CTLFireability-13: DISJ true findpath
Angiogenesis-PT-01-CTLFireability-14: CTL true CTL model checker
Angiogenesis-PT-01-CTLFireability-15: CONJ false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Angiogenesis-PT-01"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Angiogenesis-PT-01, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595300314"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Angiogenesis-PT-01.tgz
mv Angiogenesis-PT-01 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;