About the Execution of LoLa+red for AirplaneLD-PT-0100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3379.340 | 287967.00 | 298137.00 | 40.50 | ??TTFF??F?TT?FTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595200266.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is AirplaneLD-PT-0100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595200266
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.9M
-rw-r--r-- 1 mcc users 37K Feb 26 11:15 CTLCardinality.txt
-rw-r--r-- 1 mcc users 153K Feb 26 11:15 CTLCardinality.xml
-rw-r--r-- 1 mcc users 55K Feb 26 11:12 CTLFireability.txt
-rw-r--r-- 1 mcc users 325K Feb 26 11:12 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 39K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 17K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 83K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 200K Feb 26 11:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 806K Feb 26 11:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 89K Feb 26 11:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 542K Feb 26 11:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 6.1K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 13K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 433K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-00
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-01
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-02
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-03
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-04
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-05
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-06
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-07
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-08
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-09
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-10
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-11
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-12
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-13
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-14
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678345223813
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-PT-0100
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 07:00:26] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 07:00:26] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 07:00:27] [INFO ] Load time of PNML (sax parser for PT used): 136 ms
[2023-03-09 07:00:27] [INFO ] Transformed 719 places.
[2023-03-09 07:00:27] [INFO ] Transformed 808 transitions.
[2023-03-09 07:00:27] [INFO ] Parsed PT model containing 719 places and 808 transitions and 3078 arcs in 258 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 22 ms.
Reduce places removed 302 places and 0 transitions.
Support contains 414 out of 417 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 417/417 places, 808/808 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 414 transition count 808
Applied a total of 3 rules in 17 ms. Remains 414 /417 variables (removed 3) and now considering 808/808 (removed 0) transitions.
// Phase 1: matrix 808 rows 414 cols
[2023-03-09 07:00:27] [INFO ] Computed 1 place invariants in 42 ms
[2023-03-09 07:00:27] [INFO ] Implicit Places using invariants in 551 ms returned []
[2023-03-09 07:00:27] [INFO ] Invariant cache hit.
[2023-03-09 07:00:28] [INFO ] Implicit Places using invariants and state equation in 536 ms returned []
Implicit Place search using SMT with State Equation took 1130 ms to find 0 implicit places.
[2023-03-09 07:00:28] [INFO ] Invariant cache hit.
[2023-03-09 07:00:29] [INFO ] Dead Transitions using invariants and state equation in 981 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 414/417 places, 808/808 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2139 ms. Remains : 414/417 places, 808/808 transitions.
Support contains 414 out of 414 places after structural reductions.
[2023-03-09 07:00:29] [INFO ] Flatten gal took : 92 ms
[2023-03-09 07:00:30] [INFO ] Flatten gal took : 79 ms
[2023-03-09 07:00:30] [INFO ] Input system was already deterministic with 808 transitions.
Incomplete random walk after 10000 steps, including 1262 resets, run finished after 563 ms. (steps per millisecond=17 ) properties (out of 50) seen :40
Incomplete Best-First random walk after 10001 steps, including 11 resets, run finished after 8 ms. (steps per millisecond=1250 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 10 resets, run finished after 83 ms. (steps per millisecond=120 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 6 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 13 resets, run finished after 6 ms. (steps per millisecond=1666 ) properties (out of 10) seen :1
Incomplete Best-First random walk after 10001 steps, including 7 resets, run finished after 5 ms. (steps per millisecond=2000 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 13 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 13 resets, run finished after 6 ms. (steps per millisecond=1666 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 13 resets, run finished after 6 ms. (steps per millisecond=1666 ) properties (out of 9) seen :1
Incomplete Best-First random walk after 10001 steps, including 11 resets, run finished after 5 ms. (steps per millisecond=2000 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 11 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 8) seen :0
Running SMT prover for 8 properties.
[2023-03-09 07:00:31] [INFO ] Invariant cache hit.
[2023-03-09 07:00:31] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-09 07:00:32] [INFO ] After 535ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:7
[2023-03-09 07:00:32] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 07:00:33] [INFO ] After 1025ms SMT Verify possible using state equation in natural domain returned unsat :5 sat :3
[2023-03-09 07:00:33] [INFO ] After 1416ms SMT Verify possible using trap constraints in natural domain returned unsat :5 sat :3
Attempting to minimize the solution found.
Minimization took 285 ms.
[2023-03-09 07:00:34] [INFO ] After 2069ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :3
Fused 8 Parikh solutions to 3 different solutions.
Finished Parikh walk after 9 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=9 )
Parikh walk visited 3 properties in 6 ms.
Successfully simplified 5 atomic propositions for a total of 16 simplifications.
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 56 ms
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 43 ms
[2023-03-09 07:00:34] [INFO ] Input system was already deterministic with 808 transitions.
Computed a total of 414 stabilizing places and 808 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 414 transition count 808
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 2 formulas.
FORMULA AirplaneLD-PT-0100-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA AirplaneLD-PT-0100-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Discarding 295 places :
Symmetric choice reduction at 0 with 295 rule applications. Total rules 295 place count 119 transition count 513
Iterating global reduction 0 with 295 rules applied. Total rules applied 590 place count 119 transition count 513
Ensure Unique test removed 295 transitions
Reduce isomorphic transitions removed 295 transitions.
Iterating post reduction 0 with 295 rules applied. Total rules applied 885 place count 119 transition count 218
Applied a total of 885 rules in 11 ms. Remains 119 /414 variables (removed 295) and now considering 218/808 (removed 590) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 119/414 places, 218/808 transitions.
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 11 ms
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 15 ms
[2023-03-09 07:00:34] [INFO ] Input system was already deterministic with 218 transitions.
Starting structural reductions in LTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Discarding 345 places :
Symmetric choice reduction at 0 with 345 rule applications. Total rules 345 place count 69 transition count 463
Iterating global reduction 0 with 345 rules applied. Total rules applied 690 place count 69 transition count 463
Ensure Unique test removed 345 transitions
Reduce isomorphic transitions removed 345 transitions.
Iterating post reduction 0 with 345 rules applied. Total rules applied 1035 place count 69 transition count 118
Applied a total of 1035 rules in 7 ms. Remains 69 /414 variables (removed 345) and now considering 118/808 (removed 690) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 69/414 places, 118/808 transitions.
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 17 ms
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:00:34] [INFO ] Input system was already deterministic with 118 transitions.
Starting structural reductions in LTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Discarding 196 places :
Symmetric choice reduction at 0 with 196 rule applications. Total rules 196 place count 218 transition count 612
Iterating global reduction 0 with 196 rules applied. Total rules applied 392 place count 218 transition count 612
Ensure Unique test removed 196 transitions
Reduce isomorphic transitions removed 196 transitions.
Iterating post reduction 0 with 196 rules applied. Total rules applied 588 place count 218 transition count 416
Applied a total of 588 rules in 6 ms. Remains 218 /414 variables (removed 196) and now considering 416/808 (removed 392) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 218/414 places, 416/808 transitions.
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 12 ms
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 14 ms
[2023-03-09 07:00:34] [INFO ] Input system was already deterministic with 416 transitions.
Starting structural reductions in LTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Discarding 298 places :
Symmetric choice reduction at 0 with 298 rule applications. Total rules 298 place count 116 transition count 510
Iterating global reduction 0 with 298 rules applied. Total rules applied 596 place count 116 transition count 510
Ensure Unique test removed 298 transitions
Reduce isomorphic transitions removed 298 transitions.
Iterating post reduction 0 with 298 rules applied. Total rules applied 894 place count 116 transition count 212
Applied a total of 894 rules in 6 ms. Remains 116 /414 variables (removed 298) and now considering 212/808 (removed 596) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 116/414 places, 212/808 transitions.
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:00:34] [INFO ] Input system was already deterministic with 212 transitions.
Starting structural reductions in LTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Discarding 200 places :
Symmetric choice reduction at 0 with 200 rule applications. Total rules 200 place count 214 transition count 608
Iterating global reduction 0 with 200 rules applied. Total rules applied 400 place count 214 transition count 608
Ensure Unique test removed 200 transitions
Reduce isomorphic transitions removed 200 transitions.
Iterating post reduction 0 with 200 rules applied. Total rules applied 600 place count 214 transition count 408
Applied a total of 600 rules in 5 ms. Remains 214 /414 variables (removed 200) and now considering 408/808 (removed 400) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 214/414 places, 408/808 transitions.
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 10 ms
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 29 ms
[2023-03-09 07:00:34] [INFO ] Input system was already deterministic with 408 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Graph (complete) has 562 edges and 414 vertex of which 211 are kept as prefixes of interest. Removing 203 places using SCC suffix rule.3 ms
Discarding 203 places :
Also discarding 300 output transitions
Drop transitions removed 300 transitions
Ensure Unique test removed 99 transitions
Reduce isomorphic transitions removed 99 transitions.
Iterating post reduction 0 with 99 rules applied. Total rules applied 100 place count 211 transition count 409
Applied a total of 100 rules in 28 ms. Remains 211 /414 variables (removed 203) and now considering 409/808 (removed 399) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 211/414 places, 409/808 transitions.
[2023-03-09 07:00:34] [INFO ] Flatten gal took : 11 ms
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 14 ms
[2023-03-09 07:00:35] [INFO ] Input system was already deterministic with 409 transitions.
Starting structural reductions in LTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Discarding 294 places :
Symmetric choice reduction at 0 with 294 rule applications. Total rules 294 place count 120 transition count 514
Iterating global reduction 0 with 294 rules applied. Total rules applied 588 place count 120 transition count 514
Ensure Unique test removed 294 transitions
Reduce isomorphic transitions removed 294 transitions.
Iterating post reduction 0 with 294 rules applied. Total rules applied 882 place count 120 transition count 220
Applied a total of 882 rules in 5 ms. Remains 120 /414 variables (removed 294) and now considering 220/808 (removed 588) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 120/414 places, 220/808 transitions.
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 7 ms
[2023-03-09 07:00:35] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in LTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Discarding 394 places :
Symmetric choice reduction at 0 with 394 rule applications. Total rules 394 place count 20 transition count 414
Iterating global reduction 0 with 394 rules applied. Total rules applied 788 place count 20 transition count 414
Ensure Unique test removed 394 transitions
Reduce isomorphic transitions removed 394 transitions.
Iterating post reduction 0 with 394 rules applied. Total rules applied 1182 place count 20 transition count 20
Applied a total of 1182 rules in 5 ms. Remains 20 /414 variables (removed 394) and now considering 20/808 (removed 788) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 20/414 places, 20/808 transitions.
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:00:35] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Discarding 393 places :
Symmetric choice reduction at 0 with 393 rule applications. Total rules 393 place count 21 transition count 415
Iterating global reduction 0 with 393 rules applied. Total rules applied 786 place count 21 transition count 415
Ensure Unique test removed 393 transitions
Reduce isomorphic transitions removed 393 transitions.
Iterating post reduction 0 with 393 rules applied. Total rules applied 1179 place count 21 transition count 22
Applied a total of 1179 rules in 5 ms. Remains 21 /414 variables (removed 393) and now considering 22/808 (removed 786) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 21/414 places, 22/808 transitions.
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:00:35] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Graph (complete) has 562 edges and 414 vertex of which 210 are kept as prefixes of interest. Removing 204 places using SCC suffix rule.1 ms
Discarding 204 places :
Also discarding 400 output transitions
Drop transitions removed 400 transitions
Discarding 198 places :
Symmetric choice reduction at 0 with 198 rule applications. Total rules 199 place count 12 transition count 210
Iterating global reduction 0 with 198 rules applied. Total rules applied 397 place count 12 transition count 210
Ensure Unique test removed 198 transitions
Reduce isomorphic transitions removed 198 transitions.
Iterating post reduction 0 with 198 rules applied. Total rules applied 595 place count 12 transition count 12
Applied a total of 595 rules in 6 ms. Remains 12 /414 variables (removed 402) and now considering 12/808 (removed 796) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 12/414 places, 12/808 transitions.
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:00:35] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Discarding 391 places :
Symmetric choice reduction at 0 with 391 rule applications. Total rules 391 place count 23 transition count 417
Iterating global reduction 0 with 391 rules applied. Total rules applied 782 place count 23 transition count 417
Ensure Unique test removed 391 transitions
Reduce isomorphic transitions removed 391 transitions.
Iterating post reduction 0 with 391 rules applied. Total rules applied 1173 place count 23 transition count 26
Applied a total of 1173 rules in 8 ms. Remains 23 /414 variables (removed 391) and now considering 26/808 (removed 782) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 23/414 places, 26/808 transitions.
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 14 ms
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:00:35] [INFO ] Input system was already deterministic with 26 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Graph (complete) has 562 edges and 414 vertex of which 1 are kept as prefixes of interest. Removing 413 places using SCC suffix rule.1 ms
Discarding 413 places :
Also discarding 708 output transitions
Drop transitions removed 708 transitions
Ensure Unique test removed 99 transitions
Reduce isomorphic transitions removed 99 transitions.
Iterating post reduction 0 with 99 rules applied. Total rules applied 100 place count 1 transition count 1
Applied a total of 100 rules in 2 ms. Remains 1 /414 variables (removed 413) and now considering 1/808 (removed 807) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 1/414 places, 1/808 transitions.
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:00:35] [INFO ] Input system was already deterministic with 1 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Graph (complete) has 562 edges and 414 vertex of which 212 are kept as prefixes of interest. Removing 202 places using SCC suffix rule.1 ms
Discarding 202 places :
Also discarding 200 output transitions
Drop transitions removed 200 transitions
Ensure Unique test removed 198 transitions
Reduce isomorphic transitions removed 198 transitions.
Iterating post reduction 0 with 198 rules applied. Total rules applied 199 place count 212 transition count 410
Discarding 197 places :
Symmetric choice reduction at 1 with 197 rule applications. Total rules 396 place count 15 transition count 213
Iterating global reduction 1 with 197 rules applied. Total rules applied 593 place count 15 transition count 213
Ensure Unique test removed 197 transitions
Reduce isomorphic transitions removed 197 transitions.
Iterating post reduction 1 with 197 rules applied. Total rules applied 790 place count 15 transition count 16
Applied a total of 790 rules in 9 ms. Remains 15 /414 variables (removed 399) and now considering 16/808 (removed 792) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 15/414 places, 16/808 transitions.
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:00:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 414/414 places, 808/808 transitions.
Discarding 388 places :
Symmetric choice reduction at 0 with 388 rule applications. Total rules 388 place count 26 transition count 420
Iterating global reduction 0 with 388 rules applied. Total rules applied 776 place count 26 transition count 420
Ensure Unique test removed 388 transitions
Reduce isomorphic transitions removed 388 transitions.
Iterating post reduction 0 with 388 rules applied. Total rules applied 1164 place count 26 transition count 32
Applied a total of 1164 rules in 4 ms. Remains 26 /414 variables (removed 388) and now considering 32/808 (removed 776) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 26/414 places, 32/808 transitions.
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:00:35] [INFO ] Input system was already deterministic with 32 transitions.
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 30 ms
[2023-03-09 07:00:35] [INFO ] Flatten gal took : 30 ms
[2023-03-09 07:00:35] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 12 ms.
[2023-03-09 07:00:35] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 414 places, 808 transitions and 1770 arcs took 2 ms.
Total runtime 8487 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT AirplaneLD-PT-0100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/377
CTLFireability
FORMULA AirplaneLD-PT-0100-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0100-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0100-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0100-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0100-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0100-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0100-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0100-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678345511780
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/377/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/377/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/377/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:203
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: LAUNCH task # 66 (type SKEL/SRCH) for 16 AirplaneLD-PT-0100-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 66 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-04
lola: result : true
lola: markings : 7
lola: fired transitions : 6
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 67 (type SKEL/SRCH) for 6 AirplaneLD-PT-0100-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 67 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-02
lola: result : true
lola: markings : 8534
lola: fired transitions : 41486
lola: time used : 0.000000
lola: memory pages used : 1
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 68 (type SKEL/SRCH) for 33 AirplaneLD-PT-0100-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 68 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-09
lola: result : false
lola: markings : 8
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 69 (type SKEL/SRCH) for 45 AirplaneLD-PT-0100-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 69 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-13
lola: result : false
lola: markings : 45
lola: fired transitions : 44
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 1 (type EXCL) for 0 AirplaneLD-PT-0100-CTLFireability-00
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 70 (type SKEL/SRCH) for 39 AirplaneLD-PT-0100-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: FINISHED task # 70 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-11
lola: result : true
lola: markings : 8
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 71 (type SKEL/SRCH) for 16 AirplaneLD-PT-0100-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 71 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-04
lola: result : false
lola: markings : 6
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 74 (type SKEL/SRCH) for 51 AirplaneLD-PT-0100-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type SKEL/SRCH) for 51 AirplaneLD-PT-0100-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 75 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-15
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 74 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-15
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 76 (type SKEL/SRCH) for 51 AirplaneLD-PT-0100-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 76 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-15
lola: result : false
lola: markings : 12
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 77 (type SKEL/SRCH) for 51 AirplaneLD-PT-0100-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 77 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-15
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 78 (type SKEL/SRCH) for 48 AirplaneLD-PT-0100-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 78 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-14
lola: result : true
lola: markings : 527
lola: fired transitions : 4752
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 3 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 4/239 5/32 AirplaneLD-PT-0100-CTLFireability-00 733231 m, 146646 m/sec, 1324513 t fired, .
Time elapsed: 10 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 3 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 9/239 11/32 AirplaneLD-PT-0100-CTLFireability-00 1585166 m, 170387 m/sec, 2846010 t fired, .
Time elapsed: 15 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 3 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 14/239 16/32 AirplaneLD-PT-0100-CTLFireability-00 2423827 m, 167732 m/sec, 4374565 t fired, .
Time elapsed: 20 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 3 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 19/239 21/32 AirplaneLD-PT-0100-CTLFireability-00 3267316 m, 168697 m/sec, 5919415 t fired, .
Time elapsed: 25 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 3 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 24/239 27/32 AirplaneLD-PT-0100-CTLFireability-00 4109375 m, 168411 m/sec, 7462126 t fired, .
Time elapsed: 30 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 3 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 29/239 32/32 AirplaneLD-PT-0100-CTLFireability-00 4944578 m, 167040 m/sec, 8995537 t fired, .
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 1 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 3 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 72 (type EXCL) for 51 AirplaneLD-PT-0100-CTLFireability-15
lola: time limit : 254 sec
lola: memory limit: 32 pages
lola: FINISHED task # 72 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-15
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 64 (type EXCL) for 51 AirplaneLD-PT-0100-CTLFireability-15
lola: time limit : 273 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-15
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 AirplaneLD-PT-0100-CTLFireability-10
lola: time limit : 296 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-10
lola: result : true
lola: markings : 10
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 AirplaneLD-PT-0100-CTLFireability-09
lola: time limit : 323 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/323 4/32 AirplaneLD-PT-0100-CTLFireability-09 523201 m, 104640 m/sec, 1629730 t fired, .
Time elapsed: 46 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/323 7/32 AirplaneLD-PT-0100-CTLFireability-09 1032955 m, 101950 m/sec, 3260561 t fired, .
Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/323 10/32 AirplaneLD-PT-0100-CTLFireability-09 1432416 m, 79892 m/sec, 4894215 t fired, .
Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 20/323 13/32 AirplaneLD-PT-0100-CTLFireability-09 1953629 m, 104242 m/sec, 6522300 t fired, .
Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 25/323 16/32 AirplaneLD-PT-0100-CTLFireability-09 2415796 m, 92433 m/sec, 8191154 t fired, .
Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 30/323 19/32 AirplaneLD-PT-0100-CTLFireability-09 2871383 m, 91117 m/sec, 9808104 t fired, .
Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 35/323 22/32 AirplaneLD-PT-0100-CTLFireability-09 3400415 m, 105806 m/sec, 11454539 t fired, .
Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 40/323 25/32 AirplaneLD-PT-0100-CTLFireability-09 3798585 m, 79634 m/sec, 13116856 t fired, .
Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 45/323 28/32 AirplaneLD-PT-0100-CTLFireability-09 4322837 m, 104850 m/sec, 14753878 t fired, .
Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 50/323 31/32 AirplaneLD-PT-0100-CTLFireability-09 4831630 m, 101758 m/sec, 16399592 t fired, .
Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 34 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 31 (type EXCL) for 30 AirplaneLD-PT-0100-CTLFireability-07
lola: time limit : 350 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/350 7/32 AirplaneLD-PT-0100-CTLFireability-07 1080220 m, 216044 m/sec, 1087547 t fired, .
Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/350 14/32 AirplaneLD-PT-0100-CTLFireability-07 2168074 m, 217570 m/sec, 2182745 t fired, .
Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/350 21/32 AirplaneLD-PT-0100-CTLFireability-07 3257698 m, 217924 m/sec, 3279722 t fired, .
Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/350 28/32 AirplaneLD-PT-0100-CTLFireability-07 4348309 m, 218122 m/sec, 4377685 t fired, .
Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 31 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-04: CONJ 0 3 0 0 3 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 25 (type EXCL) for 16 AirplaneLD-PT-0100-CTLFireability-04
lola: time limit : 386 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-04
lola: result : false
lola: markings : 6
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 AirplaneLD-PT-0100-CTLFireability-03
lola: time limit : 579 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-03
lola: result : true
lola: markings : 10
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 AirplaneLD-PT-0100-CTLFireability-01
lola: time limit : 695 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/695 4/32 AirplaneLD-PT-0100-CTLFireability-01 573235 m, 114647 m/sec, 582648 t fired, .
Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/695 8/32 AirplaneLD-PT-0100-CTLFireability-01 1146516 m, 114656 m/sec, 1165747 t fired, .
Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/695 11/32 AirplaneLD-PT-0100-CTLFireability-01 1720542 m, 114805 m/sec, 1749391 t fired, .
Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/695 15/32 AirplaneLD-PT-0100-CTLFireability-01 2297266 m, 115344 m/sec, 2335751 t fired, .
Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/695 19/32 AirplaneLD-PT-0100-CTLFireability-01 2881431 m, 116833 m/sec, 2929595 t fired, .
Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/695 23/32 AirplaneLD-PT-0100-CTLFireability-01 3461824 m, 116078 m/sec, 3519643 t fired, .
Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/695 26/32 AirplaneLD-PT-0100-CTLFireability-01 4038878 m, 115410 m/sec, 4106333 t fired, .
Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/695 30/32 AirplaneLD-PT-0100-CTLFireability-01 4607730 m, 113770 m/sec, 4684778 t fired, .
Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 4 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-11: EG 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-15: CONJ 0 1 0 0 6 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 40 (type EXCL) for 39 AirplaneLD-PT-0100-CTLFireability-11
lola: time limit : 858 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-11
lola: result : true
lola: markings : 7
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 51 AirplaneLD-PT-0100-CTLFireability-15
lola: time limit : 1144 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-15
lola: result : false
lola: markings : 10
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 AirplaneLD-PT-0100-CTLFireability-12
lola: time limit : 1717 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/1717 5/32 AirplaneLD-PT-0100-CTLFireability-12 651059 m, 130211 m/sec, 1606503 t fired, .
Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/1717 9/32 AirplaneLD-PT-0100-CTLFireability-12 1290705 m, 127929 m/sec, 3193174 t fired, .
Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/1717 13/32 AirplaneLD-PT-0100-CTLFireability-12 1936538 m, 129166 m/sec, 4794107 t fired, .
Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/1717 17/32 AirplaneLD-PT-0100-CTLFireability-12 2573772 m, 127446 m/sec, 6372701 t fired, .
Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/1717 21/32 AirplaneLD-PT-0100-CTLFireability-12 3195737 m, 124393 m/sec, 7915421 t fired, .
Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/1717 25/32 AirplaneLD-PT-0100-CTLFireability-12 3829111 m, 126674 m/sec, 9485032 t fired, .
Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 35/1717 29/32 AirplaneLD-PT-0100-CTLFireability-12 4470967 m, 128371 m/sec, 11071017 t fired, .
Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 43 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 28 (type EXCL) for 27 AirplaneLD-PT-0100-CTLFireability-06
lola: time limit : 3394 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/3394 3/32 AirplaneLD-PT-0100-CTLFireability-06 383678 m, 76735 m/sec, 1556266 t fired, .
Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/3394 5/32 AirplaneLD-PT-0100-CTLFireability-06 769367 m, 77137 m/sec, 3118101 t fired, .
Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/3394 8/32 AirplaneLD-PT-0100-CTLFireability-06 1146664 m, 75459 m/sec, 4656100 t fired, .
Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/3394 10/32 AirplaneLD-PT-0100-CTLFireability-06 1528395 m, 76346 m/sec, 6207807 t fired, .
Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/3394 13/32 AirplaneLD-PT-0100-CTLFireability-06 1910149 m, 76350 m/sec, 7757034 t fired, .
Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 30/3394 15/32 AirplaneLD-PT-0100-CTLFireability-06 2295932 m, 77156 m/sec, 9321334 t fired, .
Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 35/3394 17/32 AirplaneLD-PT-0100-CTLFireability-06 2682644 m, 77342 m/sec, 10887713 t fired, .
Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 40/3394 20/32 AirplaneLD-PT-0100-CTLFireability-06 3063936 m, 76258 m/sec, 12438769 t fired, .
Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 45/3394 22/32 AirplaneLD-PT-0100-CTLFireability-06 3449867 m, 77186 m/sec, 14002002 t fired, .
Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 50/3394 25/32 AirplaneLD-PT-0100-CTLFireability-06 3796669 m, 69360 m/sec, 15589486 t fired, .
Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 55/3394 27/32 AirplaneLD-PT-0100-CTLFireability-06 4142999 m, 69266 m/sec, 17128232 t fired, .
Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 60/3394 29/32 AirplaneLD-PT-0100-CTLFireability-06 4494339 m, 70268 m/sec, 18676628 t fired, .
Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 65/3394 31/32 AirplaneLD-PT-0100-CTLFireability-06 4881939 m, 77520 m/sec, 20244969 t fired, .
Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 28 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: Portfolio finished: no open tasks 14
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0100-CTLFireability-00: CTL unknown AGGR
AirplaneLD-PT-0100-CTLFireability-01: CTL unknown AGGR
AirplaneLD-PT-0100-CTLFireability-02: DISJ true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-03: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-04: CONJ false CTL model checker
AirplaneLD-PT-0100-CTLFireability-06: CTL unknown AGGR
AirplaneLD-PT-0100-CTLFireability-07: CTL unknown AGGR
AirplaneLD-PT-0100-CTLFireability-09: CTL unknown AGGR
AirplaneLD-PT-0100-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0100-CTLFireability-11: EG true state space / EG
AirplaneLD-PT-0100-CTLFireability-12: CTL unknown AGGR
AirplaneLD-PT-0100-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0100-CTLFireability-14: CTL true skeleton: CTL model checker
AirplaneLD-PT-0100-CTLFireability-15: CONJ false CTL model checker
Time elapsed: 276 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is AirplaneLD-PT-0100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595200266"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0100.tgz
mv AirplaneLD-PT-0100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;