About the Execution of LoLa+red for AirplaneLD-PT-0050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 816.556 | 47705.00 | 62017.00 | 47.50 | FFFTTFFFFFTTTFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595200258.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is AirplaneLD-PT-0050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595200258
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.9M
-rw-r--r-- 1 mcc users 44K Feb 26 11:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 196K Feb 26 11:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 38K Feb 26 11:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 248K Feb 26 11:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 23K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 83K Feb 26 11:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 358K Feb 26 11:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 68K Feb 26 11:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 433K Feb 26 11:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 219K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-00
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-01
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-02
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-03
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-04
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-05
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-06
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-07
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-08
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-09
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-10
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-11
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-12
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-13
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-14
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678345141211
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-PT-0050
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 06:59:03] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 06:59:03] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 06:59:03] [INFO ] Load time of PNML (sax parser for PT used): 84 ms
[2023-03-09 06:59:03] [INFO ] Transformed 369 places.
[2023-03-09 06:59:03] [INFO ] Transformed 408 transitions.
[2023-03-09 06:59:03] [INFO ] Parsed PT model containing 369 places and 408 transitions and 1553 arcs in 183 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 19 ms.
Reduce places removed 152 places and 0 transitions.
Support contains 214 out of 217 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 217/217 places, 408/408 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 214 transition count 408
Applied a total of 3 rules in 18 ms. Remains 214 /217 variables (removed 3) and now considering 408/408 (removed 0) transitions.
// Phase 1: matrix 408 rows 214 cols
[2023-03-09 06:59:04] [INFO ] Computed 1 place invariants in 16 ms
[2023-03-09 06:59:04] [INFO ] Implicit Places using invariants in 258 ms returned []
[2023-03-09 06:59:04] [INFO ] Invariant cache hit.
[2023-03-09 06:59:04] [INFO ] Implicit Places using invariants and state equation in 213 ms returned []
Implicit Place search using SMT with State Equation took 498 ms to find 0 implicit places.
[2023-03-09 06:59:04] [INFO ] Invariant cache hit.
[2023-03-09 06:59:04] [INFO ] Dead Transitions using invariants and state equation in 202 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 214/217 places, 408/408 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 719 ms. Remains : 214/217 places, 408/408 transitions.
Support contains 214 out of 214 places after structural reductions.
[2023-03-09 06:59:04] [INFO ] Flatten gal took : 54 ms
[2023-03-09 06:59:05] [INFO ] Flatten gal took : 41 ms
[2023-03-09 06:59:05] [INFO ] Input system was already deterministic with 408 transitions.
Incomplete random walk after 10000 steps, including 1252 resets, run finished after 494 ms. (steps per millisecond=20 ) properties (out of 48) seen :39
Incomplete Best-First random walk after 10001 steps, including 26 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 24 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 25 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 22 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 17 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 20 resets, run finished after 128 ms. (steps per millisecond=78 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 13 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 24 resets, run finished after 8 ms. (steps per millisecond=1250 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 17 resets, run finished after 9 ms. (steps per millisecond=1111 ) properties (out of 9) seen :1
Running SMT prover for 8 properties.
[2023-03-09 06:59:06] [INFO ] Invariant cache hit.
[2023-03-09 06:59:06] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-09 06:59:07] [INFO ] After 882ms SMT Verify possible using all constraints in real domain returned unsat :5 sat :0 real:3
[2023-03-09 06:59:07] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 21 ms returned sat
[2023-03-09 06:59:08] [INFO ] After 573ms SMT Verify possible using all constraints in natural domain returned unsat :8 sat :0
Fused 8 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 8 atomic propositions for a total of 16 simplifications.
[2023-03-09 06:59:08] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 49 ms
[2023-03-09 06:59:08] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA AirplaneLD-PT-0050-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA AirplaneLD-PT-0050-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 46 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 408 transitions.
Computed a total of 214 stabilizing places and 408 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 214 transition count 408
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 2 formulas.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 146 places :
Symmetric choice reduction at 0 with 146 rule applications. Total rules 146 place count 68 transition count 262
Iterating global reduction 0 with 146 rules applied. Total rules applied 292 place count 68 transition count 262
Ensure Unique test removed 146 transitions
Reduce isomorphic transitions removed 146 transitions.
Iterating post reduction 0 with 146 rules applied. Total rules applied 438 place count 68 transition count 116
Applied a total of 438 rules in 7 ms. Remains 68 /214 variables (removed 146) and now considering 116/408 (removed 292) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 68/214 places, 116/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 4 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 4 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 172 places :
Symmetric choice reduction at 0 with 172 rule applications. Total rules 172 place count 42 transition count 236
Iterating global reduction 0 with 172 rules applied. Total rules applied 344 place count 42 transition count 236
Ensure Unique test removed 172 transitions
Reduce isomorphic transitions removed 172 transitions.
Iterating post reduction 0 with 172 rules applied. Total rules applied 516 place count 42 transition count 64
Applied a total of 516 rules in 4 ms. Remains 42 /214 variables (removed 172) and now considering 64/408 (removed 344) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 42/214 places, 64/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 4 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 147 places :
Symmetric choice reduction at 0 with 147 rule applications. Total rules 147 place count 67 transition count 261
Iterating global reduction 0 with 147 rules applied. Total rules applied 294 place count 67 transition count 261
Ensure Unique test removed 147 transitions
Reduce isomorphic transitions removed 147 transitions.
Iterating post reduction 0 with 147 rules applied. Total rules applied 441 place count 67 transition count 114
Applied a total of 441 rules in 3 ms. Remains 67 /214 variables (removed 147) and now considering 114/408 (removed 294) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 67/214 places, 114/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 4 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 4 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 114 transitions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 121 places :
Symmetric choice reduction at 0 with 121 rule applications. Total rules 121 place count 93 transition count 287
Iterating global reduction 0 with 121 rules applied. Total rules applied 242 place count 93 transition count 287
Ensure Unique test removed 121 transitions
Reduce isomorphic transitions removed 121 transitions.
Iterating post reduction 0 with 121 rules applied. Total rules applied 363 place count 93 transition count 166
Applied a total of 363 rules in 3 ms. Remains 93 /214 variables (removed 121) and now considering 166/408 (removed 242) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 93/214 places, 166/408 transitions.
[2023-03-09 06:59:08] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 6 ms
FORMULA AirplaneLD-PT-0050-CTLFireability-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 4 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 166 transitions.
Support contains 0 out of 93 places (down from 86) after GAL structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 191 transition count 385
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 191 transition count 385
Ensure Unique test removed 23 transitions
Reduce isomorphic transitions removed 23 transitions.
Iterating post reduction 0 with 23 rules applied. Total rules applied 69 place count 191 transition count 362
Applied a total of 69 rules in 3 ms. Remains 191 /214 variables (removed 23) and now considering 362/408 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 191/214 places, 362/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 12 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 13 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 362 transitions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 171 places :
Symmetric choice reduction at 0 with 171 rule applications. Total rules 171 place count 43 transition count 237
Iterating global reduction 0 with 171 rules applied. Total rules applied 342 place count 43 transition count 237
Ensure Unique test removed 171 transitions
Reduce isomorphic transitions removed 171 transitions.
Iterating post reduction 0 with 171 rules applied. Total rules applied 513 place count 43 transition count 66
Applied a total of 513 rules in 3 ms. Remains 43 /214 variables (removed 171) and now considering 66/408 (removed 342) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 43/214 places, 66/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 66 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Graph (complete) has 287 edges and 214 vertex of which 111 are kept as prefixes of interest. Removing 103 places using SCC suffix rule.1 ms
Discarding 103 places :
Also discarding 150 output transitions
Drop transitions removed 150 transitions
Ensure Unique test removed 49 transitions
Reduce isomorphic transitions removed 49 transitions.
Iterating post reduction 0 with 49 rules applied. Total rules applied 50 place count 111 transition count 209
Discarding 97 places :
Symmetric choice reduction at 1 with 97 rule applications. Total rules 147 place count 14 transition count 112
Iterating global reduction 1 with 97 rules applied. Total rules applied 244 place count 14 transition count 112
Ensure Unique test removed 97 transitions
Reduce isomorphic transitions removed 97 transitions.
Iterating post reduction 1 with 97 rules applied. Total rules applied 341 place count 14 transition count 15
Applied a total of 341 rules in 8 ms. Remains 14 /214 variables (removed 200) and now considering 15/408 (removed 393) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 14/214 places, 15/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 194 places :
Symmetric choice reduction at 0 with 194 rule applications. Total rules 194 place count 20 transition count 214
Iterating global reduction 0 with 194 rules applied. Total rules applied 388 place count 20 transition count 214
Ensure Unique test removed 194 transitions
Reduce isomorphic transitions removed 194 transitions.
Iterating post reduction 0 with 194 rules applied. Total rules applied 582 place count 20 transition count 20
Applied a total of 582 rules in 3 ms. Remains 20 /214 variables (removed 194) and now considering 20/408 (removed 388) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 20/214 places, 20/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 195 places :
Symmetric choice reduction at 0 with 195 rule applications. Total rules 195 place count 19 transition count 213
Iterating global reduction 0 with 195 rules applied. Total rules applied 390 place count 19 transition count 213
Ensure Unique test removed 195 transitions
Reduce isomorphic transitions removed 195 transitions.
Iterating post reduction 0 with 195 rules applied. Total rules applied 585 place count 19 transition count 18
Applied a total of 585 rules in 3 ms. Remains 19 /214 variables (removed 195) and now considering 18/408 (removed 390) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 19/214 places, 18/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 189 places :
Symmetric choice reduction at 0 with 189 rule applications. Total rules 189 place count 25 transition count 219
Iterating global reduction 0 with 189 rules applied. Total rules applied 378 place count 25 transition count 219
Ensure Unique test removed 189 transitions
Reduce isomorphic transitions removed 189 transitions.
Iterating post reduction 0 with 189 rules applied. Total rules applied 567 place count 25 transition count 30
Applied a total of 567 rules in 3 ms. Remains 25 /214 variables (removed 189) and now considering 30/408 (removed 378) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 25/214 places, 30/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 195 places :
Symmetric choice reduction at 0 with 195 rule applications. Total rules 195 place count 19 transition count 213
Iterating global reduction 0 with 195 rules applied. Total rules applied 390 place count 19 transition count 213
Ensure Unique test removed 195 transitions
Reduce isomorphic transitions removed 195 transitions.
Iterating post reduction 0 with 195 rules applied. Total rules applied 585 place count 19 transition count 18
Applied a total of 585 rules in 2 ms. Remains 19 /214 variables (removed 195) and now considering 18/408 (removed 390) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 19/214 places, 18/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Graph (complete) has 287 edges and 214 vertex of which 1 are kept as prefixes of interest. Removing 213 places using SCC suffix rule.0 ms
Discarding 213 places :
Also discarding 358 output transitions
Drop transitions removed 358 transitions
Ensure Unique test removed 49 transitions
Reduce isomorphic transitions removed 49 transitions.
Iterating post reduction 0 with 49 rules applied. Total rules applied 50 place count 1 transition count 1
Applied a total of 50 rules in 1 ms. Remains 1 /214 variables (removed 213) and now considering 1/408 (removed 407) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 1/214 places, 1/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 1 transitions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Discarding 194 places :
Symmetric choice reduction at 0 with 194 rule applications. Total rules 194 place count 20 transition count 214
Iterating global reduction 0 with 194 rules applied. Total rules applied 388 place count 20 transition count 214
Ensure Unique test removed 194 transitions
Reduce isomorphic transitions removed 194 transitions.
Iterating post reduction 0 with 194 rules applied. Total rules applied 582 place count 20 transition count 20
Applied a total of 582 rules in 2 ms. Remains 20 /214 variables (removed 194) and now considering 20/408 (removed 388) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 20/214 places, 20/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 214/214 places, 408/408 transitions.
Graph (complete) has 287 edges and 214 vertex of which 162 are kept as prefixes of interest. Removing 52 places using SCC suffix rule.1 ms
Discarding 52 places :
Also discarding 100 output transitions
Drop transitions removed 100 transitions
Discarding 146 places :
Symmetric choice reduction at 0 with 146 rule applications. Total rules 147 place count 16 transition count 162
Iterating global reduction 0 with 146 rules applied. Total rules applied 293 place count 16 transition count 162
Ensure Unique test removed 146 transitions
Reduce isomorphic transitions removed 146 transitions.
Iterating post reduction 0 with 146 rules applied. Total rules applied 439 place count 16 transition count 16
Applied a total of 439 rules in 4 ms. Remains 16 /214 variables (removed 198) and now considering 16/408 (removed 392) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 16/214 places, 16/408 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:59:08] [INFO ] Input system was already deterministic with 16 transitions.
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 14 ms
[2023-03-09 06:59:08] [INFO ] Flatten gal took : 15 ms
[2023-03-09 06:59:08] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 6 ms.
[2023-03-09 06:59:08] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 214 places, 408 transitions and 895 arcs took 2 ms.
Total runtime 5086 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT AirplaneLD-PT-0050
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/380
CTLFireability
FORMULA AirplaneLD-PT-0050-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678345188916
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/380/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/380/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/380/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 55 (type SKEL/SRCH) for 23 AirplaneLD-PT-0050-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SKEL/SRCH) for 9 AirplaneLD-PT-0050-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 55 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-08
lola: result : false
lola: markings : 10
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH INITIAL
lola: LAUNCH task # 40 (type CNST) for 39 AirplaneLD-PT-0050-CTLFireability-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 40 (type CNST) for AirplaneLD-PT-0050-CTLFireability-12
lola: result : true
lola: FINISHED task # 56 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-06
lola: result : false
lola: markings : 163
lola: fired transitions : 517
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 4 (type EXCL) for 3 AirplaneLD-PT-0050-CTLFireability-01
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 57 (type SKEL/SRCH) for 20 AirplaneLD-PT-0050-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 58 (type SKEL/SRCH) for 9 AirplaneLD-PT-0050-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 57 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-07
lola: result : false
lola: markings : 4187
lola: fired transitions : 50389
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 59 (type SKEL/SRCH) for 42 AirplaneLD-PT-0050-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: FINISHED task # 59 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-13
lola: result : false
lola: markings : 30
lola: fired transitions : 29
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 60 (type SKEL/SRCH) for 23 AirplaneLD-PT-0050-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 60 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-08
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 61 (type SKEL/SRCH) for 52 AirplaneLD-PT-0050-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 61 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-15
lola: result : false
lola: markings : 216
lola: fired transitions : 722
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 62 (type SKEL/SRCH) for 45 AirplaneLD-PT-0050-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 62 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-14
lola: result : true
lola: markings : 305
lola: fired transitions : 466
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 58 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-06
lola: result : false
lola: markings : 35280
lola: fired transitions : 75208
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 4 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-01
lola: result : false
lola: markings : 521227
lola: fired transitions : 773668
lola: time used : 2.000000
lola: memory pages used : 3
lola: LAUNCH task # 50 (type EXCL) for 45 AirplaneLD-PT-0050-CTLFireability-14
lola: time limit : 449 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0050-CTLFireability-01: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-06: CONJ false CONJ
AirplaneLD-PT-0050-CTLFireability-07: CTL false skeleton: CTL model checker
AirplaneLD-PT-0050-CTLFireability-12: INITIAL true preprocessing
AirplaneLD-PT-0050-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0050-CTLFireability-15: EGEF false skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-14: CONJ 0 0 1 0 2 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 3/449 3/32 AirplaneLD-PT-0050-CTLFireability-14 554236 m, 110847 m/sec, 1661766 t fired, .
Time elapsed: 6 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 13
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AirplaneLD-PT-0050-CTLFireability-01: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-06: CONJ false CONJ
AirplaneLD-PT-0050-CTLFireability-07: CTL false skeleton: CTL model checker
AirplaneLD-PT-0050-CTLFireability-12: INITIAL true preprocessing
AirplaneLD-PT-0050-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0050-CTLFireability-15: EGEF false skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-14: CONJ 0 0 1 0 2 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 8/449 6/32 AirplaneLD-PT-0050-CTLFireability-14 1185814 m, 126315 m/sec, 4286747 t fired, .
Time elapsed: 11 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0050-CTLFireability-01: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-06: CONJ false CONJ
AirplaneLD-PT-0050-CTLFireability-07: CTL false skeleton: CTL model checker
AirplaneLD-PT-0050-CTLFireability-12: INITIAL true preprocessing
AirplaneLD-PT-0050-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0050-CTLFireability-15: EGEF false skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-14: CONJ 0 0 1 0 2 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 13/449 9/32 AirplaneLD-PT-0050-CTLFireability-14 1803580 m, 123553 m/sec, 6935571 t fired, .
Time elapsed: 16 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0050-CTLFireability-01: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-06: CONJ false CONJ
AirplaneLD-PT-0050-CTLFireability-07: CTL false skeleton: CTL model checker
AirplaneLD-PT-0050-CTLFireability-12: INITIAL true preprocessing
AirplaneLD-PT-0050-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0050-CTLFireability-15: EGEF false skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-14: CONJ 0 0 1 0 2 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 18/449 12/32 AirplaneLD-PT-0050-CTLFireability-14 2400158 m, 119315 m/sec, 9480833 t fired, .
Time elapsed: 21 secs. Pages in use: 12
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0050-CTLFireability-01: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-06: CONJ false CONJ
AirplaneLD-PT-0050-CTLFireability-07: CTL false skeleton: CTL model checker
AirplaneLD-PT-0050-CTLFireability-12: INITIAL true preprocessing
AirplaneLD-PT-0050-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0050-CTLFireability-15: EGEF false skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-14: CONJ 0 0 1 0 2 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 23/449 15/32 AirplaneLD-PT-0050-CTLFireability-14 3030404 m, 126049 m/sec, 12230256 t fired, .
Time elapsed: 26 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0050-CTLFireability-01: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-06: CONJ false CONJ
AirplaneLD-PT-0050-CTLFireability-07: CTL false skeleton: CTL model checker
AirplaneLD-PT-0050-CTLFireability-12: INITIAL true preprocessing
AirplaneLD-PT-0050-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0050-CTLFireability-15: EGEF false skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-14: CONJ 0 0 1 0 2 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 28/449 18/32 AirplaneLD-PT-0050-CTLFireability-14 3722065 m, 138332 m/sec, 15152343 t fired, .
Time elapsed: 31 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0050-CTLFireability-01: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-06: CONJ false CONJ
AirplaneLD-PT-0050-CTLFireability-07: CTL false skeleton: CTL model checker
AirplaneLD-PT-0050-CTLFireability-12: INITIAL true preprocessing
AirplaneLD-PT-0050-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0050-CTLFireability-15: EGEF false skeleton: CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0050-CTLFireability-14: CONJ 0 0 1 0 2 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 33/449 20/32 AirplaneLD-PT-0050-CTLFireability-14 4251192 m, 105825 m/sec, 17743159 t fired, .
Time elapsed: 36 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 13
lola: FINISHED task # 50 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-14
lola: result : true
lola: markings : 4434661
lola: fired transitions : 18646240
lola: time used : 35.000000
lola: memory pages used : 21
lola: LAUNCH task # 37 (type EXCL) for 36 AirplaneLD-PT-0050-CTLFireability-11
lola: time limit : 508 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-11
lola: result : true
lola: markings : 60
lola: fired transitions : 141
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 AirplaneLD-PT-0050-CTLFireability-10
lola: time limit : 593 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 AirplaneLD-PT-0050-CTLFireability-09
lola: time limit : 712 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-09
lola: result : false
lola: markings : 44
lola: fired transitions : 73
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 AirplaneLD-PT-0050-CTLFireability-02
lola: time limit : 890 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-02
lola: result : false
lola: markings : 5216
lola: fired transitions : 18144
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 AirplaneLD-PT-0050-CTLFireability-00
lola: time limit : 1187 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-00
lola: result : false
lola: markings : 525519
lola: fired transitions : 1038102
lola: time used : 2.000000
lola: memory pages used : 3
lola: LAUNCH task # 28 (type EXCL) for 23 AirplaneLD-PT-0050-CTLFireability-08
lola: time limit : 1780 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-08
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 23 AirplaneLD-PT-0050-CTLFireability-08
lola: time limit : 3560 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-08
lola: result : false
lola: markings : 11
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0050-CTLFireability-00: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-01: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-02: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-06: CONJ false CONJ
AirplaneLD-PT-0050-CTLFireability-07: CTL false skeleton: CTL model checker
AirplaneLD-PT-0050-CTLFireability-08: CONJ false CTL model checker
AirplaneLD-PT-0050-CTLFireability-09: CTL false CTL model checker
AirplaneLD-PT-0050-CTLFireability-10: CTL true CTL model checker
AirplaneLD-PT-0050-CTLFireability-11: CTL true CTL model checker
AirplaneLD-PT-0050-CTLFireability-12: INITIAL true preprocessing
AirplaneLD-PT-0050-CTLFireability-13: EG false skeleton: state space / EG
AirplaneLD-PT-0050-CTLFireability-14: CONJ true CONJ
AirplaneLD-PT-0050-CTLFireability-15: EGEF false skeleton: CTL model checker
Time elapsed: 40 secs. Pages in use: 21
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is AirplaneLD-PT-0050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595200258"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0050.tgz
mv AirplaneLD-PT-0050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;