Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595200250.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is AirplaneLD-PT-0020, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595200250
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 936K
-rw-r--r-- 1 mcc users 24K Feb 26 11:15 CTLCardinality.txt
-rw-r--r-- 1 mcc users 142K Feb 26 11:15 CTLCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 11:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 80K Feb 26 11:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 8.4K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 39K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 35K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 26K Feb 26 11:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 140K Feb 26 11:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 34K Feb 26 11:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 242K Feb 26 11:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.6K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 91K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-00
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-01
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-02
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-03
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-04
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-05
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-06
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-07
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-08
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-09
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-10
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-11
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-12
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-13
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-14
FORMULA_NAME AirplaneLD-PT-0020-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678345059800

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-PT-0020
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 06:57:41] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 06:57:42] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 06:57:42] [INFO ] Load time of PNML (sax parser for PT used): 63 ms
[2023-03-09 06:57:42] [INFO ] Transformed 159 places.
[2023-03-09 06:57:42] [INFO ] Transformed 168 transitions.
[2023-03-09 06:57:42] [INFO ] Parsed PT model containing 159 places and 168 transitions and 638 arcs in 196 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Reduce places removed 62 places and 0 transitions.
Support contains 94 out of 97 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 97/97 places, 168/168 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 94 transition count 168
Applied a total of 3 rules in 11 ms. Remains 94 /97 variables (removed 3) and now considering 168/168 (removed 0) transitions.
// Phase 1: matrix 168 rows 94 cols
[2023-03-09 06:57:42] [INFO ] Computed 1 place invariants in 10 ms
[2023-03-09 06:57:42] [INFO ] Implicit Places using invariants in 156 ms returned []
[2023-03-09 06:57:42] [INFO ] Invariant cache hit.
[2023-03-09 06:57:42] [INFO ] Implicit Places using invariants and state equation in 121 ms returned []
Implicit Place search using SMT with State Equation took 308 ms to find 0 implicit places.
[2023-03-09 06:57:42] [INFO ] Invariant cache hit.
[2023-03-09 06:57:42] [INFO ] Dead Transitions using invariants and state equation in 122 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 94/97 places, 168/168 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 444 ms. Remains : 94/97 places, 168/168 transitions.
Support contains 94 out of 94 places after structural reductions.
[2023-03-09 06:57:42] [INFO ] Flatten gal took : 36 ms
[2023-03-09 06:57:42] [INFO ] Flatten gal took : 15 ms
[2023-03-09 06:57:43] [INFO ] Input system was already deterministic with 168 transitions.
Incomplete random walk after 10000 steps, including 1253 resets, run finished after 404 ms. (steps per millisecond=24 ) properties (out of 47) seen :40
Incomplete Best-First random walk after 10001 steps, including 56 resets, run finished after 82 ms. (steps per millisecond=121 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 39 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 56 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 47 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 39 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 34 resets, run finished after 7 ms. (steps per millisecond=1428 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 54 resets, run finished after 10 ms. (steps per millisecond=1000 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-09 06:57:43] [INFO ] Invariant cache hit.
[2023-03-09 06:57:43] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 06:57:43] [INFO ] After 138ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:7
[2023-03-09 06:57:43] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-09 06:57:44] [INFO ] After 401ms SMT Verify possible using all constraints in natural domain returned unsat :7 sat :0
Fused 7 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 7 atomic propositions for a total of 16 simplifications.
[2023-03-09 06:57:44] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 10 ms
FORMULA AirplaneLD-PT-0020-CTLFireability-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 9 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 168 transitions.
Support contains 62 out of 94 places (down from 74) after GAL structural reductions.
Computed a total of 94 stabilizing places and 168 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 94 transition count 168
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 3 formulas.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Graph (complete) has 122 edges and 94 vertex of which 1 are kept as prefixes of interest. Removing 93 places using SCC suffix rule.1 ms
Discarding 93 places :
Also discarding 166 output transitions
Drop transitions removed 166 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 1 transition count 1
Applied a total of 2 rules in 3 ms. Remains 1 /94 variables (removed 93) and now considering 1/168 (removed 167) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 1/94 places, 1/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 1 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=0 )
FORMULA AirplaneLD-PT-0020-CTLFireability-00 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Discarding 64 places :
Symmetric choice reduction at 0 with 64 rule applications. Total rules 64 place count 30 transition count 104
Iterating global reduction 0 with 64 rules applied. Total rules applied 128 place count 30 transition count 104
Ensure Unique test removed 64 transitions
Reduce isomorphic transitions removed 64 transitions.
Iterating post reduction 0 with 64 rules applied. Total rules applied 192 place count 30 transition count 40
Applied a total of 192 rules in 3 ms. Remains 30 /94 variables (removed 64) and now considering 40/168 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 30/94 places, 40/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 15 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Discarding 75 places :
Symmetric choice reduction at 0 with 75 rule applications. Total rules 75 place count 19 transition count 93
Iterating global reduction 0 with 75 rules applied. Total rules applied 150 place count 19 transition count 93
Ensure Unique test removed 75 transitions
Reduce isomorphic transitions removed 75 transitions.
Iterating post reduction 0 with 75 rules applied. Total rules applied 225 place count 19 transition count 18
Applied a total of 225 rules in 2 ms. Remains 19 /94 variables (removed 75) and now considering 18/168 (removed 150) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 19/94 places, 18/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Discarding 54 places :
Symmetric choice reduction at 0 with 54 rule applications. Total rules 54 place count 40 transition count 114
Iterating global reduction 0 with 54 rules applied. Total rules applied 108 place count 40 transition count 114
Ensure Unique test removed 54 transitions
Reduce isomorphic transitions removed 54 transitions.
Iterating post reduction 0 with 54 rules applied. Total rules applied 162 place count 40 transition count 60
Applied a total of 162 rules in 5 ms. Remains 40 /94 variables (removed 54) and now considering 60/168 (removed 108) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 40/94 places, 60/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Discarding 64 places :
Symmetric choice reduction at 0 with 64 rule applications. Total rules 64 place count 30 transition count 104
Iterating global reduction 0 with 64 rules applied. Total rules applied 128 place count 30 transition count 104
Ensure Unique test removed 64 transitions
Reduce isomorphic transitions removed 64 transitions.
Iterating post reduction 0 with 64 rules applied. Total rules applied 192 place count 30 transition count 40
Applied a total of 192 rules in 5 ms. Remains 30 /94 variables (removed 64) and now considering 40/168 (removed 128) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 30/94 places, 40/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Graph (complete) has 122 edges and 94 vertex of which 1 are kept as prefixes of interest. Removing 93 places using SCC suffix rule.0 ms
Discarding 93 places :
Also discarding 166 output transitions
Drop transitions removed 166 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 1 transition count 1
Applied a total of 2 rules in 1 ms. Remains 1 /94 variables (removed 93) and now considering 1/168 (removed 167) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 1/94 places, 1/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 1 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 48 transition count 122
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 48 transition count 122
Ensure Unique test removed 46 transitions
Reduce isomorphic transitions removed 46 transitions.
Iterating post reduction 0 with 46 rules applied. Total rules applied 138 place count 48 transition count 76
Applied a total of 138 rules in 2 ms. Remains 48 /94 variables (removed 46) and now considering 76/168 (removed 92) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 48/94 places, 76/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 3 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 3 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Discarding 74 places :
Symmetric choice reduction at 0 with 74 rule applications. Total rules 74 place count 20 transition count 94
Iterating global reduction 0 with 74 rules applied. Total rules applied 148 place count 20 transition count 94
Ensure Unique test removed 74 transitions
Reduce isomorphic transitions removed 74 transitions.
Iterating post reduction 0 with 74 rules applied. Total rules applied 222 place count 20 transition count 20
Applied a total of 222 rules in 2 ms. Remains 20 /94 variables (removed 74) and now considering 20/168 (removed 148) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 20/94 places, 20/168 transitions.
[2023-03-09 06:57:44] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
FORMULA AirplaneLD-PT-0020-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 20 transitions.
Support contains 0 out of 20 places (down from 3) after GAL structural reductions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Graph (complete) has 122 edges and 94 vertex of which 50 are kept as prefixes of interest. Removing 44 places using SCC suffix rule.1 ms
Discarding 44 places :
Also discarding 80 output transitions
Drop transitions removed 80 transitions
Discarding 38 places :
Symmetric choice reduction at 0 with 38 rule applications. Total rules 39 place count 12 transition count 50
Iterating global reduction 0 with 38 rules applied. Total rules applied 77 place count 12 transition count 50
Ensure Unique test removed 38 transitions
Reduce isomorphic transitions removed 38 transitions.
Iterating post reduction 0 with 38 rules applied. Total rules applied 115 place count 12 transition count 12
Applied a total of 115 rules in 3 ms. Remains 12 /94 variables (removed 82) and now considering 12/168 (removed 156) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 12/94 places, 12/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 12 transitions.
Finished random walk after 38 steps, including 6 resets, run visited all 1 properties in 2 ms. (steps per millisecond=19 )
FORMULA AirplaneLD-PT-0020-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Graph (complete) has 122 edges and 94 vertex of which 72 are kept as prefixes of interest. Removing 22 places using SCC suffix rule.0 ms
Discarding 22 places :
Also discarding 40 output transitions
Drop transitions removed 40 transitions
Discarding 56 places :
Symmetric choice reduction at 0 with 56 rule applications. Total rules 57 place count 16 transition count 72
Iterating global reduction 0 with 56 rules applied. Total rules applied 113 place count 16 transition count 72
Ensure Unique test removed 56 transitions
Reduce isomorphic transitions removed 56 transitions.
Iterating post reduction 0 with 56 rules applied. Total rules applied 169 place count 16 transition count 16
Applied a total of 169 rules in 3 ms. Remains 16 /94 variables (removed 78) and now considering 16/168 (removed 152) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 16/94 places, 16/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Discarding 74 places :
Symmetric choice reduction at 0 with 74 rule applications. Total rules 74 place count 20 transition count 94
Iterating global reduction 0 with 74 rules applied. Total rules applied 148 place count 20 transition count 94
Ensure Unique test removed 74 transitions
Reduce isomorphic transitions removed 74 transitions.
Iterating post reduction 0 with 74 rules applied. Total rules applied 222 place count 20 transition count 20
Applied a total of 222 rules in 1 ms. Remains 20 /94 variables (removed 74) and now considering 20/168 (removed 148) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 20/94 places, 20/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Discarding 73 places :
Symmetric choice reduction at 0 with 73 rule applications. Total rules 73 place count 21 transition count 95
Iterating global reduction 0 with 73 rules applied. Total rules applied 146 place count 21 transition count 95
Ensure Unique test removed 73 transitions
Reduce isomorphic transitions removed 73 transitions.
Iterating post reduction 0 with 73 rules applied. Total rules applied 219 place count 21 transition count 22
Applied a total of 219 rules in 1 ms. Remains 21 /94 variables (removed 73) and now considering 22/168 (removed 146) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 21/94 places, 22/168 transitions.
[2023-03-09 06:57:44] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
FORMULA AirplaneLD-PT-0020-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 22 transitions.
Support contains 0 out of 21 places (down from 5) after GAL structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Discarding 73 places :
Symmetric choice reduction at 0 with 73 rule applications. Total rules 73 place count 21 transition count 95
Iterating global reduction 0 with 73 rules applied. Total rules applied 146 place count 21 transition count 95
Ensure Unique test removed 73 transitions
Reduce isomorphic transitions removed 73 transitions.
Iterating post reduction 0 with 73 rules applied. Total rules applied 219 place count 21 transition count 22
Applied a total of 219 rules in 1 ms. Remains 21 /94 variables (removed 73) and now considering 22/168 (removed 146) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 21/94 places, 22/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Graph (complete) has 122 edges and 94 vertex of which 50 are kept as prefixes of interest. Removing 44 places using SCC suffix rule.1 ms
Discarding 44 places :
Also discarding 80 output transitions
Drop transitions removed 80 transitions
Discarding 38 places :
Symmetric choice reduction at 0 with 38 rule applications. Total rules 39 place count 12 transition count 50
Iterating global reduction 0 with 38 rules applied. Total rules applied 77 place count 12 transition count 50
Ensure Unique test removed 38 transitions
Reduce isomorphic transitions removed 38 transitions.
Iterating post reduction 0 with 38 rules applied. Total rules applied 115 place count 12 transition count 12
Applied a total of 115 rules in 2 ms. Remains 12 /94 variables (removed 82) and now considering 12/168 (removed 156) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 12/94 places, 12/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 12 transitions.
Finished random walk after 60 steps, including 10 resets, run visited all 1 properties in 1 ms. (steps per millisecond=60 )
FORMULA AirplaneLD-PT-0020-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 168/168 transitions.
Discarding 68 places :
Symmetric choice reduction at 0 with 68 rule applications. Total rules 68 place count 26 transition count 100
Iterating global reduction 0 with 68 rules applied. Total rules applied 136 place count 26 transition count 100
Ensure Unique test removed 68 transitions
Reduce isomorphic transitions removed 68 transitions.
Iterating post reduction 0 with 68 rules applied. Total rules applied 204 place count 26 transition count 32
Applied a total of 204 rules in 1 ms. Remains 26 /94 variables (removed 68) and now considering 32/168 (removed 136) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 26/94 places, 32/168 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:57:44] [INFO ] Input system was already deterministic with 32 transitions.
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 7 ms
[2023-03-09 06:57:44] [INFO ] Flatten gal took : 7 ms
[2023-03-09 06:57:44] [INFO ] Export to MCC of 10 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-09 06:57:44] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 94 places, 168 transitions and 370 arcs took 1 ms.
Total runtime 2662 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT AirplaneLD-PT-0020
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/377
CTLFireability

FORMULA AirplaneLD-PT-0020-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0020-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0020-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0020-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0020-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0020-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0020-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0020-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0020-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0020-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678345070152

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/377/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/377/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/377/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 34 (type SKEL/SRCH) for 0 AirplaneLD-PT-0020-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 34 (type SKEL/SRCH) for AirplaneLD-PT-0020-CTLFireability-01
lola: result : true
lola: markings : 323
lola: fired transitions : 1981
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 36 (type SKEL/FNDP) for 6 AirplaneLD-PT-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 37 (type SKEL/EQUN) for 6 AirplaneLD-PT-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 38 (type SKEL/SRCH) for 6 AirplaneLD-PT-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 39 (type SKEL/SRCH) for 6 AirplaneLD-PT-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: FINISHED task # 36 (type SKEL/FNDP) for AirplaneLD-PT-0020-CTLFireability-04
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 37 (type EQUN) for AirplaneLD-PT-0020-CTLFireability-04 (obsolete)
lola: CANCELED task # 38 (type SRCH) for AirplaneLD-PT-0020-CTLFireability-04 (obsolete)
lola: CANCELED task # 39 (type SRCH) for AirplaneLD-PT-0020-CTLFireability-04 (obsolete)
lola: FINISHED task # 37 (type SKEL/EQUN) for AirplaneLD-PT-0020-CTLFireability-04
lola: result : unknown
lola: FINISHED task # 38 (type SKEL/SRCH) for AirplaneLD-PT-0020-CTLFireability-04
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: planning for AirplaneLD-PT-0020-CTLFireability-01 stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 39 (type SKEL/SRCH) for AirplaneLD-PT-0020-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 40 (type SKEL/SRCH) for 16 AirplaneLD-PT-0020-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 40 (type SKEL/SRCH) for AirplaneLD-PT-0020-CTLFireability-06
lola: result : false
lola: markings : 24
lola: fired transitions : 23
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: planning for AirplaneLD-PT-0020-CTLFireability-06 stopped (result already fixed).
lola: LAUNCH task # 9 (type EXCL) for 6 AirplaneLD-PT-0020-CTLFireability-04
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: LAUNCH task # 41 (type SKEL/SRCH) for 25 AirplaneLD-PT-0020-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 41 (type SKEL/SRCH) for AirplaneLD-PT-0020-CTLFireability-11
lola: result : false
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 42 (type FNDP) for 6 AirplaneLD-PT-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: LAUNCH task # 43 (type EQUN) for 6 AirplaneLD-PT-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 45 (type SRCH) for 6 AirplaneLD-PT-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 45 (type SRCH) for AirplaneLD-PT-0020-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 42 (type FNDP) for AirplaneLD-PT-0020-CTLFireability-04
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 43 (type EQUN) for AirplaneLD-PT-0020-CTLFireability-04 (obsolete)
sara: try reading problem file /home/mcc/execution/377/CTLFireability-43.sara.
sara: error: :5: error: syntax error, unexpected $end, expecting KEY_TRANSITION
sara: error while reading Petri net from file -- aborting [#04]
sara: see manual for a documentation of this error
sara: last error message: No such file or directory
lola: FINISHED task # 43 (type EQUN) for AirplaneLD-PT-0020-CTLFireability-04
lola: result : unknown
lola: FINISHED task # 9 (type EXCL) for AirplaneLD-PT-0020-CTLFireability-04
lola: result : true
lola: markings : 308302
lola: fired transitions : 1647868
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 32 (type EXCL) for 31 AirplaneLD-PT-0020-CTLFireability-15
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for AirplaneLD-PT-0020-CTLFireability-15
lola: result : true
lola: markings : 308302
lola: fired transitions : 1578587
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 29 (type EXCL) for 28 AirplaneLD-PT-0020-CTLFireability-13
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for AirplaneLD-PT-0020-CTLFireability-13
lola: result : false
lola: markings : 202460
lola: fired transitions : 220240
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 AirplaneLD-PT-0020-CTLFireability-11
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for AirplaneLD-PT-0020-CTLFireability-11
lola: result : false
lola: markings : 531
lola: fired transitions : 1029
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 AirplaneLD-PT-0020-CTLFireability-07
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for AirplaneLD-PT-0020-CTLFireability-07
lola: result : false
lola: markings : 460
lola: fired transitions : 480
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 AirplaneLD-PT-0020-CTLFireability-03
lola: time limit : 1198 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for AirplaneLD-PT-0020-CTLFireability-03
lola: result : false
lola: markings : 25
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 AirplaneLD-PT-0020-CTLFireability-10
lola: time limit : 1798 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for AirplaneLD-PT-0020-CTLFireability-10
lola: result : false
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 AirplaneLD-PT-0020-CTLFireability-05
lola: time limit : 3596 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0020-CTLFireability-01: CTL true skeleton: CTL model checker
AirplaneLD-PT-0020-CTLFireability-03: CTL false CTL model checker
AirplaneLD-PT-0020-CTLFireability-04: CONJ true CONJ
AirplaneLD-PT-0020-CTLFireability-06: EG false skeleton: state space / EG
AirplaneLD-PT-0020-CTLFireability-07: CTL false CTL model checker
AirplaneLD-PT-0020-CTLFireability-10: CTL false CTL model checker
AirplaneLD-PT-0020-CTLFireability-11: CTL false CTL model checker
AirplaneLD-PT-0020-CTLFireability-13: CTL false CTL model checker
AirplaneLD-PT-0020-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0020-CTLFireability-05: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 1/3596 2/32 AirplaneLD-PT-0020-CTLFireability-05 283417 m, 56683 m/sec, 1486505 t fired, .

Time elapsed: 5 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 10
lola: FINISHED task # 14 (type EXCL) for AirplaneLD-PT-0020-CTLFireability-05
lola: result : true
lola: markings : 308302
lola: fired transitions : 1701660
lola: time used : 2.000000
lola: memory pages used : 2
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0020-CTLFireability-01: CTL true skeleton: CTL model checker
AirplaneLD-PT-0020-CTLFireability-03: CTL false CTL model checker
AirplaneLD-PT-0020-CTLFireability-04: CONJ true CONJ
AirplaneLD-PT-0020-CTLFireability-05: CTL true CTL model checker
AirplaneLD-PT-0020-CTLFireability-06: EG false skeleton: state space / EG
AirplaneLD-PT-0020-CTLFireability-07: CTL false CTL model checker
AirplaneLD-PT-0020-CTLFireability-10: CTL false CTL model checker
AirplaneLD-PT-0020-CTLFireability-11: CTL false CTL model checker
AirplaneLD-PT-0020-CTLFireability-13: CTL false CTL model checker
AirplaneLD-PT-0020-CTLFireability-15: CTL true CTL model checker


Time elapsed: 6 secs. Pages in use: 2

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0020"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is AirplaneLD-PT-0020, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595200250"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0020.tgz
mv AirplaneLD-PT-0020 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;