Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595200210.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is AirplaneLD-COL-0500, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595200210
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 532K
-rw-r--r-- 1 mcc users 7.2K Feb 26 11:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K Feb 26 11:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 26 11:32 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 26 11:32 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 12:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 96K Feb 26 12:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.6K Feb 26 12:11 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 26 12:11 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 109K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-00
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-01
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-02
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-03
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-04
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-05
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-06
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-07
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-08
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-09
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-10
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-11
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-12
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-13
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-14
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678344181989

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-COL-0500
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 06:43:04] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 06:43:04] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 06:43:04] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-09 06:43:05] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-09 06:43:05] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 676 ms
[2023-03-09 06:43:05] [INFO ] Detected 3 constant HL places corresponding to 1502 PT places.
[2023-03-09 06:43:05] [INFO ] Imported 20 HL places and 15 HL transitions for a total of 3519 PT places and 6012.0 transition bindings in 20 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
[2023-03-09 06:43:05] [INFO ] Built PT skeleton of HLPN with 20 places and 15 transitions 56 arcs in 4 ms.
[2023-03-09 06:43:05] [INFO ] Skeletonized 8 HLPN properties in 2 ms. Removed 8 properties that had guard overlaps.
Computed a total of 20 stabilizing places and 15 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 20 transition count 15
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 4 formulas.
FORMULA AirplaneLD-COL-0500-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 2 properties that can be checked using skeleton over-approximation.
Initial state reduction rules removed 1 formulas.
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
FORMULA AirplaneLD-COL-0500-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 17 stabilizing places and 14 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 17 transition count 14
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Finished random walk after 11 steps, including 1 resets, run visited all 1 properties in 8 ms. (steps per millisecond=1 )
[2023-03-09 06:43:05] [INFO ] Flatten gal took : 20 ms
[2023-03-09 06:43:05] [INFO ] Flatten gal took : 4 ms
Symmetric sort wr.t. initial and guards and successors and join/free detected :Altitude
Symmetric sort wr.t. initial detected :Altitude
Transition t3_2 : guard parameter $A(Altitude:1000) in guard (OR (GEQ $A 499) (EQ $A 999))introduces in Altitude(1000) partition with 2 elements
Transition t3_1 : guard parameter $A(Altitude:1000) in guard (AND (LT $A 499) (NEQ $A 999))introduces in Altitude(1000) partition with 2 elements
Sort wr.t. initial and guards Altitude has partition 2
Applying symmetric unfolding of partitioned symmetric sort :Altitude domain size was 1000 reducing to 2 values.
For transition t3_2:(OR (GEQ $A 499) (EQ $A 999)) -> (EQ $A 1)
For transition t3_1:(AND (LT $A 499) (NEQ $A 999)) -> (EQ $A 0)
Symmetric sort wr.t. initial and guards and successors and join/free detected :Speed
Symmetric sort wr.t. initial detected :Speed
Transition t5_2 : guard parameter $S(Speed:500) in guard (OR (LEQ $S 249) (EQ $S 499))introduces in Speed(500) partition with 2 elements
Transition t5_1 : guard parameter $S(Speed:500) in guard (AND (GT $S 249) (NEQ $S 499))introduces in Speed(500) partition with 2 elements
Transition t4_2 : guard parameter $S(Speed:500) in guard (OR (LEQ $S 249) (EQ $S 499))introduces in Speed(500) partition with 2 elements
Transition t4_1 : guard parameter $S(Speed:500) in guard (AND (GT $S 249) (NEQ $S 499))introduces in Speed(500) partition with 2 elements
Sort wr.t. initial and guards Speed has partition 2
Applying symmetric unfolding of partitioned symmetric sort :Speed domain size was 500 reducing to 2 values.
For transition t5_2:(OR (LEQ $S 249) (EQ $S 499)) -> (EQ $S 1)
For transition t5_1:(AND (GT $S 249) (NEQ $S 499)) -> (EQ $S 0)
For transition t4_2:(OR (LEQ $S 249) (EQ $S 499)) -> (EQ $S 1)
For transition t4_1:(AND (GT $S 249) (NEQ $S 499)) -> (EQ $S 0)
Symmetric sort wr.t. initial and guards and successors and join/free detected :Signal
Arc [19:1*[1]] contains constants of sort Signal
Transition t5_2 : constants on arcs in [[19:1*[1]]] introduces in Signal(2) partition with 1 elements that refines current partition to 2 subsets.
Symmetric sort wr.t. initial and guards and successors and join/free detected :Weight
Symmetric sort wr.t. initial detected :Weight
Transition t2_2 : guard parameter $W(Weight:2) in guard (EQ $W 1)introduces in Weight(2) partition with 2 elements
[2023-03-09 06:43:05] [INFO ] Unfolded HLPN to a Petri net with 29 places and 20 transitions 56 arcs in 53 ms.
[2023-03-09 06:43:05] [INFO ] Unfolded 14 HLPN properties in 0 ms.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:43:05] [INFO ] Reduced 1 identical enabling conditions.
Reduce places removed 6 places and 0 transitions.
Support contains 20 out of 23 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 23/23 places, 20/20 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 20 transition count 20
Applied a total of 3 rules in 5 ms. Remains 20 /23 variables (removed 3) and now considering 20/20 (removed 0) transitions.
// Phase 1: matrix 20 rows 20 cols
[2023-03-09 06:43:05] [INFO ] Computed 1 place invariants in 7 ms
[2023-03-09 06:43:05] [INFO ] Implicit Places using invariants in 188 ms returned []
[2023-03-09 06:43:05] [INFO ] Invariant cache hit.
[2023-03-09 06:43:06] [INFO ] Implicit Places using invariants and state equation in 79 ms returned []
Implicit Place search using SMT with State Equation took 296 ms to find 0 implicit places.
[2023-03-09 06:43:06] [INFO ] Invariant cache hit.
[2023-03-09 06:43:06] [INFO ] Dead Transitions using invariants and state equation in 74 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 20/23 places, 20/20 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 377 ms. Remains : 20/23 places, 20/20 transitions.
Support contains 20 out of 20 places after structural reductions.
[2023-03-09 06:43:06] [INFO ] Flatten gal took : 8 ms
[2023-03-09 06:43:06] [INFO ] Flatten gal took : 6 ms
[2023-03-09 06:43:06] [INFO ] Input system was already deterministic with 20 transitions.
Incomplete random walk after 10000 steps, including 1264 resets, run finished after 411 ms. (steps per millisecond=24 ) properties (out of 33) seen :27
Incomplete Best-First random walk after 10001 steps, including 239 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 250 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 248 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 231 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10000 steps, including 264 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 263 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-09 06:43:06] [INFO ] Invariant cache hit.
[2023-03-09 06:43:06] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-09 06:43:06] [INFO ] After 52ms SMT Verify possible using all constraints in real domain returned unsat :5 sat :0 real:1
[2023-03-09 06:43:07] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-09 06:43:07] [INFO ] After 43ms SMT Verify possible using all constraints in natural domain returned unsat :6 sat :0
Fused 6 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 6 atomic propositions for a total of 14 simplifications.
FORMULA AirplaneLD-COL-0500-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 5 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 3 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 20 transitions.
Computed a total of 20 stabilizing places and 20 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 20 transition count 20
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 1 formulas.
Starting structural reductions in SI_CTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Graph (complete) has 18 edges and 20 vertex of which 1 are kept as prefixes of interest. Removing 19 places using SCC suffix rule.0 ms
Discarding 19 places :
Also discarding 18 output transitions
Drop transitions removed 18 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 1 transition count 1
Applied a total of 2 rules in 4 ms. Remains 1 /20 variables (removed 19) and now considering 1/20 (removed 19) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 1/20 places, 1/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 1 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 19 transition count 19
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 19 transition count 19
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 19 transition count 18
Applied a total of 3 rules in 2 ms. Remains 19 /20 variables (removed 1) and now considering 18/20 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 19/20 places, 18/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 19 transition count 19
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 19 transition count 19
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 19 transition count 18
Applied a total of 3 rules in 1 ms. Remains 19 /20 variables (removed 1) and now considering 18/20 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 19/20 places, 18/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 20 /20 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 20/20 places, 20/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Graph (complete) has 18 edges and 20 vertex of which 10 are kept as prefixes of interest. Removing 10 places using SCC suffix rule.0 ms
Discarding 10 places :
Also discarding 8 output transitions
Drop transitions removed 8 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 3 place count 10 transition count 10
Applied a total of 3 rules in 1 ms. Remains 10 /20 variables (removed 10) and now considering 10/20 (removed 10) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 10/20 places, 10/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 19 transition count 19
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 19 transition count 19
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 19 transition count 18
Applied a total of 3 rules in 1 ms. Remains 19 /20 variables (removed 1) and now considering 18/20 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 19/20 places, 18/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Graph (complete) has 18 edges and 20 vertex of which 12 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.0 ms
Discarding 8 places :
Also discarding 8 output transitions
Drop transitions removed 8 transitions
Applied a total of 1 rules in 1 ms. Remains 12 /20 variables (removed 8) and now considering 12/20 (removed 8) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 12/20 places, 12/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Graph (complete) has 18 edges and 20 vertex of which 8 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.1 ms
Discarding 12 places :
Also discarding 12 output transitions
Drop transitions removed 12 transitions
Applied a total of 1 rules in 1 ms. Remains 8 /20 variables (removed 12) and now considering 8/20 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/20 places, 8/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 8 transitions.
Finished random walk after 15 steps, including 3 resets, run visited all 1 properties in 1 ms. (steps per millisecond=15 )
FORMULA AirplaneLD-COL-0500-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 20 /20 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 20/20 places, 20/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Graph (complete) has 18 edges and 20 vertex of which 8 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.0 ms
Discarding 12 places :
Also discarding 12 output transitions
Drop transitions removed 12 transitions
Applied a total of 1 rules in 1 ms. Remains 8 /20 variables (removed 12) and now considering 8/20 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/20 places, 8/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 8 transitions.
Finished random walk after 3 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=3 )
FORMULA AirplaneLD-COL-0500-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 20 /20 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 20/20 places, 20/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 20 /20 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 20/20 places, 20/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 20 /20 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 20/20 places, 20/20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Input system was already deterministic with 20 transitions.
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:43:07] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:43:07] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 1 ms.
[2023-03-09 06:43:07] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 20 places, 20 transitions and 44 arcs took 0 ms.
Total runtime 2490 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT AirplaneLD-COL-0500
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

FORMULA AirplaneLD-COL-0500-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0500-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0500-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0500-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0500-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0500-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0500-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0500-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0500-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0500-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0500-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678344187438

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 35 (type EXCL) for 34 AirplaneLD-COL-0500-CTLFireability-15
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: FINISHED task # 35 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-15
lola: result : true
lola: markings : 306
lola: fired transitions : 1037
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 AirplaneLD-COL-0500-CTLFireability-03
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-03
lola: result : false
lola: markings : 95
lola: fired transitions : 122
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 AirplaneLD-COL-0500-CTLFireability-02
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 7 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-02
lola: result : false
lola: markings : 37
lola: fired transitions : 66
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 AirplaneLD-COL-0500-CTLFireability-04
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 13 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-04
lola: result : false
lola: markings : 11
lola: fired transitions : 37
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 AirplaneLD-COL-0500-CTLFireability-01
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-01
lola: result : false
lola: markings : 17
lola: fired transitions : 43
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 32 (type EXCL) for 31 AirplaneLD-COL-0500-CTLFireability-14
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 32 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-14
lola: result : false
lola: markings : 243
lola: fired transitions : 825
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 AirplaneLD-COL-0500-CTLFireability-10
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 26 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-10
lola: result : false
lola: markings : 112
lola: fired transitions : 276
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 15 AirplaneLD-COL-0500-CTLFireability-06
lola: time limit : 720 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-06
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 15 AirplaneLD-COL-0500-CTLFireability-06
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-06
lola: result : false
lola: markings : 33
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 AirplaneLD-COL-0500-CTLFireability-00
lola: time limit : 1200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-00
lola: result : false
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 AirplaneLD-COL-0500-CTLFireability-07
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-07
lola: result : true
lola: markings : 6
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 AirplaneLD-COL-0500-CTLFireability-13
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-13
lola: result : false
lola: markings : 484
lola: fired transitions : 3756
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0500-CTLFireability-00: AGEF false tscc_search
AirplaneLD-COL-0500-CTLFireability-01: CTL false CTL model checker
AirplaneLD-COL-0500-CTLFireability-02: CTL false CTL model checker
AirplaneLD-COL-0500-CTLFireability-03: CTL false CTL model checker
AirplaneLD-COL-0500-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0500-CTLFireability-06: DISJ false DISJ
AirplaneLD-COL-0500-CTLFireability-07: EU true state space /EU
AirplaneLD-COL-0500-CTLFireability-10: CTL false CTL model checker
AirplaneLD-COL-0500-CTLFireability-13: CTL false CTL model checker
AirplaneLD-COL-0500-CTLFireability-14: CTL false CTL model checker
AirplaneLD-COL-0500-CTLFireability-15: CTL true CTL model checker


Time elapsed: 0 secs. Pages in use: 1

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0500"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is AirplaneLD-COL-0500, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595200210"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0500.tgz
mv AirplaneLD-COL-0500 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;