About the Execution of LoLa+red for AirplaneLD-COL-0200
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 226.420 | 5162.00 | 11954.00 | 35.00 | TTTTFFTTFTTTFTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595100202.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is AirplaneLD-COL-0200, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595100202
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 7.8K Feb 26 11:31 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 26 11:31 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 26 11:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 26 11:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 11:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 122K Feb 26 11:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 26 11:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 65K Feb 26 11:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 67K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-00
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-01
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-02
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-03
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-04
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-05
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-06
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-07
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-08
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-09
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-10
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-11
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-12
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-13
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-14
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678344115985
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-COL-0200
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 06:41:58] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 06:41:58] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 06:41:58] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-09 06:41:58] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-09 06:41:58] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 648 ms
[2023-03-09 06:41:58] [INFO ] Detected 3 constant HL places corresponding to 602 PT places.
[2023-03-09 06:41:58] [INFO ] Imported 20 HL places and 15 HL transitions for a total of 1419 PT places and 2412.0 transition bindings in 19 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
[2023-03-09 06:41:58] [INFO ] Built PT skeleton of HLPN with 20 places and 15 transitions 56 arcs in 3 ms.
[2023-03-09 06:41:58] [INFO ] Skeletonized 8 HLPN properties in 1 ms. Removed 8 properties that had guard overlaps.
Computed a total of 20 stabilizing places and 15 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 20 transition count 15
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 4 formulas.
FORMULA AirplaneLD-COL-0200-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA AirplaneLD-COL-0200-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 3 properties that can be checked using skeleton over-approximation.
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
Computed a total of 17 stabilizing places and 14 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 17 transition count 14
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Finished random walk after 51 steps, including 6 resets, run visited all 1 properties in 8 ms. (steps per millisecond=6 )
[2023-03-09 06:41:59] [INFO ] Flatten gal took : 14 ms
[2023-03-09 06:41:59] [INFO ] Flatten gal took : 3 ms
Symmetric sort wr.t. initial and guards and successors and join/free detected :Altitude
Symmetric sort wr.t. initial detected :Altitude
Transition t3_2 : guard parameter $A(Altitude:400) in guard (OR (GEQ $A 199) (EQ $A 399))introduces in Altitude(400) partition with 2 elements
Transition t3_1 : guard parameter $A(Altitude:400) in guard (AND (LT $A 199) (NEQ $A 399))introduces in Altitude(400) partition with 2 elements
Sort wr.t. initial and guards Altitude has partition 2
Applying symmetric unfolding of partitioned symmetric sort :Altitude domain size was 400 reducing to 2 values.
For transition t3_2:(OR (GEQ $A 199) (EQ $A 399)) -> (EQ $A 1)
For transition t3_1:(AND (LT $A 199) (NEQ $A 399)) -> (EQ $A 0)
Symmetric sort wr.t. initial and guards and successors and join/free detected :Speed
Symmetric sort wr.t. initial detected :Speed
Transition t5_2 : guard parameter $S(Speed:200) in guard (OR (LEQ $S 99) (EQ $S 199))introduces in Speed(200) partition with 2 elements
Transition t5_1 : guard parameter $S(Speed:200) in guard (AND (GT $S 99) (NEQ $S 199))introduces in Speed(200) partition with 2 elements
Transition t4_2 : guard parameter $S(Speed:200) in guard (OR (LEQ $S 99) (EQ $S 199))introduces in Speed(200) partition with 2 elements
Transition t4_1 : guard parameter $S(Speed:200) in guard (AND (GT $S 99) (NEQ $S 199))introduces in Speed(200) partition with 2 elements
Sort wr.t. initial and guards Speed has partition 2
Applying symmetric unfolding of partitioned symmetric sort :Speed domain size was 200 reducing to 2 values.
For transition t5_2:(OR (LEQ $S 99) (EQ $S 199)) -> (EQ $S 1)
For transition t5_1:(AND (GT $S 99) (NEQ $S 199)) -> (EQ $S 0)
For transition t4_2:(OR (LEQ $S 99) (EQ $S 199)) -> (EQ $S 1)
For transition t4_1:(AND (GT $S 99) (NEQ $S 199)) -> (EQ $S 0)
Symmetric sort wr.t. initial and guards and successors and join/free detected :Signal
Arc [19:1*[1]] contains constants of sort Signal
Transition t5_2 : constants on arcs in [[19:1*[1]]] introduces in Signal(2) partition with 1 elements that refines current partition to 2 subsets.
Symmetric sort wr.t. initial and guards and successors and join/free detected :Weight
Symmetric sort wr.t. initial detected :Weight
Transition t2_2 : guard parameter $W(Weight:2) in guard (EQ $W 1)introduces in Weight(2) partition with 2 elements
[2023-03-09 06:41:59] [INFO ] Unfolded HLPN to a Petri net with 29 places and 20 transitions 56 arcs in 22 ms.
[2023-03-09 06:41:59] [INFO ] Unfolded 14 HLPN properties in 1 ms.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-09 06:41:59] [INFO ] Reduced 1 identical enabling conditions.
Reduce places removed 6 places and 0 transitions.
Support contains 20 out of 23 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 23/23 places, 20/20 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 20 transition count 20
Applied a total of 3 rules in 8 ms. Remains 20 /23 variables (removed 3) and now considering 20/20 (removed 0) transitions.
// Phase 1: matrix 20 rows 20 cols
[2023-03-09 06:41:59] [INFO ] Computed 1 place invariants in 3 ms
[2023-03-09 06:41:59] [INFO ] Implicit Places using invariants in 189 ms returned []
[2023-03-09 06:41:59] [INFO ] Invariant cache hit.
[2023-03-09 06:41:59] [INFO ] Implicit Places using invariants and state equation in 118 ms returned []
Implicit Place search using SMT with State Equation took 352 ms to find 0 implicit places.
[2023-03-09 06:41:59] [INFO ] Invariant cache hit.
[2023-03-09 06:41:59] [INFO ] Dead Transitions using invariants and state equation in 150 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 20/23 places, 20/20 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 514 ms. Remains : 20/23 places, 20/20 transitions.
Support contains 20 out of 20 places after structural reductions.
[2023-03-09 06:41:59] [INFO ] Flatten gal took : 7 ms
[2023-03-09 06:41:59] [INFO ] Flatten gal took : 5 ms
[2023-03-09 06:41:59] [INFO ] Input system was already deterministic with 20 transitions.
Incomplete random walk after 10000 steps, including 1268 resets, run finished after 409 ms. (steps per millisecond=24 ) properties (out of 32) seen :25
Incomplete Best-First random walk after 10000 steps, including 232 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 241 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 240 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 263 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 246 resets, run finished after 11 ms. (steps per millisecond=909 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 263 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 259 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-09 06:42:00] [INFO ] Invariant cache hit.
[2023-03-09 06:42:00] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-09 06:42:00] [INFO ] After 68ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :0 real:3
[2023-03-09 06:42:00] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 06:42:00] [INFO ] After 55ms SMT Verify possible using all constraints in natural domain returned unsat :7 sat :0
Fused 7 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 7 atomic propositions for a total of 14 simplifications.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 3 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 20 transitions.
Computed a total of 20 stabilizing places and 20 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 20 transition count 20
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in SI_CTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Graph (complete) has 18 edges and 20 vertex of which 17 are kept as prefixes of interest. Removing 3 places using SCC suffix rule.0 ms
Discarding 3 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 17 transition count 17
Applied a total of 2 rules in 3 ms. Remains 17 /20 variables (removed 3) and now considering 17/20 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 17/20 places, 17/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 17 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 20 /20 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 20/20 places, 20/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 19 transition count 19
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 19 transition count 19
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 19 transition count 18
Applied a total of 3 rules in 1 ms. Remains 19 /20 variables (removed 1) and now considering 18/20 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 19/20 places, 18/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Graph (complete) has 18 edges and 20 vertex of which 16 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.0 ms
Discarding 4 places :
Also discarding 4 output transitions
Drop transitions removed 4 transitions
Applied a total of 1 rules in 1 ms. Remains 16 /20 variables (removed 4) and now considering 16/20 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 16/20 places, 16/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 16 transitions.
Finished random walk after 279 steps, including 41 resets, run visited all 1 properties in 2 ms. (steps per millisecond=139 )
FORMULA AirplaneLD-COL-0200-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 19 transition count 19
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 19 transition count 19
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 19 transition count 18
Applied a total of 3 rules in 1 ms. Remains 19 /20 variables (removed 1) and now considering 18/20 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 19/20 places, 18/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 20 /20 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 20/20 places, 20/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 19 transition count 19
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 19 transition count 19
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 19 transition count 18
Applied a total of 3 rules in 1 ms. Remains 19 /20 variables (removed 1) and now considering 18/20 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 19/20 places, 18/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 20 /20 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 20/20 places, 20/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 19 transition count 19
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 19 transition count 19
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 19 transition count 18
Applied a total of 3 rules in 2 ms. Remains 19 /20 variables (removed 1) and now considering 18/20 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 19/20 places, 18/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Graph (complete) has 18 edges and 20 vertex of which 16 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.1 ms
Discarding 4 places :
Also discarding 4 output transitions
Drop transitions removed 4 transitions
Applied a total of 1 rules in 1 ms. Remains 16 /20 variables (removed 4) and now considering 16/20 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 16/20 places, 16/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 16 transitions.
Finished random walk after 74 steps, including 10 resets, run visited all 1 properties in 1 ms. (steps per millisecond=74 )
FORMULA AirplaneLD-COL-0200-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 19 transition count 19
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 19 transition count 19
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 19 transition count 18
Applied a total of 3 rules in 1 ms. Remains 19 /20 variables (removed 1) and now considering 18/20 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 19/20 places, 18/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 20 /20 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 20/20 places, 20/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 19 transition count 19
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 19 transition count 19
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 19 transition count 18
Applied a total of 3 rules in 1 ms. Remains 19 /20 variables (removed 1) and now considering 18/20 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 19/20 places, 18/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 20/20 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 20 /20 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 20/20 places, 20/20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:42:00] [INFO ] Input system was already deterministic with 20 transitions.
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:42:00] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-09 06:42:00] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 20 places, 20 transitions and 44 arcs took 0 ms.
Total runtime 2518 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT AirplaneLD-COL-0200
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability
FORMULA AirplaneLD-COL-0200-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678344121147
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 14 (type EXCL) for 13 AirplaneLD-COL-0200-CTLFireability-04
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-04
lola: result : false
lola: markings : 85
lola: fired transitions : 105
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 AirplaneLD-COL-0200-CTLFireability-01
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type FNDP) for 25 AirplaneLD-COL-0200-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type EQUN) for 25 AirplaneLD-COL-0200-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type SRCH) for 25 AirplaneLD-COL-0200-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 55 (type SRCH) for AirplaneLD-COL-0200-CTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 4 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-01
lola: result : true
lola: markings : 484
lola: fired transitions : 2108
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 49 AirplaneLD-COL-0200-CTLFireability-15
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 50 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-15
lola: result : true
lola: markings : 11
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 AirplaneLD-COL-0200-CTLFireability-14
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-14
lola: result : true
lola: markings : 89
lola: fired transitions : 131
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 52 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-10
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 53 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-10 (obsolete)
lola: LAUNCH task # 44 (type EXCL) for 43 AirplaneLD-COL-0200-CTLFireability-13
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 53 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-10
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 56 (type FNDP) for 32 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 32 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type SRCH) for 32 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 59 (type SRCH) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 60 (type FNDP) for 32 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 44 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-13
lola: result : true
lola: markings : 9
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 56 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 57 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-12 (obsolete)
lola: LAUNCH task # 35 (type EXCL) for 32 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 61 (type EQUN) for 32 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type SRCH) for 32 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 60 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 61 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-12 (obsolete)
lola: CANCELED task # 63 (type SRCH) for AirplaneLD-COL-0200-CTLFireability-12 (obsolete)
lola: FINISHED task # 63 (type SRCH) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 35 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : false
lola: markings : 248
lola: fired transitions : 411
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 AirplaneLD-COL-0200-CTLFireability-08
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-08
lola: result : false
lola: markings : 10
lola: fired transitions : 32
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 AirplaneLD-COL-0200-CTLFireability-07
lola: time limit : 719 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/376/CTLFireability-61.sara.
lola: FINISHED task # 20 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-07
lola: result : true
lola: markings : 242
lola: sara: fired transitions : 989try reading problem file /home/mcc/execution/376/CTLFireability-57.sara.
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 6 AirplaneLD-COL-0200-CTLFireability-02
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-02
lola: result : true
lola: markings : 163
lola: fired transitions : 974
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 AirplaneLD-COL-0200-CTLFireability-05
lola: time limit : 1799 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-05
lola: result : false
lola: markings : 10
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 AirplaneLD-COL-0200-CTLFireability-00
lola: time limit : 3599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-00
lola: result : true
lola: markings : 11
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-00: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-01: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true findpath
AirplaneLD-COL-0200-CTLFireability-12: CONJ false CTL model checker
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: CTL true CTL model checker
Time elapsed: 1 secs. Pages in use: 2
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0200"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is AirplaneLD-COL-0200, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595100202"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0200.tgz
mv AirplaneLD-COL-0200 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;