About the Execution of LoLa+red for ASLink-PT-05a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1680.355 | 3600000.00 | 503933.00 | 276.20 | FTT?FFFFFTFF?TTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595000074.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ASLink-PT-05a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595000074
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 6.8K Feb 26 13:05 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 26 13:05 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 26 13:05 CTLFireability.txt
-rw-r--r-- 1 mcc users 75K Feb 26 13:05 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:29 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:29 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:29 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 13:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 190K Feb 26 13:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 26 13:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 61K Feb 26 13:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 516K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-05a-CTLFireability-00
FORMULA_NAME ASLink-PT-05a-CTLFireability-01
FORMULA_NAME ASLink-PT-05a-CTLFireability-02
FORMULA_NAME ASLink-PT-05a-CTLFireability-03
FORMULA_NAME ASLink-PT-05a-CTLFireability-04
FORMULA_NAME ASLink-PT-05a-CTLFireability-05
FORMULA_NAME ASLink-PT-05a-CTLFireability-06
FORMULA_NAME ASLink-PT-05a-CTLFireability-07
FORMULA_NAME ASLink-PT-05a-CTLFireability-08
FORMULA_NAME ASLink-PT-05a-CTLFireability-09
FORMULA_NAME ASLink-PT-05a-CTLFireability-10
FORMULA_NAME ASLink-PT-05a-CTLFireability-11
FORMULA_NAME ASLink-PT-05a-CTLFireability-12
FORMULA_NAME ASLink-PT-05a-CTLFireability-13
FORMULA_NAME ASLink-PT-05a-CTLFireability-14
FORMULA_NAME ASLink-PT-05a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678337962160
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ASLink-PT-05a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 04:59:25] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 04:59:25] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 04:59:25] [INFO ] Load time of PNML (sax parser for PT used): 176 ms
[2023-03-09 04:59:25] [INFO ] Transformed 1211 places.
[2023-03-09 04:59:25] [INFO ] Transformed 1827 transitions.
[2023-03-09 04:59:25] [INFO ] Found NUPN structural information;
[2023-03-09 04:59:25] [INFO ] Parsed PT model containing 1211 places and 1827 transitions and 6877 arcs in 309 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Ensure Unique test removed 19 transitions
Reduce redundant transitions removed 19 transitions.
Support contains 241 out of 1211 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1211/1211 places, 1808/1808 transitions.
Ensure Unique test removed 18 places
Discarding 8 places :
Implicit places reduction removed 8 places
Iterating post reduction 0 with 26 rules applied. Total rules applied 26 place count 1185 transition count 1808
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 31 place count 1180 transition count 1793
Iterating global reduction 1 with 5 rules applied. Total rules applied 36 place count 1180 transition count 1793
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 37 place count 1180 transition count 1792
Applied a total of 37 rules in 171 ms. Remains 1180 /1211 variables (removed 31) and now considering 1792/1808 (removed 16) transitions.
// Phase 1: matrix 1792 rows 1180 cols
[2023-03-09 04:59:25] [INFO ] Computed 206 place invariants in 111 ms
[2023-03-09 04:59:28] [INFO ] Implicit Places using invariants in 2838 ms returned [1, 20, 21, 24, 35, 71, 200, 217, 222, 261, 391, 407, 413, 451, 580, 601, 602, 622, 640, 769, 785, 790, 792, 810, 828, 958, 963, 975, 980, 981, 1019, 1040, 1042, 1043, 1044, 1061, 1069, 1077, 1083, 1089, 1095, 1101, 1109, 1115, 1121, 1129]
Discarding 46 places :
Implicit Place search using SMT only with invariants took 2893 ms to find 46 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 1134/1211 places, 1792/1808 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 1123 transition count 1781
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 1123 transition count 1781
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 30 place count 1115 transition count 1773
Iterating global reduction 0 with 8 rules applied. Total rules applied 38 place count 1115 transition count 1773
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 42 place count 1111 transition count 1769
Iterating global reduction 0 with 4 rules applied. Total rules applied 46 place count 1111 transition count 1769
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 47 place count 1110 transition count 1768
Iterating global reduction 0 with 1 rules applied. Total rules applied 48 place count 1110 transition count 1768
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 49 place count 1109 transition count 1767
Iterating global reduction 0 with 1 rules applied. Total rules applied 50 place count 1109 transition count 1767
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 51 place count 1108 transition count 1766
Iterating global reduction 0 with 1 rules applied. Total rules applied 52 place count 1108 transition count 1766
Applied a total of 52 rules in 195 ms. Remains 1108 /1134 variables (removed 26) and now considering 1766/1792 (removed 26) transitions.
// Phase 1: matrix 1766 rows 1108 cols
[2023-03-09 04:59:28] [INFO ] Computed 160 place invariants in 31 ms
[2023-03-09 04:59:29] [INFO ] Implicit Places using invariants in 790 ms returned []
[2023-03-09 04:59:29] [INFO ] Invariant cache hit.
[2023-03-09 04:59:33] [INFO ] Implicit Places using invariants and state equation in 3655 ms returned []
Implicit Place search using SMT with State Equation took 4475 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 1108/1211 places, 1766/1808 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 7736 ms. Remains : 1108/1211 places, 1766/1808 transitions.
Support contains 241 out of 1108 places after structural reductions.
[2023-03-09 04:59:33] [INFO ] Flatten gal took : 252 ms
[2023-03-09 04:59:34] [INFO ] Flatten gal took : 104 ms
[2023-03-09 04:59:34] [INFO ] Input system was already deterministic with 1766 transitions.
Support contains 233 out of 1108 places (down from 241) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 62 resets, run finished after 644 ms. (steps per millisecond=15 ) properties (out of 123) seen :45
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 78) seen :0
Running SMT prover for 78 properties.
[2023-03-09 04:59:35] [INFO ] Invariant cache hit.
[2023-03-09 04:59:38] [INFO ] [Real]Absence check using 31 positive place invariants in 105 ms returned sat
[2023-03-09 04:59:38] [INFO ] [Real]Absence check using 31 positive and 129 generalized place invariants in 154 ms returned sat
[2023-03-09 04:59:40] [INFO ] After 4482ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:78
[2023-03-09 04:59:42] [INFO ] [Nat]Absence check using 31 positive place invariants in 64 ms returned sat
[2023-03-09 04:59:42] [INFO ] [Nat]Absence check using 31 positive and 129 generalized place invariants in 81 ms returned sat
[2023-03-09 05:00:05] [INFO ] After 20737ms SMT Verify possible using state equation in natural domain returned unsat :31 sat :45
[2023-03-09 05:00:05] [INFO ] After 20740ms SMT Verify possible using trap constraints in natural domain returned unsat :31 sat :45
Attempting to minimize the solution found.
Minimization took 0 ms.
[2023-03-09 05:00:05] [INFO ] After 25036ms SMT Verify possible using all constraints in natural domain returned unsat :31 sat :45
Fused 78 Parikh solutions to 8 different solutions.
Parikh walk visited 1 properties in 378 ms.
Support contains 101 out of 1108 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1108/1108 places, 1766/1766 transitions.
Ensure Unique test removed 2 places
Discarding 2 places :
Implicit places reduction removed 2 places
Drop transitions removed 141 transitions
Trivial Post-agglo rules discarded 141 transitions
Performed 141 trivial Post agglomeration. Transition count delta: 141
Iterating post reduction 0 with 145 rules applied. Total rules applied 145 place count 1104 transition count 1625
Reduce places removed 141 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 142 rules applied. Total rules applied 287 place count 963 transition count 1624
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 288 place count 962 transition count 1624
Performed 125 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 125 Pre rules applied. Total rules applied 288 place count 962 transition count 1499
Deduced a syphon composed of 125 places in 6 ms
Ensure Unique test removed 45 places
Reduce places removed 170 places and 0 transitions.
Iterating global reduction 3 with 295 rules applied. Total rules applied 583 place count 792 transition count 1499
Discarding 2 places :
Implicit places reduction removed 2 places
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 3 with 6 rules applied. Total rules applied 589 place count 790 transition count 1495
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 593 place count 786 transition count 1495
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 8 Pre rules applied. Total rules applied 593 place count 786 transition count 1487
Deduced a syphon composed of 8 places in 2 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 5 with 16 rules applied. Total rules applied 609 place count 778 transition count 1487
Discarding 3 places :
Symmetric choice reduction at 5 with 3 rule applications. Total rules 612 place count 775 transition count 1479
Iterating global reduction 5 with 3 rules applied. Total rules applied 615 place count 775 transition count 1479
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 1 Pre rules applied. Total rules applied 615 place count 775 transition count 1478
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 617 place count 774 transition count 1478
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 618 place count 773 transition count 1477
Iterating global reduction 5 with 1 rules applied. Total rules applied 619 place count 773 transition count 1477
Performed 56 Post agglomeration using F-continuation condition.Transition count delta: 56
Deduced a syphon composed of 56 places in 2 ms
Reduce places removed 56 places and 0 transitions.
Iterating global reduction 5 with 112 rules applied. Total rules applied 731 place count 717 transition count 1421
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 732 place count 716 transition count 1420
Iterating global reduction 5 with 1 rules applied. Total rules applied 733 place count 716 transition count 1420
Free-agglomeration rule applied 3 times.
Iterating global reduction 5 with 3 rules applied. Total rules applied 736 place count 716 transition count 1417
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 739 place count 713 transition count 1417
Free-agglomeration rule (complex) applied 25 times.
Iterating global reduction 6 with 25 rules applied. Total rules applied 764 place count 713 transition count 1394
Reduce places removed 25 places and 0 transitions.
Iterating post reduction 6 with 25 rules applied. Total rules applied 789 place count 688 transition count 1394
Partial Free-agglomeration rule applied 8 times.
Drop transitions removed 8 transitions
Iterating global reduction 7 with 8 rules applied. Total rules applied 797 place count 688 transition count 1394
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 7 with 2 rules applied. Total rules applied 799 place count 688 transition count 1394
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 7 with 1 rules applied. Total rules applied 800 place count 688 transition count 1393
Applied a total of 800 rules in 423 ms. Remains 688 /1108 variables (removed 420) and now considering 1393/1766 (removed 373) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 423 ms. Remains : 688/1108 places, 1393/1766 transitions.
Incomplete random walk after 10000 steps, including 158 resets, run finished after 410 ms. (steps per millisecond=24 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Interrupted probabilistic random walk after 61068 steps, run timeout after 3001 ms. (steps per millisecond=20 ) properties seen :{0=1, 2=1, 4=1, 9=1, 15=1, 31=1, 43=1}
Probabilistic random walk after 61068 steps, saw 57712 distinct states, run finished after 3003 ms. (steps per millisecond=20 ) properties seen :7
Running SMT prover for 39 properties.
[2023-03-09 05:00:09] [INFO ] Flow matrix only has 1392 transitions (discarded 1 similar events)
// Phase 1: matrix 1392 rows 688 cols
[2023-03-09 05:00:09] [INFO ] Computed 109 place invariants in 11 ms
[2023-03-09 05:00:10] [INFO ] After 670ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:39
[2023-03-09 05:00:11] [INFO ] [Nat]Absence check using 31 positive place invariants in 7 ms returned sat
[2023-03-09 05:00:11] [INFO ] [Nat]Absence check using 31 positive and 78 generalized place invariants in 189 ms returned sat
[2023-03-09 05:00:35] [INFO ] After 22348ms SMT Verify possible using state equation in natural domain returned unsat :23 sat :15
[2023-03-09 05:00:35] [INFO ] State equation strengthened by 24 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-09 05:00:35] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-09 05:00:35] [INFO ] After 25043ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:39
Fused 39 Parikh solutions to 12 different solutions.
Parikh walk visited 0 properties in 801 ms.
Support contains 38 out of 688 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 688/688 places, 1393/1393 transitions.
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 688 transition count 1386
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 14 place count 681 transition count 1386
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 14 place count 681 transition count 1384
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 18 place count 679 transition count 1384
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 19 place count 678 transition count 1383
Ensure Unique test removed 1 places
Iterating global reduction 2 with 2 rules applied. Total rules applied 21 place count 677 transition count 1383
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 2 with 3 rules applied. Total rules applied 24 place count 677 transition count 1380
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 26 place count 675 transition count 1380
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 2 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 4 with 8 rules applied. Total rules applied 34 place count 671 transition count 1376
Free-agglomeration rule (complex) applied 2 times.
Iterating global reduction 4 with 2 rules applied. Total rules applied 36 place count 671 transition count 1374
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 38 place count 669 transition count 1374
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 5 with 1 rules applied. Total rules applied 39 place count 669 transition count 1374
Applied a total of 39 rules in 194 ms. Remains 669 /688 variables (removed 19) and now considering 1374/1393 (removed 19) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 194 ms. Remains : 669/688 places, 1374/1393 transitions.
Incomplete random walk after 10000 steps, including 154 resets, run finished after 196 ms. (steps per millisecond=51 ) properties (out of 16) seen :3
Incomplete Best-First random walk after 10001 steps, including 35 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 29 resets, run finished after 68 ms. (steps per millisecond=147 ) properties (out of 13) seen :1
Incomplete Best-First random walk after 10001 steps, including 30 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 26 resets, run finished after 95 ms. (steps per millisecond=105 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 29 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 27 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10000 steps, including 29 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 30 resets, run finished after 69 ms. (steps per millisecond=144 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10000 steps, including 32 resets, run finished after 151 ms. (steps per millisecond=66 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 31 resets, run finished after 179 ms. (steps per millisecond=55 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 28 resets, run finished after 69 ms. (steps per millisecond=144 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 32 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 12) seen :0
Running SMT prover for 12 properties.
[2023-03-09 05:00:37] [INFO ] Flow matrix only has 1373 transitions (discarded 1 similar events)
// Phase 1: matrix 1373 rows 669 cols
[2023-03-09 05:00:37] [INFO ] Computed 108 place invariants in 11 ms
[2023-03-09 05:00:37] [INFO ] After 182ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:12
[2023-03-09 05:00:38] [INFO ] [Nat]Absence check using 30 positive place invariants in 94 ms returned sat
[2023-03-09 05:00:38] [INFO ] [Nat]Absence check using 30 positive and 78 generalized place invariants in 58 ms returned sat
[2023-03-09 05:00:43] [INFO ] After 5356ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :9
[2023-03-09 05:00:43] [INFO ] State equation strengthened by 32 read => feed constraints.
[2023-03-09 05:00:57] [INFO ] After 13449ms SMT Verify possible using 32 Read/Feed constraints in natural domain returned unsat :3 sat :8
[2023-03-09 05:01:02] [INFO ] After 19167ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :7
Attempting to minimize the solution found.
Minimization took 1 ms.
[2023-03-09 05:01:02] [INFO ] After 25017ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :7
Fused 12 Parikh solutions to 9 different solutions.
Parikh walk visited 0 properties in 928 ms.
Support contains 20 out of 669 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 669/669 places, 1374/1374 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 669 transition count 1373
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 668 transition count 1373
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 4 place count 666 transition count 1371
Ensure Unique test removed 1 places
Iterating global reduction 0 with 3 rules applied. Total rules applied 7 place count 665 transition count 1371
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 8 place count 664 transition count 1370
Iterating global reduction 0 with 1 rules applied. Total rules applied 9 place count 664 transition count 1370
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 10 place count 664 transition count 1369
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 11 place count 663 transition count 1369
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 13 place count 662 transition count 1368
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 2 with 1 rules applied. Total rules applied 14 place count 662 transition count 1367
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 15 place count 661 transition count 1367
Applied a total of 15 rules in 122 ms. Remains 661 /669 variables (removed 8) and now considering 1367/1374 (removed 7) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 122 ms. Remains : 661/669 places, 1367/1374 transitions.
Incomplete random walk after 10000 steps, including 145 resets, run finished after 94 ms. (steps per millisecond=106 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 26 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 25 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 26 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 29 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 31 resets, run finished after 104 ms. (steps per millisecond=96 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 30 resets, run finished after 91 ms. (steps per millisecond=109 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 28 resets, run finished after 117 ms. (steps per millisecond=85 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 29 resets, run finished after 90 ms. (steps per millisecond=111 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 27 resets, run finished after 100 ms. (steps per millisecond=100 ) properties (out of 9) seen :0
Interrupted probabilistic random walk after 159269 steps, run timeout after 3001 ms. (steps per millisecond=53 ) properties seen :{2=1, 3=1, 5=1}
Probabilistic random walk after 159269 steps, saw 49995 distinct states, run finished after 3001 ms. (steps per millisecond=53 ) properties seen :3
Running SMT prover for 6 properties.
[2023-03-09 05:01:07] [INFO ] Flow matrix only has 1366 transitions (discarded 1 similar events)
// Phase 1: matrix 1366 rows 661 cols
[2023-03-09 05:01:07] [INFO ] Computed 107 place invariants in 11 ms
[2023-03-09 05:01:07] [INFO ] After 141ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2023-03-09 05:01:08] [INFO ] [Nat]Absence check using 31 positive place invariants in 10 ms returned sat
[2023-03-09 05:01:08] [INFO ] [Nat]Absence check using 31 positive and 76 generalized place invariants in 103 ms returned sat
[2023-03-09 05:01:12] [INFO ] After 4190ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :6
[2023-03-09 05:01:12] [INFO ] State equation strengthened by 32 read => feed constraints.
[2023-03-09 05:01:22] [INFO ] After 10368ms SMT Verify possible using 32 Read/Feed constraints in natural domain returned unsat :0 sat :5
[2023-03-09 05:01:23] [INFO ] Deduced a trap composed of 23 places in 272 ms of which 9 ms to minimize.
[2023-03-09 05:01:23] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 392 ms
[2023-03-09 05:01:24] [INFO ] Deduced a trap composed of 50 places in 748 ms of which 1 ms to minimize.
[2023-03-09 05:01:24] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 1 trap constraints in 813 ms
[2023-03-09 05:01:26] [INFO ] Deduced a trap composed of 24 places in 519 ms of which 1 ms to minimize.
[2023-03-09 05:01:26] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 1 trap constraints in 569 ms
[2023-03-09 05:01:26] [INFO ] After 14509ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :3
Attempting to minimize the solution found.
Minimization took 1209 ms.
[2023-03-09 05:01:28] [INFO ] After 20252ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :3
Fused 6 Parikh solutions to 4 different solutions.
Parikh walk visited 0 properties in 351 ms.
Support contains 10 out of 661 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 661/661 places, 1367/1367 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 661 transition count 1366
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 660 transition count 1366
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 659 transition count 1358
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 659 transition count 1358
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 5 place count 658 transition count 1358
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 1 with 2 rules applied. Total rules applied 7 place count 657 transition count 1357
Free-agglomeration rule applied 1 times.
Iterating global reduction 1 with 1 rules applied. Total rules applied 8 place count 657 transition count 1356
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 9 place count 656 transition count 1356
Applied a total of 9 rules in 76 ms. Remains 656 /661 variables (removed 5) and now considering 1356/1367 (removed 11) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 76 ms. Remains : 656/661 places, 1356/1367 transitions.
Successfully simplified 59 atomic propositions for a total of 16 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA ASLink-PT-05a-CTLFireability-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ASLink-PT-05a-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ASLink-PT-05a-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ASLink-PT-05a-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 05:01:28] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2023-03-09 05:01:28] [INFO ] Flatten gal took : 68 ms
[2023-03-09 05:01:28] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
FORMULA ASLink-PT-05a-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ASLink-PT-05a-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ASLink-PT-05a-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ASLink-PT-05a-CTLFireability-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 05:01:28] [INFO ] Flatten gal took : 81 ms
[2023-03-09 05:01:28] [INFO ] Input system was already deterministic with 1766 transitions.
Support contains 55 out of 1108 places (down from 104) after GAL structural reductions.
FORMULA ASLink-PT-05a-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 1108/1108 places, 1766/1766 transitions.
Ensure Unique test removed 2 places
Reduce places removed 3 places and 1 transitions.
Discarding 2 places :
Implicit places reduction removed 2 places
Drop transitions removed 145 transitions
Trivial Post-agglo rules discarded 145 transitions
Performed 145 trivial Post agglomeration. Transition count delta: 145
Iterating post reduction 0 with 147 rules applied. Total rules applied 147 place count 1103 transition count 1620
Reduce places removed 150 places and 0 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 152 rules applied. Total rules applied 299 place count 953 transition count 1618
Reduce places removed 2 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 3 rules applied. Total rules applied 302 place count 951 transition count 1617
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 303 place count 950 transition count 1617
Performed 139 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 139 Pre rules applied. Total rules applied 303 place count 950 transition count 1478
Deduced a syphon composed of 139 places in 1 ms
Ensure Unique test removed 43 places
Reduce places removed 182 places and 0 transitions.
Iterating global reduction 4 with 321 rules applied. Total rules applied 624 place count 768 transition count 1478
Discarding 7 places :
Implicit places reduction removed 7 places
Drop transitions removed 17 transitions
Trivial Post-agglo rules discarded 17 transitions
Performed 17 trivial Post agglomeration. Transition count delta: 17
Iterating post reduction 4 with 24 rules applied. Total rules applied 648 place count 761 transition count 1461
Reduce places removed 19 places and 0 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 5 with 21 rules applied. Total rules applied 669 place count 742 transition count 1459
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 6 with 2 rules applied. Total rules applied 671 place count 740 transition count 1459
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 7 with 16 Pre rules applied. Total rules applied 671 place count 740 transition count 1443
Deduced a syphon composed of 16 places in 1 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 7 with 32 rules applied. Total rules applied 703 place count 724 transition count 1443
Discarding 13 places :
Symmetric choice reduction at 7 with 13 rule applications. Total rules 716 place count 711 transition count 1407
Ensure Unique test removed 1 places
Iterating global reduction 7 with 14 rules applied. Total rules applied 730 place count 710 transition count 1407
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Discarding 7 places :
Implicit places reduction removed 7 places
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 7 with 15 rules applied. Total rules applied 745 place count 703 transition count 1399
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 8 with 3 rules applied. Total rules applied 748 place count 700 transition count 1399
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 9 with 1 Pre rules applied. Total rules applied 748 place count 700 transition count 1398
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 750 place count 699 transition count 1398
Discarding 6 places :
Symmetric choice reduction at 9 with 6 rule applications. Total rules 756 place count 693 transition count 1385
Iterating global reduction 9 with 6 rules applied. Total rules applied 762 place count 693 transition count 1385
Discarding 4 places :
Symmetric choice reduction at 9 with 4 rule applications. Total rules 766 place count 689 transition count 1374
Iterating global reduction 9 with 4 rules applied. Total rules applied 770 place count 689 transition count 1374
Discarding 4 places :
Symmetric choice reduction at 9 with 4 rule applications. Total rules 774 place count 685 transition count 1363
Iterating global reduction 9 with 4 rules applied. Total rules applied 778 place count 685 transition count 1363
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 9 with 3 rules applied. Total rules applied 781 place count 685 transition count 1360
Discarding 1 places :
Symmetric choice reduction at 10 with 1 rule applications. Total rules 782 place count 684 transition count 1352
Iterating global reduction 10 with 1 rules applied. Total rules applied 783 place count 684 transition count 1352
Performed 39 Post agglomeration using F-continuation condition.Transition count delta: 39
Deduced a syphon composed of 39 places in 1 ms
Ensure Unique test removed 1 places
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 10 with 79 rules applied. Total rules applied 862 place count 644 transition count 1313
Discarding 4 places :
Symmetric choice reduction at 10 with 4 rule applications. Total rules 866 place count 640 transition count 1309
Iterating global reduction 10 with 4 rules applied. Total rules applied 870 place count 640 transition count 1309
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 10 with 1 rules applied. Total rules applied 871 place count 640 transition count 1308
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 872 place count 639 transition count 1308
Applied a total of 872 rules in 239 ms. Remains 639 /1108 variables (removed 469) and now considering 1308/1766 (removed 458) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 240 ms. Remains : 639/1108 places, 1308/1766 transitions.
[2023-03-09 05:01:29] [INFO ] Flatten gal took : 44 ms
[2023-03-09 05:01:29] [INFO ] Flatten gal took : 46 ms
[2023-03-09 05:01:29] [INFO ] Input system was already deterministic with 1308 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1108/1108 places, 1766/1766 transitions.
Ensure Unique test removed 2 places
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 1104 transition count 1766
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 1096 transition count 1735
Ensure Unique test removed 1 places
Iterating global reduction 1 with 9 rules applied. Total rules applied 21 place count 1095 transition count 1735
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 22 place count 1095 transition count 1734
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 26 place count 1091 transition count 1723
Iterating global reduction 2 with 4 rules applied. Total rules applied 30 place count 1091 transition count 1723
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 31 place count 1090 transition count 1722
Iterating global reduction 2 with 1 rules applied. Total rules applied 32 place count 1090 transition count 1722
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 33 place count 1089 transition count 1721
Iterating global reduction 2 with 1 rules applied. Total rules applied 34 place count 1089 transition count 1721
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 35 place count 1088 transition count 1720
Iterating global reduction 2 with 1 rules applied. Total rules applied 36 place count 1088 transition count 1720
Applied a total of 36 rules in 313 ms. Remains 1088 /1108 variables (removed 20) and now considering 1720/1766 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 314 ms. Remains : 1088/1108 places, 1720/1766 transitions.
[2023-03-09 05:01:29] [INFO ] Flatten gal took : 68 ms
[2023-03-09 05:01:29] [INFO ] Flatten gal took : 63 ms
[2023-03-09 05:01:30] [INFO ] Input system was already deterministic with 1720 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1108/1108 places, 1766/1766 transitions.
Ensure Unique test removed 2 places
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 1104 transition count 1766
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 1096 transition count 1735
Ensure Unique test removed 1 places
Iterating global reduction 1 with 9 rules applied. Total rules applied 21 place count 1095 transition count 1735
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 22 place count 1095 transition count 1734
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 26 place count 1091 transition count 1723
Iterating global reduction 2 with 4 rules applied. Total rules applied 30 place count 1091 transition count 1723
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 32 place count 1089 transition count 1714
Iterating global reduction 2 with 2 rules applied. Total rules applied 34 place count 1089 transition count 1714
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 36 place count 1087 transition count 1705
Iterating global reduction 2 with 2 rules applied. Total rules applied 38 place count 1087 transition count 1705
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 40 place count 1085 transition count 1696
Iterating global reduction 2 with 2 rules applied. Total rules applied 42 place count 1085 transition count 1696
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 43 place count 1084 transition count 1688
Iterating global reduction 2 with 1 rules applied. Total rules applied 44 place count 1084 transition count 1688
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 45 place count 1083 transition count 1680
Iterating global reduction 2 with 1 rules applied. Total rules applied 46 place count 1083 transition count 1680
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 47 place count 1082 transition count 1672
Iterating global reduction 2 with 1 rules applied. Total rules applied 48 place count 1082 transition count 1672
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 49 place count 1081 transition count 1664
Iterating global reduction 2 with 1 rules applied. Total rules applied 50 place count 1081 transition count 1664
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 51 place count 1080 transition count 1656
Iterating global reduction 2 with 1 rules applied. Total rules applied 52 place count 1080 transition count 1656
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 53 place count 1079 transition count 1648
Iterating global reduction 2 with 1 rules applied. Total rules applied 54 place count 1079 transition count 1648
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 55 place count 1078 transition count 1640
Iterating global reduction 2 with 1 rules applied. Total rules applied 56 place count 1078 transition count 1640
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 57 place count 1077 transition count 1632
Iterating global reduction 2 with 1 rules applied. Total rules applied 58 place count 1077 transition count 1632
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 59 place count 1076 transition count 1624
Iterating global reduction 2 with 1 rules applied. Total rules applied 60 place count 1076 transition count 1624
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 61 place count 1075 transition count 1616
Iterating global reduction 2 with 1 rules applied. Total rules applied 62 place count 1075 transition count 1616
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 63 place count 1074 transition count 1608
Iterating global reduction 2 with 1 rules applied. Total rules applied 64 place count 1074 transition count 1608
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 65 place count 1073 transition count 1600
Iterating global reduction 2 with 1 rules applied. Total rules applied 66 place count 1073 transition count 1600
Applied a total of 66 rules in 467 ms. Remains 1073 /1108 variables (removed 35) and now considering 1600/1766 (removed 166) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 467 ms. Remains : 1073/1108 places, 1600/1766 transitions.
[2023-03-09 05:01:30] [INFO ] Flatten gal took : 116 ms
[2023-03-09 05:01:30] [INFO ] Flatten gal took : 74 ms
[2023-03-09 05:01:30] [INFO ] Input system was already deterministic with 1600 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1108/1108 places, 1766/1766 transitions.
Ensure Unique test removed 2 places
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 1104 transition count 1766
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 1096 transition count 1735
Ensure Unique test removed 1 places
Iterating global reduction 1 with 9 rules applied. Total rules applied 21 place count 1095 transition count 1735
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 22 place count 1095 transition count 1734
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 26 place count 1091 transition count 1723
Iterating global reduction 2 with 4 rules applied. Total rules applied 30 place count 1091 transition count 1723
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 31 place count 1090 transition count 1722
Iterating global reduction 2 with 1 rules applied. Total rules applied 32 place count 1090 transition count 1722
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 33 place count 1089 transition count 1721
Iterating global reduction 2 with 1 rules applied. Total rules applied 34 place count 1089 transition count 1721
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 35 place count 1088 transition count 1720
Iterating global reduction 2 with 1 rules applied. Total rules applied 36 place count 1088 transition count 1720
Applied a total of 36 rules in 142 ms. Remains 1088 /1108 variables (removed 20) and now considering 1720/1766 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 142 ms. Remains : 1088/1108 places, 1720/1766 transitions.
[2023-03-09 05:01:31] [INFO ] Flatten gal took : 60 ms
[2023-03-09 05:01:31] [INFO ] Flatten gal took : 105 ms
[2023-03-09 05:01:31] [INFO ] Input system was already deterministic with 1720 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1108/1108 places, 1766/1766 transitions.
Ensure Unique test removed 2 places
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 1104 transition count 1766
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 1096 transition count 1735
Ensure Unique test removed 1 places
Iterating global reduction 1 with 9 rules applied. Total rules applied 21 place count 1095 transition count 1735
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 22 place count 1095 transition count 1734
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 26 place count 1091 transition count 1723
Iterating global reduction 2 with 4 rules applied. Total rules applied 30 place count 1091 transition count 1723
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 32 place count 1089 transition count 1714
Iterating global reduction 2 with 2 rules applied. Total rules applied 34 place count 1089 transition count 1714
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 36 place count 1087 transition count 1705
Iterating global reduction 2 with 2 rules applied. Total rules applied 38 place count 1087 transition count 1705
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 40 place count 1085 transition count 1696
Iterating global reduction 2 with 2 rules applied. Total rules applied 42 place count 1085 transition count 1696
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 43 place count 1084 transition count 1688
Iterating global reduction 2 with 1 rules applied. Total rules applied 44 place count 1084 transition count 1688
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 45 place count 1083 transition count 1680
Iterating global reduction 2 with 1 rules applied. Total rules applied 46 place count 1083 transition count 1680
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 47 place count 1082 transition count 1672
Iterating global reduction 2 with 1 rules applied. Total rules applied 48 place count 1082 transition count 1672
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 49 place count 1081 transition count 1664
Iterating global reduction 2 with 1 rules applied. Total rules applied 50 place count 1081 transition count 1664
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 51 place count 1080 transition count 1656
Iterating global reduction 2 with 1 rules applied. Total rules applied 52 place count 1080 transition count 1656
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 53 place count 1079 transition count 1648
Iterating global reduction 2 with 1 rules applied. Total rules applied 54 place count 1079 transition count 1648
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 55 place count 1078 transition count 1640
Iterating global reduction 2 with 1 rules applied. Total rules applied 56 place count 1078 transition count 1640
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 57 place count 1077 transition count 1632
Iterating global reduction 2 with 1 rules applied. Total rules applied 58 place count 1077 transition count 1632
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 59 place count 1076 transition count 1624
Iterating global reduction 2 with 1 rules applied. Total rules applied 60 place count 1076 transition count 1624
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 61 place count 1075 transition count 1616
Iterating global reduction 2 with 1 rules applied. Total rules applied 62 place count 1075 transition count 1616
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 63 place count 1074 transition count 1608
Iterating global reduction 2 with 1 rules applied. Total rules applied 64 place count 1074 transition count 1608
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 65 place count 1073 transition count 1600
Iterating global reduction 2 with 1 rules applied. Total rules applied 66 place count 1073 transition count 1600
Applied a total of 66 rules in 454 ms. Remains 1073 /1108 variables (removed 35) and now considering 1600/1766 (removed 166) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 454 ms. Remains : 1073/1108 places, 1600/1766 transitions.
[2023-03-09 05:01:31] [INFO ] Flatten gal took : 45 ms
[2023-03-09 05:01:31] [INFO ] Flatten gal took : 48 ms
[2023-03-09 05:01:32] [INFO ] Input system was already deterministic with 1600 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1108/1108 places, 1766/1766 transitions.
Ensure Unique test removed 2 places
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 1104 transition count 1766
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 1096 transition count 1735
Ensure Unique test removed 1 places
Iterating global reduction 1 with 9 rules applied. Total rules applied 21 place count 1095 transition count 1735
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 22 place count 1095 transition count 1734
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 26 place count 1091 transition count 1723
Iterating global reduction 2 with 4 rules applied. Total rules applied 30 place count 1091 transition count 1723
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 32 place count 1089 transition count 1714
Iterating global reduction 2 with 2 rules applied. Total rules applied 34 place count 1089 transition count 1714
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 36 place count 1087 transition count 1705
Iterating global reduction 2 with 2 rules applied. Total rules applied 38 place count 1087 transition count 1705
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 40 place count 1085 transition count 1696
Iterating global reduction 2 with 2 rules applied. Total rules applied 42 place count 1085 transition count 1696
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 43 place count 1084 transition count 1688
Iterating global reduction 2 with 1 rules applied. Total rules applied 44 place count 1084 transition count 1688
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 45 place count 1083 transition count 1680
Iterating global reduction 2 with 1 rules applied. Total rules applied 46 place count 1083 transition count 1680
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 47 place count 1082 transition count 1672
Iterating global reduction 2 with 1 rules applied. Total rules applied 48 place count 1082 transition count 1672
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 49 place count 1081 transition count 1664
Iterating global reduction 2 with 1 rules applied. Total rules applied 50 place count 1081 transition count 1664
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 51 place count 1080 transition count 1656
Iterating global reduction 2 with 1 rules applied. Total rules applied 52 place count 1080 transition count 1656
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 53 place count 1079 transition count 1648
Iterating global reduction 2 with 1 rules applied. Total rules applied 54 place count 1079 transition count 1648
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 55 place count 1078 transition count 1640
Iterating global reduction 2 with 1 rules applied. Total rules applied 56 place count 1078 transition count 1640
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 57 place count 1077 transition count 1632
Iterating global reduction 2 with 1 rules applied. Total rules applied 58 place count 1077 transition count 1632
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 59 place count 1076 transition count 1624
Iterating global reduction 2 with 1 rules applied. Total rules applied 60 place count 1076 transition count 1624
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 61 place count 1075 transition count 1616
Iterating global reduction 2 with 1 rules applied. Total rules applied 62 place count 1075 transition count 1616
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 63 place count 1074 transition count 1608
Iterating global reduction 2 with 1 rules applied. Total rules applied 64 place count 1074 transition count 1608
Applied a total of 64 rules in 413 ms. Remains 1074 /1108 variables (removed 34) and now considering 1608/1766 (removed 158) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 413 ms. Remains : 1074/1108 places, 1608/1766 transitions.
[2023-03-09 05:01:32] [INFO ] Flatten gal took : 49 ms
[2023-03-09 05:01:32] [INFO ] Flatten gal took : 50 ms
[2023-03-09 05:01:32] [INFO ] Input system was already deterministic with 1608 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1108/1108 places, 1766/1766 transitions.
Ensure Unique test removed 2 places
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 1104 transition count 1766
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 1096 transition count 1735
Ensure Unique test removed 1 places
Iterating global reduction 1 with 9 rules applied. Total rules applied 21 place count 1095 transition count 1735
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 22 place count 1095 transition count 1734
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 26 place count 1091 transition count 1723
Iterating global reduction 2 with 4 rules applied. Total rules applied 30 place count 1091 transition count 1723
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 32 place count 1089 transition count 1714
Iterating global reduction 2 with 2 rules applied. Total rules applied 34 place count 1089 transition count 1714
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 36 place count 1087 transition count 1705
Iterating global reduction 2 with 2 rules applied. Total rules applied 38 place count 1087 transition count 1705
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 40 place count 1085 transition count 1696
Iterating global reduction 2 with 2 rules applied. Total rules applied 42 place count 1085 transition count 1696
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 43 place count 1084 transition count 1688
Iterating global reduction 2 with 1 rules applied. Total rules applied 44 place count 1084 transition count 1688
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 45 place count 1083 transition count 1680
Iterating global reduction 2 with 1 rules applied. Total rules applied 46 place count 1083 transition count 1680
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 47 place count 1082 transition count 1672
Iterating global reduction 2 with 1 rules applied. Total rules applied 48 place count 1082 transition count 1672
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 49 place count 1081 transition count 1664
Iterating global reduction 2 with 1 rules applied. Total rules applied 50 place count 1081 transition count 1664
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 51 place count 1080 transition count 1656
Iterating global reduction 2 with 1 rules applied. Total rules applied 52 place count 1080 transition count 1656
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 53 place count 1079 transition count 1648
Iterating global reduction 2 with 1 rules applied. Total rules applied 54 place count 1079 transition count 1648
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 55 place count 1078 transition count 1640
Iterating global reduction 2 with 1 rules applied. Total rules applied 56 place count 1078 transition count 1640
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 57 place count 1077 transition count 1632
Iterating global reduction 2 with 1 rules applied. Total rules applied 58 place count 1077 transition count 1632
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 59 place count 1076 transition count 1624
Iterating global reduction 2 with 1 rules applied. Total rules applied 60 place count 1076 transition count 1624
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 61 place count 1075 transition count 1616
Iterating global reduction 2 with 1 rules applied. Total rules applied 62 place count 1075 transition count 1616
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 63 place count 1074 transition count 1608
Iterating global reduction 2 with 1 rules applied. Total rules applied 64 place count 1074 transition count 1608
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 65 place count 1073 transition count 1600
Iterating global reduction 2 with 1 rules applied. Total rules applied 66 place count 1073 transition count 1600
Applied a total of 66 rules in 417 ms. Remains 1073 /1108 variables (removed 35) and now considering 1600/1766 (removed 166) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 417 ms. Remains : 1073/1108 places, 1600/1766 transitions.
[2023-03-09 05:01:33] [INFO ] Flatten gal took : 42 ms
[2023-03-09 05:01:33] [INFO ] Flatten gal took : 85 ms
[2023-03-09 05:01:33] [INFO ] Input system was already deterministic with 1600 transitions.
[2023-03-09 05:01:33] [INFO ] Flatten gal took : 50 ms
[2023-03-09 05:01:33] [INFO ] Flatten gal took : 51 ms
[2023-03-09 05:01:33] [INFO ] Export to MCC of 7 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-09 05:01:33] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1108 places, 1766 transitions and 6377 arcs took 7 ms.
Total runtime 128522 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ASLink-PT-05a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/377
CTLFireability
FORMULA ASLink-PT-05a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393220 kB
MemFree: 14472116 kB
After kill :
MemTotal: 16393220 kB
MemFree: 16101956 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/377/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/377/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/377/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 13 (type CNST) for 12 ASLink-PT-05a-CTLFireability-10
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 13 (type CNST) for ASLink-PT-05a-CTLFireability-10
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 19 (type EXCL) for 18 ASLink-PT-05a-CTLFireability-12
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
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ASLink-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-05a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ASLink-PT-05a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595000074"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-05a.tgz
mv ASLink-PT-05a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;