Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r006-oct2-167813594000202.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is AirplaneLD-COL-0200, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r006-oct2-167813594000202
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 7.8K Feb 26 11:31 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 26 11:31 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 26 11:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 26 11:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 11:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 122K Feb 26 11:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 26 11:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 65K Feb 26 11:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 67K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-00
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-01
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-02
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-03
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-04
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-05
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-06
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-07
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-08
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-09
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-10
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-11
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-12
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-13
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-14
FORMULA_NAME AirplaneLD-COL-0200-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678287138769

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-COL-0200
Not applying reductions.
Model is COL
CTLFireability PT
[2023-03-08 14:52:20] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, CTLFireability, --reduce-single, STATESPACE]
[2023-03-08 14:52:20] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-08 14:52:21] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-08 14:52:21] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-08 14:52:21] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 815 ms
[2023-03-08 14:52:21] [INFO ] Detected 3 constant HL places corresponding to 602 PT places.
[2023-03-08 14:52:21] [INFO ] Imported 20 HL places and 15 HL transitions for a total of 1419 PT places and 2412.0 transition bindings in 19 ms.
Parsed 16 properties from file ./CTLFireability.xml in 11 ms.
[2023-03-08 14:52:21] [INFO ] Unfolded HLPN to a Petri net with 1419 places and 1608 transitions 4520 arcs in 41 ms.
[2023-03-08 14:52:21] [INFO ] Unfolded 16 HLPN properties in 2 ms.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 399 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 399 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 399 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 399 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 399 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 399 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:52:21] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:52:22] [INFO ] Export to MCC of 16 properties in file ./CTLFireability.STATESPACE.xml took 34 ms.
[2023-03-08 14:52:22] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 1419 places, 1608 transitions and 4520 arcs took 6 ms.
Total runtime 1142 ms.
starting LoLA
BK_INPUT AirplaneLD-COL-0200
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfCTLFireability

FORMULA AirplaneLD-COL-0200-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-COL-0200-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678287476482

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfCTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfCTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfCTLFireability/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 74 (type EXCL) for 13 AirplaneLD-COL-0200-CTLFireability-03
lola: time limit : 85 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 72 (type FNDP) for 13 AirplaneLD-COL-0200-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type EQUN) for 13 AirplaneLD-COL-0200-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 75 (type SRCH) for 13 AirplaneLD-COL-0200-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 75 (type SRCH) for AirplaneLD-COL-0200-CTLFireability-03
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 74 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-03
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 72 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-03 (obsolete)
lola: CANCELED task # 73 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-03 (obsolete)
lola: Created skeleton in 1.000000 secs.
lola: FINISHED task # 72 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-03
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-73.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 73 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-03
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 78 (type EXCL) for 44 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 98 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 76 (type FNDP) for 44 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type EQUN) for 44 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SRCH) for 44 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 79 (type SRCH) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 78 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 76 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-12 (obsolete)
lola: CANCELED task # 77 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-12 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 82 (type EXCL) for 44 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 107 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 80 (type FNDP) for 44 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type EQUN) for 44 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 83 (type SRCH) for 44 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 76 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 82 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 80 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-12 (obsolete)
lola: CANCELED task # 81 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-12 (obsolete)
lola: CANCELED task # 83 (type SRCH) for AirplaneLD-COL-0200-CTLFireability-12 (obsolete)
lola: FINISHED task # 83 (type SRCH) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-77.sara.

lola: FINISHED task # 77 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : true
lola: FINISHED task # 80 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-81.sara.

lola: FINISHED task # 81 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : true
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 26 (type EXCL) for 25 AirplaneLD-COL-0200-CTLFireability-07
lola: time limit : 122 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 85 (type FNDP) for 41 AirplaneLD-COL-0200-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type EQUN) for 41 AirplaneLD-COL-0200-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type SRCH) for 41 AirplaneLD-COL-0200-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 88 (type SRCH) for AirplaneLD-COL-0200-CTLFireability-11
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 85 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-11
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: CANCELED task # 86 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-11 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-86.sara.
lola: sara: place or transition ordering is non-deterministic
rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 1.000000 secs.
lola: LAUNCH task # 89 (type FNDP) for 65 AirplaneLD-COL-0200-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type EQUN) for 65 AirplaneLD-COL-0200-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 92 (type SRCH) for 65 AirplaneLD-COL-0200-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 92 (type SRCH) for AirplaneLD-COL-0200-CTLFireability-15
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1

lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:665
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:665
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 86 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-11
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 90 (type EQUN) for AirplaneLD-COL-0200-CTLFireability-15
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 2 0 0 10 0 0 8
AirplaneLD-COL-0200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-15: DISJ 0 2 1 0 4 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 3/190 2/32 AirplaneLD-COL-0200-CTLFireability-07 180612 m, 36122 m/sec, 437433 t fired, .
89 EF FNDP 2/3434 0/5 AirplaneLD-COL-0200-CTLFireability-15 109825 t fired, 36609 attempts, .

Time elapsed: 168 secs. Pages in use: 2
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 2 0 0 10 0 0 8
AirplaneLD-COL-0200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-15: DISJ 0 2 1 0 4 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 8/190 7/32 AirplaneLD-COL-0200-CTLFireability-07 533888 m, 70655 m/sec, 1300349 t fired, .
89 EF FNDP 7/3434 0/5 AirplaneLD-COL-0200-CTLFireability-15 390007 t fired, 130003 attempts, .

Time elapsed: 173 secs. Pages in use: 7
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 2 0 0 10 0 0 8
AirplaneLD-COL-0200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-15: DISJ 0 2 1 0 4 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 13/190 11/32 AirplaneLD-COL-0200-CTLFireability-07 724771 m, 38176 m/sec, 2074380 t fired, .
89 EF FNDP 12/3434 0/5 AirplaneLD-COL-0200-CTLFireability-15 668710 t fired, 222904 attempts, .

Time elapsed: 178 secs. Pages in use: 11
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 2 0 0 10 0 0 8
AirplaneLD-COL-0200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-15: DISJ 0 2 1 0 4 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 18/190 11/32 AirplaneLD-COL-0200-CTLFireability-07 726591 m, 364 m/sec, 2807171 t fired, .
89 EF FNDP 17/3434 0/5 AirplaneLD-COL-0200-CTLFireability-15 947902 t fired, 315968 attempts, .

Time elapsed: 183 secs. Pages in use: 11
# running tasks: 2 of 4 Visible: 16
lola: FINISHED task # 26 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-07
lola: result : true
lola: markings : 727622
lola: fired transitions : 3225680
lola: time used : 20.000000
lola: memory pages used : 11
lola: LAUNCH task # 68 (type EXCL) for 65 AirplaneLD-COL-0200-CTLFireability-15
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 68 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-15
lola: result : true
lola: markings : 11
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 89 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-15 (obsolete)
lola: LAUNCH task # 63 (type EXCL) for 62 AirplaneLD-COL-0200-CTLFireability-14
lola: time limit : 227 sec
lola: memory limit: 32 pages
lola: FINISHED task # 89 (type FNDP) for AirplaneLD-COL-0200-CTLFireability-15
lola: result : unknown
lola: fired transitions : 1092325
lola: tried executions : 364110
lola: time used : 19.000000
lola: memory pages used : 0
lola: FINISHED task # 63 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-14
lola: result : true
lola: markings : 1426
lola: fired transitions : 1437
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 60 (type EXCL) for 59 AirplaneLD-COL-0200-CTLFireability-13
lola: time limit : 243 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-13
lola: result : true
lola: markings : 9
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 44 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 262 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 1 0 10 0 0 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 3/262 5/32 AirplaneLD-COL-0200-CTLFireability-12 337035 m, 67407 m/sec, 411436 t fired, .

Time elapsed: 188 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 1 0 10 0 0 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 8/262 12/32 AirplaneLD-COL-0200-CTLFireability-12 864667 m, 105526 m/sec, 1296269 t fired, .

Time elapsed: 193 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 1 0 10 0 0 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 13/262 21/32 AirplaneLD-COL-0200-CTLFireability-12 1453140 m, 117694 m/sec, 2169672 t fired, .

Time elapsed: 198 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 1 0 10 0 0 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 18/262 28/32 AirplaneLD-COL-0200-CTLFireability-12 2014048 m, 112181 m/sec, 3061250 t fired, .

Time elapsed: 203 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 47 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 208 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 37 (type EXCL) for 34 AirplaneLD-COL-0200-CTLFireability-10
lola: time limit : 282 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-10
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 AirplaneLD-COL-0200-CTLFireability-09
lola: time limit : 339 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-09
lola: result : true
lola: markings : 11
lola: fired transitions : 23
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 AirplaneLD-COL-0200-CTLFireability-08
lola: time limit : 376 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-08
lola: result : false
lola: markings : 8588
lola: fired transitions : 37249
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 AirplaneLD-COL-0200-CTLFireability-06
lola: time limit : 423 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-06
lola: result : true
lola: markings : 11
lola: fired transitions : 49
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 AirplaneLD-COL-0200-CTLFireability-04
lola: time limit : 484 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-04
lola: result : false
lola: markings : 6609
lola: fired transitions : 7209
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 6 AirplaneLD-COL-0200-CTLFireability-02
lola: time limit : 565 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 4/565 2/32 AirplaneLD-COL-0200-CTLFireability-02 175919 m, 35183 m/sec, 632149 t fired, .

Time elapsed: 213 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 9/565 6/32 AirplaneLD-COL-0200-CTLFireability-02 421303 m, 49076 m/sec, 1517481 t fired, .

Time elapsed: 218 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 14/565 10/32 AirplaneLD-COL-0200-CTLFireability-02 667507 m, 49240 m/sec, 2404999 t fired, .

Time elapsed: 223 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 19/565 11/32 AirplaneLD-COL-0200-CTLFireability-02 727457 m, 11990 m/sec, 3312934 t fired, .

Time elapsed: 228 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 11 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-02
lola: result : true
lola: markings : 727621
lola: fired transitions : 3349866
lola: time used : 19.000000
lola: memory pages used : 11
lola: LAUNCH task # 4 (type EXCL) for 3 AirplaneLD-COL-0200-CTLFireability-01
lola: time limit : 843 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/843 4/32 AirplaneLD-COL-0200-CTLFireability-01 311321 m, 62264 m/sec, 758980 t fired, .

Time elapsed: 233 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/843 9/32 AirplaneLD-COL-0200-CTLFireability-01 633494 m, 64434 m/sec, 1543706 t fired, .

Time elapsed: 238 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/843 11/32 AirplaneLD-COL-0200-CTLFireability-01 727224 m, 18746 m/sec, 2415230 t fired, .

Time elapsed: 243 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/843 14/32 AirplaneLD-COL-0200-CTLFireability-01 1038866 m, 62328 m/sec, 3266708 t fired, .

Time elapsed: 248 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/843 20/32 AirplaneLD-COL-0200-CTLFireability-01 1386712 m, 69569 m/sec, 4122412 t fired, .

Time elapsed: 253 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/843 21/32 AirplaneLD-COL-0200-CTLFireability-01 1482553 m, 19168 m/sec, 5041933 t fired, .

Time elapsed: 258 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/843 25/32 AirplaneLD-COL-0200-CTLFireability-01 1825489 m, 68587 m/sec, 5890128 t fired, .

Time elapsed: 263 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/843 30/32 AirplaneLD-COL-0200-CTLFireability-01 2098761 m, 54654 m/sec, 6748524 t fired, .

Time elapsed: 268 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/843 31/32 AirplaneLD-COL-0200-CTLFireability-01 2259450 m, 32137 m/sec, 7644068 t fired, .

Time elapsed: 273 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 1 0 0 10 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 278 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 84 (type EXCL) for 44 AirplaneLD-COL-0200-CTLFireability-12
lola: time limit : 1107 sec
lola: memory limit: 32 pages
lola: FINISHED task # 84 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-12
lola: result : false
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 AirplaneLD-COL-0200-CTLFireability-05
lola: time limit : 1661 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-05
lola: result : false
lola: markings : 10
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 AirplaneLD-COL-0200-CTLFireability-00
lola: time limit : 3322 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/3322 3/32 AirplaneLD-COL-0200-CTLFireability-00 249736 m, 49947 m/sec, 804429 t fired, .

Time elapsed: 283 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/3322 8/32 AirplaneLD-COL-0200-CTLFireability-00 564707 m, 62994 m/sec, 1664307 t fired, .

Time elapsed: 288 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/3322 11/32 AirplaneLD-COL-0200-CTLFireability-00 726275 m, 32313 m/sec, 2536612 t fired, .

Time elapsed: 293 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/3322 13/32 AirplaneLD-COL-0200-CTLFireability-00 896993 m, 34143 m/sec, 3417278 t fired, .

Time elapsed: 298 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/3322 17/32 AirplaneLD-COL-0200-CTLFireability-00 1200821 m, 60765 m/sec, 4300596 t fired, .

Time elapsed: 303 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/3322 20/32 AirplaneLD-COL-0200-CTLFireability-00 1412912 m, 42418 m/sec, 5210077 t fired, .

Time elapsed: 308 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/3322 22/32 AirplaneLD-COL-0200-CTLFireability-00 1573226 m, 32062 m/sec, 6096085 t fired, .

Time elapsed: 313 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/3322 26/32 AirplaneLD-COL-0200-CTLFireability-00 1873427 m, 60040 m/sec, 6978811 t fired, .

Time elapsed: 318 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/3322 30/32 AirplaneLD-COL-0200-CTLFireability-00 2099598 m, 45234 m/sec, 7891005 t fired, .

Time elapsed: 323 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/3322 31/32 AirplaneLD-COL-0200-CTLFireability-00 2248054 m, 29691 m/sec, 8768953 t fired, .

Time elapsed: 328 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for AirplaneLD-COL-0200-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0200-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-COL-0200-CTLFireability-12: CONJ 0 0 0 0 11 0 1 8

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 333 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0200-CTLFireability-00: CTL unknown AGGR
AirplaneLD-COL-0200-CTLFireability-01: CTL unknown AGGR
AirplaneLD-COL-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-03: EF true state space
AirplaneLD-COL-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-06: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-COL-0200-CTLFireability-09: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-10: DISJ true CTL model checker
AirplaneLD-COL-0200-CTLFireability-11: EF true findpath
AirplaneLD-COL-0200-CTLFireability-12: CONJ unknown CONJ
AirplaneLD-COL-0200-CTLFireability-13: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-COL-0200-CTLFireability-15: DISJ true CTL model checker


Time elapsed: 333 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0200"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0200, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r006-oct2-167813594000202"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0200.tgz
mv AirplaneLD-COL-0200 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;