About the Execution of LoLA for AirplaneLD-COL-0020
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1051.892 | 15894.00 | 33979.00 | 74.30 | FTTFTTFFTFTFFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r006-oct2-167813593900178.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is AirplaneLD-COL-0020, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r006-oct2-167813593900178
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 528K
-rw-r--r-- 1 mcc users 8.2K Feb 26 11:14 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 26 11:14 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 26 11:12 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K Feb 26 11:12 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 11:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 122K Feb 26 11:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K Feb 26 11:17 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 87K Feb 26 11:17 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 41K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-00
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-01
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-02
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-03
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-04
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-05
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-06
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-07
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-08
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-09
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-10
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-11
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-12
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-13
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-14
FORMULA_NAME AirplaneLD-COL-0020-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678286509376
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-COL-0020
Not applying reductions.
Model is COL
CTLFireability PT
[2023-03-08 14:41:52] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, CTLFireability, --reduce-single, STATESPACE]
[2023-03-08 14:41:52] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-08 14:41:52] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-08 14:41:53] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-08 14:41:53] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 764 ms
[2023-03-08 14:41:53] [INFO ] Detected 3 constant HL places corresponding to 62 PT places.
[2023-03-08 14:41:53] [INFO ] Imported 20 HL places and 15 HL transitions for a total of 159 PT places and 252.0 transition bindings in 16 ms.
Parsed 16 properties from file ./CTLFireability.xml in 11 ms.
[2023-03-08 14:41:53] [INFO ] Unfolded HLPN to a Petri net with 159 places and 168 transitions 470 arcs in 25 ms.
[2023-03-08 14:41:53] [INFO ] Unfolded 16 HLPN properties in 0 ms.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 39 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 39 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 39 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:41:53] [INFO ] Export to MCC of 16 properties in file ./CTLFireability.STATESPACE.xml took 23 ms.
[2023-03-08 14:41:53] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 159 places, 168 transitions and 470 arcs took 3 ms.
Total runtime 1117 ms.
starting LoLA
BK_INPUT AirplaneLD-COL-0020
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfCTLFireability
FORMULA AirplaneLD-COL-0020-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678286525270
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfCTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfCTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfCTLFireability/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 70 (type SKEL/FNDP) for 0 AirplaneLD-COL-0020-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SKEL/EQUN) for 0 AirplaneLD-COL-0020-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 72 (type SKEL/SRCH) for 0 AirplaneLD-COL-0020-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 73 (type SKEL/SRCH) for 0 AirplaneLD-COL-0020-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 70 (type SKEL/FNDP) for AirplaneLD-COL-0020-CTLFireability-00
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 71 (type EQUN) for AirplaneLD-COL-0020-CTLFireability-00 (obsolete)
lola: CANCELED task # 72 (type SRCH) for AirplaneLD-COL-0020-CTLFireability-00 (obsolete)
lola: CANCELED task # 73 (type SRCH) for AirplaneLD-COL-0020-CTLFireability-00 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-71.sara.
lola: LAUNCH task # 75 (type SKEL/FNDP) for 16 AirplaneLD-COL-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type SKEL/EQUN) for 16 AirplaneLD-COL-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SKEL/SRCH) for 16 AirplaneLD-COL-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type SKEL/SRCH) for 16 AirplaneLD-COL-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 77 (type SKEL/SRCH) for AirplaneLD-COL-0020-CTLFireability-04
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 75 (type FNDP) for AirplaneLD-COL-0020-CTLFireability-04 (obsolete)
lola: CANCELED task # 76 (type EQUN) for AirplaneLD-COL-0020-CTLFireability-04 (obsolete)
lola: CANCELED task # 78 (type SRCH) for AirplaneLD-COL-0020-CTLFireability-04 (obsolete)
lola: FINISHED task # 78 (type SKEL/SRCH) for AirplaneLD-COL-0020-CTLFireability-04
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 71 (type SKEL/EQUN) for AirplaneLD-COL-0020-CTLFireability-00
lola: NOTDEADLOCKFREE
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-76.sara.
lola: result : true
lola: LAUNCH task # 79 (type SKEL/SRCH) for 30 AirplaneLD-COL-0020-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 75 (type SKEL/FNDP) for AirplaneLD-COL-0020-CTLFireability-04
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 79 (type SKEL/SRCH) for AirplaneLD-COL-0020-CTLFireability-06
lola: result : false
lola: markings : 47
lola: fired transitions : 46
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 76 (type SKEL/EQUN) for AirplaneLD-COL-0020-CTLFireability-04
lola: result : true
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 8 (type EXCL) for 7 AirplaneLD-COL-0020-CTLFireability-01
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: RELEASE
lola: LAUNCH task # 82 (type SKEL/SRCH) for 36 AirplaneLD-COL-0020-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 82 (type SKEL/SRCH) for AirplaneLD-COL-0020-CTLFireability-08
lola: result : false
lola: markings : 79
lola: fired transitions : 159
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: planning for AirplaneLD-COL-0020-CTLFireability-06 stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 86 (type FNDP) for 48 AirplaneLD-COL-0020-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type EQUN) for 48 AirplaneLD-COL-0020-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 89 (type SRCH) for 48 AirplaneLD-COL-0020-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 89 (type SRCH) for AirplaneLD-COL-0020-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 95 (type FNDP) for 0 AirplaneLD-COL-0020-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 86 (type FNDP) for AirplaneLD-COL-0020-CTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 87 (type EQUN) for AirplaneLD-COL-0020-CTLFireability-12 (obsolete)
lola: LAUNCH task # 90 (type FNDP) for 59 AirplaneLD-COL-0020-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 91 (type EQUN) for 59 AirplaneLD-COL-0020-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 95 (type FNDP) for AirplaneLD-COL-0020-CTLFireability-00
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 93 (type SRCH) for 59 AirplaneLD-COL-0020-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 93 (type SRCH) for AirplaneLD-COL-0020-CTLFireability-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 90 (type FNDP) for AirplaneLD-COL-0020-CTLFireability-13
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 91 (type EQUN) for AirplaneLD-COL-0020-CTLFireability-13 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 101 (type SKEL/FNDP) for 48 AirplaneLD-COL-0020-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 102 (type SKEL/EQUN) for 48 AirplaneLD-COL-0020-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type SKEL/SRCH) for 48 AirplaneLD-COL-0020-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 103 (type SKEL/SRCH) for AirplaneLD-COL-0020-CTLFireability-12
lola: result : true
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 101 (type FNDP) for AirplaneLD-COL-0020-CTLFireability-12 (obsolete)
lola: CANCELED task # 102 (type EQUN) for AirplaneLD-COL-0020-CTLFireability-12 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-102.sara.
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 105 (type FNDP) for 16 AirplaneLD-COL-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 106 (type EQUN) for 16 AirplaneLD-COL-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 108 (type SRCH) for 16 AirplaneLD-COL-0020-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 101 (type SKEL/FNDP) for AirplaneLD-COL-0020-CTLFireability-12
lola: result : true
lola: fired transitions : 8
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-106.sara.
sara: error: :5: error: syntax error, unexpected $end, expecting KEY_TRANSITION
sara: error while reading Petri net from file -- aborting [#04]
sara: see manual for a documentation of this error
sara: last error message: No such file or directory
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 108 (type SRCH) for AirplaneLD-COL-0020-CTLFireability-04
lola: result : unknown
lola: time used : 1.000000
lola: memory pages used : 1
lola: FINISHED task # 102 (type SKEL/EQUN) for AirplaneLD-COL-0020-CTLFireability-12
lola: result : true
lola: FINISHED task # 105 (type FNDP) for AirplaneLD-COL-0020-CTLFireability-04
lola: result : true
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:736
lola: rewrite Frontend/Parser/formula_rewrite.k:696
lola: CANCELED task # 106 (type EQUN) for AirplaneLD-COL-0020-CTLFireability-04 (obsolete)
lola: FINISHED task # 106 (type EQUN) for AirplaneLD-COL-0020-CTLFireability-04
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 110 (type FNDP) for 48 AirplaneLD-COL-0020-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 111 (type EQUN) for 48 AirplaneLD-COL-0020-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type SRCH) for 48 AirplaneLD-COL-0020-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 113 (type SRCH) for AirplaneLD-COL-0020-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-111.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 111 (type EQUN) for AirplaneLD-COL-0020-CTLFireability-12
lola: result : true
lola: CANCELED task # 110 (type FNDP) for AirplaneLD-COL-0020-CTLFireability-12 (obsolete)
lola: FINISHED task # 110 (type FNDP) for AirplaneLD-COL-0020-CTLFireability-12
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-91.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 91 (type EQUN) for AirplaneLD-COL-0020-CTLFireability-13
lola: result : true
lola: FINISHED task # 8 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-01
lola: result : true
lola: markings : 308302
lola: fired transitions : 3430562
lola: time used : 4.000000
lola: memory pages used : 2
lola: LAUNCH task # 66 (type EXCL) for 65 AirplaneLD-COL-0020-CTLFireability-15
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 66 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-15
lola: result : false
lola: markings : 29
lola: fired transitions : 38
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 AirplaneLD-COL-0020-CTLFireability-11
lola: time limit : 276 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0020-CTLFireability-01: CTL true CTL model checker
AirplaneLD-COL-0020-CTLFireability-06: EG false skeleton: state space / EG
AirplaneLD-COL-0020-CTLFireability-13: EF true findpath
AirplaneLD-COL-0020-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0020-CTLFireability-00: DISJ 0 1 0 0 4 0 0 5
AirplaneLD-COL-0020-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0020-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0020-CTLFireability-04: CONJ 0 2 0 0 9 0 0 1
AirplaneLD-COL-0020-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0020-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0020-CTLFireability-08: SP ECTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0020-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0020-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0020-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
AirplaneLD-COL-0020-CTLFireability-12: DISJ 0 1 0 0 10 0 0 4
AirplaneLD-COL-0020-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 1/276 1/32 AirplaneLD-COL-0020-CTLFireability-11 156601 m, 31320 m/sec, 736511 t fired, .
Time elapsed: 6 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 46 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-11
lola: result : false
lola: markings : 308302
lola: fired transitions : 1737812
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 43 (type EXCL) for 42 AirplaneLD-COL-0020-CTLFireability-10
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-10
lola: result : true
lola: markings : 86
lola: fired transitions : 102
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 AirplaneLD-COL-0020-CTLFireability-09
lola: time limit : 326 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-09
lola: result : false
lola: markings : 14701
lola: fired transitions : 43727
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 AirplaneLD-COL-0020-CTLFireability-07
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-07
lola: result : false
lola: markings : 460
lola: fired transitions : 480
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 16 AirplaneLD-COL-0020-CTLFireability-04
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-04
lola: result : true
lola: markings : 84
lola: fired transitions : 83
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 AirplaneLD-COL-0020-CTLFireability-03
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-03
lola: result : false
lola: markings : 25
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 AirplaneLD-COL-0020-CTLFireability-02
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-02
lola: result : true
lola: markings : 308302
lola: fired transitions : 1339104
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 5 (type EXCL) for 0 AirplaneLD-COL-0020-CTLFireability-00
lola: time limit : 598 sec
lola: memory limit: 32 pages
lola: FINISHED task # 5 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-00
lola: result : false
lola: markings : 5174
lola: fired transitions : 9305
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 84 (type EXCL) for 36 AirplaneLD-COL-0020-CTLFireability-08
lola: time limit : 718 sec
lola: memory limit: 32 pages
lola: FINISHED task # 84 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-08
lola: result : false
lola: markings : 57351
lola: fired transitions : 126359
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 48 AirplaneLD-COL-0020-CTLFireability-12
lola: time limit : 898 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-12
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 63 (type EXCL) for 62 AirplaneLD-COL-0020-CTLFireability-14
lola: time limit : 1197 sec
lola: memory limit: 32 pages
lola: FINISHED task # 63 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-14
lola: result : false
lola: markings : 11
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 16 AirplaneLD-COL-0020-CTLFireability-04
lola: time limit : 1796 sec
lola: memory limit: 32 pages
lola: FINISHED task # 87 (type EQUN) for AirplaneLD-COL-0020-CTLFireability-12
lola: result : unknown
lola: FINISHED task # 23 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-04
lola: result : true
lola: markings : 308302
lola: fired transitions : 1647868
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 28 (type EXCL) for 27 AirplaneLD-COL-0020-CTLFireability-05
lola: time limit : 3590 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0020-CTLFireability-00: DISJ false DISJ
AirplaneLD-COL-0020-CTLFireability-01: CTL true CTL model checker
AirplaneLD-COL-0020-CTLFireability-02: CTL true CTL model checker
AirplaneLD-COL-0020-CTLFireability-03: CTL false CTL model checker
AirplaneLD-COL-0020-CTLFireability-04: CONJ true CONJ
AirplaneLD-COL-0020-CTLFireability-06: EG false skeleton: state space / EG
AirplaneLD-COL-0020-CTLFireability-07: CTL false CTL model checker
AirplaneLD-COL-0020-CTLFireability-08: SP ECTL true LTL model checker
AirplaneLD-COL-0020-CTLFireability-09: CTL false CTL model checker
AirplaneLD-COL-0020-CTLFireability-10: CTL true CTL model checker
AirplaneLD-COL-0020-CTLFireability-11: CTL false CTL model checker
AirplaneLD-COL-0020-CTLFireability-12: DISJ false DISJ
AirplaneLD-COL-0020-CTLFireability-13: EF true findpath
AirplaneLD-COL-0020-CTLFireability-14: CTL false CTL model checker
AirplaneLD-COL-0020-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0020-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 1/3590 1/32 AirplaneLD-COL-0020-CTLFireability-05 202591 m, 40518 m/sec, 982305 t fired, .
Time elapsed: 11 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 28 (type EXCL) for AirplaneLD-COL-0020-CTLFireability-05
lola: result : true
lola: markings : 308302
lola: fired transitions : 1701669
lola: time used : 2.000000
lola: memory pages used : 2
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0020-CTLFireability-00: DISJ false DISJ
AirplaneLD-COL-0020-CTLFireability-01: CTL true CTL model checker
AirplaneLD-COL-0020-CTLFireability-02: CTL true CTL model checker
AirplaneLD-COL-0020-CTLFireability-03: CTL false CTL model checker
AirplaneLD-COL-0020-CTLFireability-04: CONJ true CONJ
AirplaneLD-COL-0020-CTLFireability-05: CTL true CTL model checker
AirplaneLD-COL-0020-CTLFireability-06: EG false skeleton: state space / EG
AirplaneLD-COL-0020-CTLFireability-07: CTL false CTL model checker
AirplaneLD-COL-0020-CTLFireability-08: SP ECTL true LTL model checker
AirplaneLD-COL-0020-CTLFireability-09: CTL false CTL model checker
AirplaneLD-COL-0020-CTLFireability-10: CTL true CTL model checker
AirplaneLD-COL-0020-CTLFireability-11: CTL false CTL model checker
AirplaneLD-COL-0020-CTLFireability-12: DISJ false DISJ
AirplaneLD-COL-0020-CTLFireability-13: EF true findpath
AirplaneLD-COL-0020-CTLFireability-14: CTL false CTL model checker
AirplaneLD-COL-0020-CTLFireability-15: CTL false CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0020"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0020, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r006-oct2-167813593900178"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0020.tgz
mv AirplaneLD-COL-0020 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;