About the Execution of LoLa+red for PGCD-PT-D05N025
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
5677.443 | 134428.00 | 127668.00 | 820.70 | ??????FTTTFFFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r519-tall-167987245300482.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PGCD-PT-D05N025, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r519-tall-167987245300482
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 508K
-rw-r--r-- 1 mcc users 7.5K Mar 23 15:25 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Mar 23 15:25 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Mar 23 15:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Mar 23 15:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.5K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 34K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 12K Mar 23 15:26 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Mar 23 15:26 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Mar 23 15:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 104K Mar 23 15:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.9K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 12K Mar 31 16:48 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-00
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-01
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-02
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-03
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-04
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-05
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-06
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-07
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-08
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-09
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-10
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-11
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-12
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-13
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-14
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1680818542879
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PGCD-PT-D05N025
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2023-04-06 22:02:24] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-04-06 22:02:24] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-04-06 22:02:24] [INFO ] Load time of PNML (sax parser for PT used): 26 ms
[2023-04-06 22:02:24] [INFO ] Transformed 18 places.
[2023-04-06 22:02:24] [INFO ] Transformed 18 transitions.
[2023-04-06 22:02:24] [INFO ] Parsed PT model containing 18 places and 18 transitions and 84 arcs in 102 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Initial state reduction rules removed 3 formulas.
FORMULA PGCD-PT-D05N025-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PGCD-PT-D05N025-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PGCD-PT-D05N025-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 18 out of 18 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 13 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
// Phase 1: matrix 18 rows 18 cols
[2023-04-06 22:02:24] [INFO ] Computed 7 invariants in 6 ms
[2023-04-06 22:02:24] [INFO ] Dead Transitions using invariants and state equation in 140 ms found 0 transitions.
[2023-04-06 22:02:24] [INFO ] Invariant cache hit.
[2023-04-06 22:02:24] [INFO ] Implicit Places using invariants in 34 ms returned []
[2023-04-06 22:02:24] [INFO ] Invariant cache hit.
[2023-04-06 22:02:24] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-04-06 22:02:24] [INFO ] Implicit Places using invariants and state equation in 41 ms returned []
Implicit Place search using SMT with State Equation took 76 ms to find 0 implicit places.
[2023-04-06 22:02:24] [INFO ] Invariant cache hit.
[2023-04-06 22:02:24] [INFO ] Dead Transitions using invariants and state equation in 41 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 300 ms. Remains : 18/18 places, 18/18 transitions.
Support contains 18 out of 18 places after structural reductions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 15 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 5 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Finished random walk after 1070 steps, including 0 resets, run visited all 31 properties in 24 ms. (steps per millisecond=44 )
Parikh walk visited 0 properties in 0 ms.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 3 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 3 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 39 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 3 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 33 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 35 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 28 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 102 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 103 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 28 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 5 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 36 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 42 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 2 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 2 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 22:02:25] [INFO ] Invariant cache hit.
[2023-04-06 22:02:25] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Input system was already deterministic with 18 transitions.
Finished random walk after 59 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=59 )
FORMULA PGCD-PT-D05N025-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Parikh walk visited 0 properties in 0 ms.
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:02:25] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:02:25] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-04-06 22:02:25] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 18 places, 18 transitions and 84 arcs took 1 ms.
Total runtime 1410 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PGCD-PT-D05N025
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA PGCD-PT-D05N025-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D05N025-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D05N025-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D05N025-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D05N025-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D05N025-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1680818677307
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: LAUNCH task # 1 (type EXCL) for 0 PGCD-PT-D05N025-CTLFireability-00
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/257 8/32 PGCD-PT-D05N025-CTLFireability-00 1776592 m, 355318 m/sec, 7844996 t fired, .
Time elapsed: 5 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 11/257 15/32 PGCD-PT-D05N025-CTLFireability-00 3413974 m, 327476 m/sec, 13850471 t fired, .
Time elapsed: 11 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 16/257 21/32 PGCD-PT-D05N025-CTLFireability-00 4907464 m, 298698 m/sec, 19460580 t fired, .
Time elapsed: 16 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 21/257 28/32 PGCD-PT-D05N025-CTLFireability-00 6356995 m, 289906 m/sec, 24968619 t fired, .
Time elapsed: 21 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 1 (type EXCL) for PGCD-PT-D05N025-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 26 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 39 (type EXCL) for 38 PGCD-PT-D05N025-CTLFireability-13
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for PGCD-PT-D05N025-CTLFireability-13
lola: result : true
lola: markings : 8
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 PGCD-PT-D05N025-CTLFireability-10
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for PGCD-PT-D05N025-CTLFireability-10
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 PGCD-PT-D05N025-CTLFireability-07
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for PGCD-PT-D05N025-CTLFireability-07
lola: result : true
lola: markings : 4919
lola: fired transitions : 9393
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 PGCD-PT-D05N025-CTLFireability-06
lola: time limit : 357 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for PGCD-PT-D05N025-CTLFireability-06
lola: result : false
lola: markings : 511
lola: fired transitions : 511
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 PGCD-PT-D05N025-CTLFireability-05
lola: time limit : 397 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/397 7/32 PGCD-PT-D05N025-CTLFireability-05 1382679 m, 276535 m/sec, 10318507 t fired, .
Time elapsed: 31 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/397 13/32 PGCD-PT-D05N025-CTLFireability-05 2780852 m, 279634 m/sec, 19074285 t fired, .
Time elapsed: 36 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/397 18/32 PGCD-PT-D05N025-CTLFireability-05 4080561 m, 259941 m/sec, 27322367 t fired, .
Time elapsed: 41 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 20/397 24/32 PGCD-PT-D05N025-CTLFireability-05 5414875 m, 266862 m/sec, 35598384 t fired, .
Time elapsed: 46 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/397 29/32 PGCD-PT-D05N025-CTLFireability-05 6682839 m, 253592 m/sec, 43705668 t fired, .
Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 20 (type EXCL) for PGCD-PT-D05N025-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 17 (type EXCL) for 16 PGCD-PT-D05N025-CTLFireability-04
lola: time limit : 443 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/443 11/32 PGCD-PT-D05N025-CTLFireability-04 2456601 m, 491320 m/sec, 10686840 t fired, .
Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/443 19/32 PGCD-PT-D05N025-CTLFireability-04 4428214 m, 394322 m/sec, 19545477 t fired, .
Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/443 27/32 PGCD-PT-D05N025-CTLFireability-04 6338473 m, 382051 m/sec, 28153389 t fired, .
Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 17 (type EXCL) for PGCD-PT-D05N025-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 14 (type EXCL) for 13 PGCD-PT-D05N025-CTLFireability-03
lola: time limit : 503 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/503 16/32 PGCD-PT-D05N025-CTLFireability-03 3641471 m, 728294 m/sec, 8888822 t fired, .
Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 10/503 30/32 PGCD-PT-D05N025-CTLFireability-03 6824689 m, 636643 m/sec, 16024109 t fired, .
Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 14 (type EXCL) for PGCD-PT-D05N025-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 11 (type EXCL) for 6 PGCD-PT-D05N025-CTLFireability-02
lola: time limit : 584 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 1 1 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/584 10/32 PGCD-PT-D05N025-CTLFireability-02 2166198 m, 433239 m/sec, 9044782 t fired, .
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 1 1 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/584 19/32 PGCD-PT-D05N025-CTLFireability-02 4264210 m, 419602 m/sec, 16419488 t fired, .
Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 1 1 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 15/584 27/32 PGCD-PT-D05N025-CTLFireability-02 6325530 m, 412264 m/sec, 23558985 t fired, .
Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 11 (type EXCL) for PGCD-PT-D05N025-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 1 0 0 2 0 1 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 9 (type EXCL) for 6 PGCD-PT-D05N025-CTLFireability-02
lola: time limit : 697 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for PGCD-PT-D05N025-CTLFireability-02
lola: result : true
lola: markings : 373630
lola: fired transitions : 1474455
lola: time used : 0.000000
lola: memory pages used : 2
lola: LAUNCH task # 4 (type EXCL) for 3 PGCD-PT-D05N025-CTLFireability-01
lola: time limit : 872 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/872 9/32 PGCD-PT-D05N025-CTLFireability-01 2001055 m, 400211 m/sec, 8140602 t fired, .
Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/872 18/32 PGCD-PT-D05N025-CTLFireability-01 4106604 m, 421109 m/sec, 15941742 t fired, .
Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/872 26/32 PGCD-PT-D05N025-CTLFireability-01 6102881 m, 399255 m/sec, 23418413 t fired, .
Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 4 (type EXCL) for PGCD-PT-D05N025-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D05N025-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-02: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D05N025-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D05N025-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 44 (type EXCL) for 31 PGCD-PT-D05N025-CTLFireability-11
lola: time limit : 1156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for PGCD-PT-D05N025-CTLFireability-11
lola: result : true
lola: markings : 53
lola: fired transitions : 53
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 PGCD-PT-D05N025-CTLFireability-14
lola: time limit : 3469 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for PGCD-PT-D05N025-CTLFireability-14
lola: result : false
lola: markings : 78
lola: fired transitions : 111
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 12
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D05N025-CTLFireability-00: CTL unknown AGGR
PGCD-PT-D05N025-CTLFireability-01: CTL unknown AGGR
PGCD-PT-D05N025-CTLFireability-02: CONJ unknown CONJ
PGCD-PT-D05N025-CTLFireability-03: CTL unknown AGGR
PGCD-PT-D05N025-CTLFireability-04: CTL unknown AGGR
PGCD-PT-D05N025-CTLFireability-05: CTL unknown AGGR
PGCD-PT-D05N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D05N025-CTLFireability-11: CONJ false state space /EFEG
PGCD-PT-D05N025-CTLFireability-13: CTL true CTL model checker
PGCD-PT-D05N025-CTLFireability-14: CTL false CTL model checker
Time elapsed: 131 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-PT-D05N025"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PGCD-PT-D05N025, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r519-tall-167987245300482"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PGCD-PT-D05N025.tgz
mv PGCD-PT-D05N025 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;