Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r519-tall-167987245300466.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PGCD-PT-D04N025, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r519-tall-167987245300466
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 6.6K Mar 23 15:25 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Mar 23 15:25 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.3K Mar 23 15:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 37K Mar 23 15:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.1K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 34K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 12K Mar 23 15:25 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Mar 23 15:25 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Mar 23 15:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Mar 23 15:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.7K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 9.3K Mar 31 16:48 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-00
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-01
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-02
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-03
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-04
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-05
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-06
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-07
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-08
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-09
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-10
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-11
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-12
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-13
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-14
FORMULA_NAME PGCD-PT-D04N025-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1680818453933

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PGCD-PT-D04N025
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2023-04-06 22:00:55] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-04-06 22:00:55] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-04-06 22:00:55] [INFO ] Load time of PNML (sax parser for PT used): 22 ms
[2023-04-06 22:00:55] [INFO ] Transformed 15 places.
[2023-04-06 22:00:55] [INFO ] Transformed 15 transitions.
[2023-04-06 22:00:55] [INFO ] Parsed PT model containing 15 places and 15 transitions and 70 arcs in 80 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 15 out of 15 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 8 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
// Phase 1: matrix 15 rows 15 cols
[2023-04-06 22:00:55] [INFO ] Computed 6 invariants in 6 ms
[2023-04-06 22:00:55] [INFO ] SMT solver returned unknown. Retrying;
[2023-04-06 22:00:55] [INFO ] Dead Transitions using invariants and state equation in 241 ms found 0 transitions.
[2023-04-06 22:00:55] [INFO ] Invariant cache hit.
[2023-04-06 22:00:55] [INFO ] Implicit Places using invariants in 25 ms returned []
[2023-04-06 22:00:55] [INFO ] Invariant cache hit.
[2023-04-06 22:00:55] [INFO ] State equation strengthened by 5 read => feed constraints.
[2023-04-06 22:00:55] [INFO ] Implicit Places using invariants and state equation in 42 ms returned []
Implicit Place search using SMT with State Equation took 69 ms to find 0 implicit places.
[2023-04-06 22:00:55] [INFO ] Invariant cache hit.
[2023-04-06 22:00:55] [INFO ] Dead Transitions using invariants and state equation in 40 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 383 ms. Remains : 15/15 places, 15/15 transitions.
Support contains 15 out of 15 places after structural reductions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 15 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 5 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Finished random walk after 256 steps, including 0 resets, run visited all 29 properties in 16 ms. (steps per millisecond=16 )
Parikh walk visited 0 properties in 0 ms.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 3 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 3 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 4 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 39 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 46 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 3 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 2 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 33 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 28 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 2 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 5 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:00:56] [INFO ] Invariant cache hit.
[2023-04-06 22:00:56] [INFO ] Dead Transitions using invariants and state equation in 33 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 35 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Input system was already deterministic with 15 transitions.
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:00:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:00:56] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-04-06 22:00:56] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 15 places, 15 transitions and 70 arcs took 0 ms.
Total runtime 1440 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PGCD-PT-D04N025
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

FORMULA PGCD-PT-D04N025-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D04N025-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1680818466842

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 13 (type EXCL) for 12 PGCD-PT-D04N025-CTLFireability-04
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 13 (type EXCL) for PGCD-PT-D04N025-CTLFireability-04
lola: result : false
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 PGCD-PT-D04N025-CTLFireability-02
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 7 (type EXCL) for PGCD-PT-D04N025-CTLFireability-02
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 PGCD-PT-D04N025-CTLFireability-06
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for PGCD-PT-D04N025-CTLFireability-06
lola: result : false
lola: markings : 3
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 56 (type EXCL) for 39 PGCD-PT-D04N025-CTLFireability-13
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for PGCD-PT-D04N025-CTLFireability-13
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 PGCD-PT-D04N025-CTLFireability-15
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for PGCD-PT-D04N025-CTLFireability-15
lola: result : false
lola: markings : 29
lola: fired transitions : 40
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 45 (type EXCL) for 42 PGCD-PT-D04N025-CTLFireability-14
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 45 (type EXCL) for PGCD-PT-D04N025-CTLFireability-14
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 37 (type EXCL) for 36 PGCD-PT-D04N025-CTLFireability-12
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N025-CTLFireability-02: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-04: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-13: AXAG false state space /EXEF
PGCD-PT-D04N025-CTLFireability-14: CONJ false CTL model checker
PGCD-PT-D04N025-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N025-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N025-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N025-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N025-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N025-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N025-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N025-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N025-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N025-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/359 11/32 PGCD-PT-D04N025-CTLFireability-12 2535425 m, 507085 m/sec, 10543707 t fired, .

Time elapsed: 6 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 37 (type EXCL) for PGCD-PT-D04N025-CTLFireability-12
lola: result : false
lola: markings : 3594056
lola: fired transitions : 15553168
lola: time used : 8.000000
lola: memory pages used : 16
lola: LAUNCH task # 34 (type EXCL) for 33 PGCD-PT-D04N025-CTLFireability-11
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for PGCD-PT-D04N025-CTLFireability-11
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 PGCD-PT-D04N025-CTLFireability-10
lola: time limit : 448 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for PGCD-PT-D04N025-CTLFireability-10
lola: result : false
lola: markings : 3
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 PGCD-PT-D04N025-CTLFireability-08
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for PGCD-PT-D04N025-CTLFireability-08
lola: result : true
lola: markings : 3
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 PGCD-PT-D04N025-CTLFireability-07
lola: time limit : 598 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for PGCD-PT-D04N025-CTLFireability-07
lola: result : true
lola: markings : 31795
lola: fired transitions : 78509
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 PGCD-PT-D04N025-CTLFireability-05
lola: time limit : 718 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for PGCD-PT-D04N025-CTLFireability-05
lola: result : false
lola: markings : 3
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 PGCD-PT-D04N025-CTLFireability-01
lola: time limit : 897 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for PGCD-PT-D04N025-CTLFireability-01
lola: result : true
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 PGCD-PT-D04N025-CTLFireability-09
lola: time limit : 1197 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for PGCD-PT-D04N025-CTLFireability-09
lola: result : false
lola: markings : 3
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 PGCD-PT-D04N025-CTLFireability-03
lola: time limit : 1795 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for PGCD-PT-D04N025-CTLFireability-03
lola: result : false
lola: markings : 429726
lola: fired transitions : 1260473
lola: time used : 0.000000
lola: memory pages used : 2
lola: LAUNCH task # 1 (type EXCL) for 0 PGCD-PT-D04N025-CTLFireability-00
lola: time limit : 3591 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for PGCD-PT-D04N025-CTLFireability-00
lola: result : false
lola: markings : 3
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N025-CTLFireability-00: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-01: CTL true CTL model checker
PGCD-PT-D04N025-CTLFireability-02: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-03: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-04: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-05: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-06: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D04N025-CTLFireability-08: CTL true CTL model checker
PGCD-PT-D04N025-CTLFireability-09: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-10: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-11: CTL true CTL model checker
PGCD-PT-D04N025-CTLFireability-12: CTL false CTL model checker
PGCD-PT-D04N025-CTLFireability-13: AXAG false state space /EXEF
PGCD-PT-D04N025-CTLFireability-14: CONJ false CTL model checker
PGCD-PT-D04N025-CTLFireability-15: CTL false CTL model checker


Time elapsed: 9 secs. Pages in use: 16

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-PT-D04N025"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PGCD-PT-D04N025, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r519-tall-167987245300466"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PGCD-PT-D04N025.tgz
mv PGCD-PT-D04N025 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;