About the Execution of LoLa+red for PGCD-PT-D03N050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5102.943 | 149059.00 | 132214.00 | 716.40 | ???????TT?TTTFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r519-tall-167987245300458.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PGCD-PT-D03N050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r519-tall-167987245300458
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 5.7K Mar 23 15:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Mar 23 15:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Mar 23 15:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Mar 23 15:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.7K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 32K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 14K Mar 23 15:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 150K Mar 23 15:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Mar 23 15:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 70K Mar 23 15:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.5K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 7.4K Mar 31 16:48 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-00
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-01
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-02
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-03
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-04
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-05
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-06
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-07
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-08
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-09
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-10
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-11
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-12
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-13
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-14
FORMULA_NAME PGCD-PT-D03N050-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1680818369704
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PGCD-PT-D03N050
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2023-04-06 21:59:31] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-04-06 21:59:31] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-04-06 21:59:31] [INFO ] Load time of PNML (sax parser for PT used): 20 ms
[2023-04-06 21:59:31] [INFO ] Transformed 12 places.
[2023-04-06 21:59:31] [INFO ] Transformed 12 transitions.
[2023-04-06 21:59:31] [INFO ] Parsed PT model containing 12 places and 12 transitions and 56 arcs in 73 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Initial state reduction rules removed 1 formulas.
FORMULA PGCD-PT-D03N050-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 12 out of 12 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 8 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
// Phase 1: matrix 12 rows 12 cols
[2023-04-06 21:59:31] [INFO ] Computed 5 invariants in 6 ms
[2023-04-06 21:59:31] [INFO ] Dead Transitions using invariants and state equation in 146 ms found 0 transitions.
[2023-04-06 21:59:31] [INFO ] Invariant cache hit.
[2023-04-06 21:59:31] [INFO ] Implicit Places using invariants in 22 ms returned []
[2023-04-06 21:59:31] [INFO ] Invariant cache hit.
[2023-04-06 21:59:31] [INFO ] State equation strengthened by 4 read => feed constraints.
[2023-04-06 21:59:31] [INFO ] Implicit Places using invariants and state equation in 28 ms returned []
Implicit Place search using SMT with State Equation took 52 ms to find 0 implicit places.
[2023-04-06 21:59:31] [INFO ] Invariant cache hit.
[2023-04-06 21:59:31] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 260 ms. Remains : 12/12 places, 12/12 transitions.
Support contains 12 out of 12 places after structural reductions.
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 13 ms
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 5 ms
[2023-04-06 21:59:31] [INFO ] Input system was already deterministic with 12 transitions.
Finished random walk after 3510 steps, including 1 resets, run visited all 32 properties in 30 ms. (steps per millisecond=117 )
Parikh walk visited 0 properties in 0 ms.
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 4 ms
[2023-04-06 21:59:31] [INFO ] Input system was already deterministic with 12 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:31] [INFO ] Invariant cache hit.
[2023-04-06 21:59:31] [INFO ] Dead Transitions using invariants and state equation in 42 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 44 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:31] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:31] [INFO ] Invariant cache hit.
[2023-04-06 21:59:31] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:31] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:31] [INFO ] Invariant cache hit.
[2023-04-06 21:59:31] [INFO ] Dead Transitions using invariants and state equation in 21 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 25 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:31] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 5 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:31] [INFO ] Invariant cache hit.
[2023-04-06 21:59:31] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:31] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:31] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:31] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 24 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:32] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 39 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:32] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 21 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:32] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 20 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:32] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 19 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 20 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:32] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:32] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:32] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 21 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 0 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:32] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:32] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 21 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 12/12 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 12/12 (removed 0) transitions.
[2023-04-06 21:59:32] [INFO ] Invariant cache hit.
[2023-04-06 21:59:32] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 12/12 places, 12/12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Input system was already deterministic with 12 transitions.
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:59:32] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:59:32] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-04-06 21:59:32] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 12 places, 12 transitions and 56 arcs took 0 ms.
Total runtime 1242 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PGCD-PT-D03N050
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA PGCD-PT-D03N050-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D03N050-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D03N050-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D03N050-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D03N050-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D03N050-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D03N050-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1680818518763
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
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PGCD-PT-D03N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
PGCD-PT-D03N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D03N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D03N050-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 16 (type EXCL) for 15 PGCD-PT-D03N050-CTLFireability-05
lola: time limit : 871 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D03N050-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-11: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-12: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-13: DISJ false DISJ
PGCD-PT-D03N050-CTLFireability-15: CTL true CTL model checker
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PGCD-PT-D03N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D03N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
PGCD-PT-D03N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D03N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D03N050-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 5/871 19/32 PGCD-PT-D03N050-CTLFireability-05 4932408 m, 986481 m/sec, 10682840 t fired, .
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PGCD-PT-D03N050-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-11: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-12: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-13: DISJ false DISJ
PGCD-PT-D03N050-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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PGCD-PT-D03N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
PGCD-PT-D03N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D03N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D03N050-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 10/871 31/32 PGCD-PT-D03N050-CTLFireability-05 8124123 m, 638343 m/sec, 19949533 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D03N050-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-11: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-12: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-13: DISJ false DISJ
PGCD-PT-D03N050-CTLFireability-15: CTL true CTL model checker
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PGCD-PT-D03N050-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D03N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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lola: time limit : 1156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for PGCD-PT-D03N050-CTLFireability-14
lola: result : false
lola: markings : 34
lola: fired transitions : 93
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 PGCD-PT-D03N050-CTLFireability-03
lola: time limit : 1735 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D03N050-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-11: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-12: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-13: DISJ false DISJ
PGCD-PT-D03N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D03N050-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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PGCD-PT-D03N050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D03N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D03N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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10 CTL EXCL 5/1735 15/32 PGCD-PT-D03N050-CTLFireability-03 3368054 m, 673610 m/sec, 10785964 t fired, .
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PGCD-PT-D03N050-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-11: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-12: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-13: DISJ false DISJ
PGCD-PT-D03N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D03N050-CTLFireability-15: CTL true CTL model checker
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PGCD-PT-D03N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D03N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/1735 27/32 PGCD-PT-D03N050-CTLFireability-03 6255738 m, 577536 m/sec, 20638432 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D03N050-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-11: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-12: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-13: DISJ false DISJ
PGCD-PT-D03N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D03N050-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D03N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D03N050-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
PGCD-PT-D03N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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lola: FINISHED task # 32 (type EXCL) for PGCD-PT-D03N050-CTLFireability-10
lola: result : true
lola: markings : 148063
lola: fired transitions : 327898
lola: time used : 0.000000
lola: memory pages used : 1
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D03N050-CTLFireability-00: CTL unknown AGGR
PGCD-PT-D03N050-CTLFireability-01: CTL unknown AGGR
PGCD-PT-D03N050-CTLFireability-02: CTL unknown AGGR
PGCD-PT-D03N050-CTLFireability-03: CTL unknown AGGR
PGCD-PT-D03N050-CTLFireability-04: CTL unknown AGGR
PGCD-PT-D03N050-CTLFireability-05: AGEF unknown AGGR
PGCD-PT-D03N050-CTLFireability-06: CTL unknown AGGR
PGCD-PT-D03N050-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-09: CONJ unknown CONJ
PGCD-PT-D03N050-CTLFireability-10: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-11: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-12: CTL true CTL model checker
PGCD-PT-D03N050-CTLFireability-13: DISJ false DISJ
PGCD-PT-D03N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D03N050-CTLFireability-15: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-PT-D03N050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PGCD-PT-D03N050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r519-tall-167987245300458"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PGCD-PT-D03N050.tgz
mv PGCD-PT-D03N050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;