Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r519-tall-167987245300426.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PGCD-COL-D05N025, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r519-tall-167987245300426
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 412K
-rw-r--r-- 1 mcc users 7.7K Mar 23 15:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 87K Mar 23 15:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Mar 23 15:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Mar 23 15:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 8.8K Mar 23 15:25 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 91K Mar 23 15:25 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Mar 23 15:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Mar 23 15:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 11K Mar 31 16:48 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-00
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-01
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-02
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-03
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-04
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-05
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-06
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-07
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-08
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-09
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-10
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-11
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-12
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-13
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-14
FORMULA_NAME PGCD-COL-D05N025-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1680814762742

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PGCD-COL-D05N025
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2023-04-06 20:59:24] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-04-06 20:59:24] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-04-06 20:59:24] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-04-06 20:59:24] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-04-06 20:59:24] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 374 ms
[2023-04-06 20:59:24] [INFO ] Imported 3 HL places and 3 HL transitions for a total of 18 PT places and 18.0 transition bindings in 24 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 12 ms.
[2023-04-06 20:59:24] [INFO ] Built PT skeleton of HLPN with 3 places and 3 transitions 14 arcs in 3 ms.
[2023-04-06 20:59:24] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 1 properties that can be checked using skeleton over-approximation.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 0 steps, including 0 resets, run visited all 0 properties in 1 ms. (steps per millisecond=0 )
Finished probabilistic random walk after 0 steps, run visited all 0 properties in 0 ms. (steps per millisecond=0 )
[2023-04-06 20:59:24] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-04-06 20:59:24] [INFO ] Flatten gal took : 12 ms
FORMULA PGCD-COL-D05N025-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-04-06 20:59:24] [INFO ] Flatten gal took : 1 ms
Arc [2:1*[(MOD (ADD $x 1) 6)]] contains successor/predecessor on variables of sort CD
[2023-04-06 20:59:24] [INFO ] Unfolded HLPN to a Petri net with 18 places and 18 transitions 84 arcs in 6 ms.
[2023-04-06 20:59:24] [INFO ] Unfolded 15 HLPN properties in 1 ms.
Initial state reduction rules removed 3 formulas.
FORMULA PGCD-COL-D05N025-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PGCD-COL-D05N025-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PGCD-COL-D05N025-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 18 out of 18 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 5 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
// Phase 1: matrix 18 rows 18 cols
[2023-04-06 20:59:25] [INFO ] Computed 7 invariants in 10 ms
[2023-04-06 20:59:25] [INFO ] Dead Transitions using invariants and state equation in 152 ms found 0 transitions.
[2023-04-06 20:59:25] [INFO ] Invariant cache hit.
[2023-04-06 20:59:25] [INFO ] Implicit Places using invariants in 24 ms returned []
[2023-04-06 20:59:25] [INFO ] Invariant cache hit.
[2023-04-06 20:59:25] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-04-06 20:59:25] [INFO ] Implicit Places using invariants and state equation in 35 ms returned []
Implicit Place search using SMT with State Equation took 60 ms to find 0 implicit places.
[2023-04-06 20:59:25] [INFO ] Invariant cache hit.
[2023-04-06 20:59:25] [INFO ] Dead Transitions using invariants and state equation in 40 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 297 ms. Remains : 18/18 places, 18/18 transitions.
Support contains 18 out of 18 places after structural reductions.
[2023-04-06 20:59:25] [INFO ] Flatten gal took : 9 ms
[2023-04-06 20:59:25] [INFO ] Flatten gal took : 11 ms
[2023-04-06 20:59:25] [INFO ] Input system was already deterministic with 18 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 144 ms. (steps per millisecond=69 ) properties (out of 18) seen :9
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 187 ms. (steps per millisecond=53 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 150 ms. (steps per millisecond=66 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 9) seen :0
Running SMT prover for 9 properties.
[2023-04-06 20:59:26] [INFO ] Invariant cache hit.
[2023-04-06 20:59:26] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-04-06 20:59:26] [INFO ] [Real]Absence check using 2 positive and 5 generalized place invariants in 1 ms returned sat
[2023-04-06 20:59:26] [INFO ] After 69ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:7
[2023-04-06 20:59:26] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-04-06 20:59:26] [INFO ] [Nat]Absence check using 2 positive and 5 generalized place invariants in 1 ms returned sat
[2023-04-06 20:59:26] [INFO ] After 49ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :7
[2023-04-06 20:59:26] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-04-06 20:59:26] [INFO ] After 50ms SMT Verify possible using 6 Read/Feed constraints in natural domain returned unsat :2 sat :7
[2023-04-06 20:59:26] [INFO ] After 113ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :7
Attempting to minimize the solution found.
Minimization took 52 ms.
[2023-04-06 20:59:26] [INFO ] After 430ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :7
Fused 9 Parikh solutions to 7 different solutions.
Parikh walk visited 0 properties in 79 ms.
Support contains 18 out of 18 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 3 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:26] [INFO ] Invariant cache hit.
[2023-04-06 20:59:26] [INFO ] Dead Transitions using invariants and state equation in 42 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 47 ms. Remains : 18/18 places, 18/18 transitions.
Incomplete random walk after 10008 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=435 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 7) seen :0
Finished probabilistic random walk after 30661 steps, run visited all 7 properties in 395 ms. (steps per millisecond=77 )
Probabilistic random walk after 30661 steps, saw 21069 distinct states, run finished after 396 ms. (steps per millisecond=77 ) properties seen :7
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 2 atomic propositions for a total of 12 simplifications.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 4 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 8 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 3 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 3 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 3 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 3 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 3 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 2 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 29 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Finished random walk after 26 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=13 )
FORMULA PGCD-COL-D05N025-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Parikh walk visited 0 properties in 0 ms.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 24 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 24 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:27] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:59:27] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:59:27] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 18/18 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 18/18 (removed 0) transitions.
[2023-04-06 20:59:27] [INFO ] Invariant cache hit.
[2023-04-06 20:59:28] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 25 ms. Remains : 18/18 places, 18/18 transitions.
[2023-04-06 20:59:28] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:59:28] [INFO ] Flatten gal took : 4 ms
[2023-04-06 20:59:28] [INFO ] Input system was already deterministic with 18 transitions.
[2023-04-06 20:59:28] [INFO ] Flatten gal took : 4 ms
[2023-04-06 20:59:28] [INFO ] Flatten gal took : 5 ms
[2023-04-06 20:59:28] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-04-06 20:59:28] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 18 places, 18 transitions and 84 arcs took 0 ms.
Total runtime 3833 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PGCD-COL-D05N025
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA PGCD-COL-D05N025-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-COL-D05N025-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-COL-D05N025-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-COL-D05N025-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-COL-D05N025-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-COL-D05N025-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-COL-D05N025-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-COL-D05N025-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-COL-D05N025-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-COL-D05N025-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1680814794443

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 4 (type EXCL) for 3 PGCD-COL-D05N025-CTLFireability-01
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 4 (type EXCL) for PGCD-COL-D05N025-CTLFireability-01
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 PGCD-COL-D05N025-CTLFireability-07
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 16 (type EXCL) for PGCD-COL-D05N025-CTLFireability-07
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 PGCD-COL-D05N025-CTLFireability-04
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for PGCD-COL-D05N025-CTLFireability-04
lola: result : true
lola: markings : 12
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 25 (type EXCL) for 24 PGCD-COL-D05N025-CTLFireability-11
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 25 (type EXCL) for PGCD-COL-D05N025-CTLFireability-11
lola: result : true
lola: markings : 2015
lola: fired transitions : 2361
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 PGCD-COL-D05N025-CTLFireability-10
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 22 (type EXCL) for PGCD-COL-D05N025-CTLFireability-10
lola: result : false
lola: markings : 555
lola: fired transitions : 566
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 PGCD-COL-D05N025-CTLFireability-15
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D05N025-CTLFireability-01: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-04: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-11: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D05N025-CTLFireability-00: EXEF 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/600 8/32 PGCD-COL-D05N025-CTLFireability-15 1582995 m, 316599 m/sec, 9757530 t fired, .

Time elapsed: 5 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 11
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D05N025-CTLFireability-01: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-04: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-11: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D05N025-CTLFireability-00: EXEF 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/600 15/32 PGCD-COL-D05N025-CTLFireability-15 3424576 m, 368316 m/sec, 18182752 t fired, .

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# running tasks: 1 of 4 Visible: 11
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D05N025-CTLFireability-01: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-04: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-11: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D05N025-CTLFireability-00: EXEF 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/600 23/32 PGCD-COL-D05N025-CTLFireability-15 5197982 m, 354681 m/sec, 26158462 t fired, .

Time elapsed: 15 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 11
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D05N025-CTLFireability-01: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-04: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-11: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D05N025-CTLFireability-00: EXEF 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/600 30/32 PGCD-COL-D05N025-CTLFireability-15 7043689 m, 369141 m/sec, 33973523 t fired, .

Time elapsed: 20 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 11
lola: CANCELED task # 31 (type EXCL) for PGCD-COL-D05N025-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D05N025-CTLFireability-01: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-04: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-11: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D05N025-CTLFireability-00: EXEF 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D05N025-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 11
lola: LAUNCH task # 28 (type EXCL) for 27 PGCD-COL-D05N025-CTLFireability-14
lola: time limit : 715 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for PGCD-COL-D05N025-CTLFireability-14
lola: result : true
lola: markings : 149
lola: fired transitions : 173
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 PGCD-COL-D05N025-CTLFireability-08
lola: time limit : 893 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for PGCD-COL-D05N025-CTLFireability-08
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 PGCD-COL-D05N025-CTLFireability-03
lola: time limit : 1191 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for PGCD-COL-D05N025-CTLFireability-03
lola: result : false
lola: markings : 148
lola: fired transitions : 168
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 PGCD-COL-D05N025-CTLFireability-02
lola: time limit : 1787 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for PGCD-COL-D05N025-CTLFireability-02
lola: result : true
lola: markings : 1
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 PGCD-COL-D05N025-CTLFireability-00
lola: time limit : 3575 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for PGCD-COL-D05N025-CTLFireability-00
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 11

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D05N025-CTLFireability-00: EXEF true state space /EXEF
PGCD-COL-D05N025-CTLFireability-01: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-02: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-03: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-04: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-08: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-10: CTL false CTL model checker
PGCD-COL-D05N025-CTLFireability-11: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-14: CTL true CTL model checker
PGCD-COL-D05N025-CTLFireability-15: CTL unknown AGGR


Time elapsed: 25 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-COL-D05N025"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PGCD-COL-D05N025, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r519-tall-167987245300426"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PGCD-COL-D05N025.tgz
mv PGCD-COL-D05N025 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;