Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r519-tall-167987245100338.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Murphy-PT-D2N050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r519-tall-167987245100338
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 7.2K Mar 23 15:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Mar 23 15:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.5K Mar 23 15:21 CTLFireability.txt
-rw-r--r-- 1 mcc users 38K Mar 23 15:21 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.1K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 12K Mar 23 15:23 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 118K Mar 23 15:23 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Mar 23 15:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 83K Mar 23 15:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.3K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 12K Mar 31 16:48 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-00
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-01
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-02
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-03
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-04
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-05
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-06
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-07
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-08
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-09
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-10
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-11
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-12
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-13
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-14
FORMULA_NAME Murphy-PT-D2N050-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1680854700784

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Murphy-PT-D2N050
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2023-04-07 08:05:02] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-04-07 08:05:02] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-04-07 08:05:02] [INFO ] Load time of PNML (sax parser for PT used): 22 ms
[2023-04-07 08:05:02] [INFO ] Transformed 18 places.
[2023-04-07 08:05:02] [INFO ] Transformed 21 transitions.
[2023-04-07 08:05:02] [INFO ] Parsed PT model containing 18 places and 21 transitions and 81 arcs in 83 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 2 formulas.
FORMULA Murphy-PT-D2N050-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Murphy-PT-D2N050-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 18 out of 18 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 9 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
// Phase 1: matrix 21 rows 18 cols
[2023-04-07 08:05:02] [INFO ] Computed 4 invariants in 7 ms
[2023-04-07 08:05:02] [INFO ] Dead Transitions using invariants and state equation in 153 ms found 0 transitions.
[2023-04-07 08:05:02] [INFO ] Invariant cache hit.
[2023-04-07 08:05:02] [INFO ] Implicit Places using invariants in 37 ms returned []
[2023-04-07 08:05:02] [INFO ] Invariant cache hit.
[2023-04-07 08:05:02] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-04-07 08:05:02] [INFO ] Implicit Places using invariants and state equation in 44 ms returned []
Implicit Place search using SMT with State Equation took 82 ms to find 0 implicit places.
[2023-04-07 08:05:02] [INFO ] Invariant cache hit.
[2023-04-07 08:05:02] [INFO ] Dead Transitions using invariants and state equation in 39 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 311 ms. Remains : 18/18 places, 21/21 transitions.
Support contains 18 out of 18 places after structural reductions.
[2023-04-07 08:05:02] [INFO ] Flatten gal took : 130 ms
[2023-04-07 08:05:02] [INFO ] Flatten gal took : 5 ms
[2023-04-07 08:05:02] [INFO ] Input system was already deterministic with 21 transitions.
Incomplete random walk after 10006 steps, including 2 resets, run finished after 102 ms. (steps per millisecond=98 ) properties (out of 30) seen :26
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-04-07 08:05:03] [INFO ] Invariant cache hit.
[2023-04-07 08:05:03] [INFO ] [Real]Absence check using 2 positive place invariants in 6 ms returned sat
[2023-04-07 08:05:03] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-04-07 08:05:03] [INFO ] After 79ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-04-07 08:05:03] [INFO ] [Nat]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-04-07 08:05:03] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 0 ms returned sat
[2023-04-07 08:05:03] [INFO ] After 22ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-04-07 08:05:03] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-04-07 08:05:03] [INFO ] After 24ms SMT Verify possible using 6 Read/Feed constraints in natural domain returned unsat :0 sat :4
[2023-04-07 08:05:03] [INFO ] After 40ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 12 ms.
[2023-04-07 08:05:03] [INFO ] After 125ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Fused 4 Parikh solutions to 3 different solutions.
Parikh walk visited 0 properties in 12 ms.
Support contains 9 out of 18 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 4 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:03] [INFO ] Invariant cache hit.
[2023-04-07 08:05:03] [INFO ] Dead Transitions using invariants and state equation in 36 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 41 ms. Remains : 18/18 places, 21/21 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 4) seen :0
Interrupted probabilistic random walk after 324814 steps, run timeout after 3001 ms. (steps per millisecond=108 ) properties seen :{}
Probabilistic random walk after 324814 steps, saw 209675 distinct states, run finished after 3002 ms. (steps per millisecond=108 ) properties seen :0
Running SMT prover for 4 properties.
[2023-04-07 08:05:06] [INFO ] Invariant cache hit.
[2023-04-07 08:05:06] [INFO ] [Real]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-04-07 08:05:06] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 0 ms returned sat
[2023-04-07 08:05:06] [INFO ] After 48ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-04-07 08:05:06] [INFO ] [Nat]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-04-07 08:05:06] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 0 ms returned sat
[2023-04-07 08:05:06] [INFO ] After 12ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-04-07 08:05:06] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-04-07 08:05:06] [INFO ] After 8ms SMT Verify possible using 6 Read/Feed constraints in natural domain returned unsat :0 sat :4
[2023-04-07 08:05:06] [INFO ] After 18ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 7 ms.
[2023-04-07 08:05:06] [INFO ] After 63ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Fused 4 Parikh solutions to 3 different solutions.
Parikh walk visited 0 properties in 3 ms.
Support contains 9 out of 18 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1 ms. Remains : 18/18 places, 21/21 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:06] [INFO ] Invariant cache hit.
[2023-04-07 08:05:06] [INFO ] Implicit Places using invariants in 25 ms returned [7, 8]
Discarding 2 places :
Implicit Place search using SMT only with invariants took 26 ms to find 2 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 1 : 16/18 places, 21/21 transitions.
Applied a total of 0 rules in 1 ms. Remains 16 /16 variables (removed 0) and now considering 21/21 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 2 iterations and 28 ms. Remains : 16/18 places, 21/21 transitions.
Incomplete random walk after 10019 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=323 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=769 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=769 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 4) seen :0
Interrupted probabilistic random walk after 406822 steps, run timeout after 3001 ms. (steps per millisecond=135 ) properties seen :{}
Probabilistic random walk after 406822 steps, saw 261582 distinct states, run finished after 3001 ms. (steps per millisecond=135 ) properties seen :0
Running SMT prover for 4 properties.
// Phase 1: matrix 21 rows 16 cols
[2023-04-07 08:05:09] [INFO ] Computed 2 invariants in 1 ms
[2023-04-07 08:05:09] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-04-07 08:05:09] [INFO ] After 35ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-04-07 08:05:09] [INFO ] [Nat]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-04-07 08:05:09] [INFO ] After 12ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-04-07 08:05:09] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-04-07 08:05:09] [INFO ] After 16ms SMT Verify possible using 6 Read/Feed constraints in natural domain returned unsat :0 sat :4
[2023-04-07 08:05:09] [INFO ] After 25ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-04-07 08:05:09] [INFO ] After 65ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Fused 4 Parikh solutions to 3 different solutions.
Parikh walk visited 0 properties in 10 ms.
Support contains 9 out of 16 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 16/16 places, 21/21 transitions.
Applied a total of 0 rules in 1 ms. Remains 16 /16 variables (removed 0) and now considering 21/21 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1 ms. Remains : 16/16 places, 21/21 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 16/16 places, 21/21 transitions.
Applied a total of 0 rules in 0 ms. Remains 16 /16 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:09] [INFO ] Invariant cache hit.
[2023-04-07 08:05:09] [INFO ] Implicit Places using invariants in 16 ms returned []
[2023-04-07 08:05:09] [INFO ] Invariant cache hit.
[2023-04-07 08:05:10] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-04-07 08:05:10] [INFO ] Implicit Places using invariants and state equation in 42 ms returned []
Implicit Place search using SMT with State Equation took 58 ms to find 0 implicit places.
[2023-04-07 08:05:10] [INFO ] Redundant transitions in 0 ms returned []
[2023-04-07 08:05:10] [INFO ] Invariant cache hit.
[2023-04-07 08:05:10] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 89 ms. Remains : 16/16 places, 21/21 transitions.
Applied a total of 0 rules in 1 ms. Remains 16 /16 variables (removed 0) and now considering 21/21 (removed 0) transitions.
Running SMT prover for 4 properties.
[2023-04-07 08:05:10] [INFO ] Invariant cache hit.
[2023-04-07 08:05:10] [INFO ] [Real]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-04-07 08:05:10] [INFO ] After 35ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-04-07 08:05:10] [INFO ] [Nat]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-04-07 08:05:10] [INFO ] After 11ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-04-07 08:05:10] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-04-07 08:05:10] [INFO ] After 6ms SMT Verify possible using 6 Read/Feed constraints in natural domain returned unsat :0 sat :4
[2023-04-07 08:05:10] [INFO ] After 17ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 8 ms.
[2023-04-07 08:05:10] [INFO ] After 62ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 3 ms
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 4 ms
[2023-04-07 08:05:10] [INFO ] Input system was already deterministic with 21 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
// Phase 1: matrix 21 rows 18 cols
[2023-04-07 08:05:10] [INFO ] Computed 4 invariants in 1 ms
[2023-04-07 08:05:10] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:10] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:10] [INFO ] Invariant cache hit.
[2023-04-07 08:05:10] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 25 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 3 ms
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 1 ms
[2023-04-07 08:05:10] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:10] [INFO ] Invariant cache hit.
[2023-04-07 08:05:10] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 29 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:10] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:10] [INFO ] Invariant cache hit.
[2023-04-07 08:05:10] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:10] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:10] [INFO ] Invariant cache hit.
[2023-04-07 08:05:10] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 1 ms
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 1 ms
[2023-04-07 08:05:10] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:10] [INFO ] Invariant cache hit.
[2023-04-07 08:05:10] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 3 ms
[2023-04-07 08:05:10] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:10] [INFO ] Input system was already deterministic with 21 transitions.
Incomplete random walk after 10014 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=1669 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=2000 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2501832 steps, run timeout after 3001 ms. (steps per millisecond=833 ) properties seen :{}
Probabilistic random walk after 2501832 steps, saw 1573478 distinct states, run finished after 3001 ms. (steps per millisecond=833 ) properties seen :0
Running SMT prover for 1 properties.
[2023-04-07 08:05:13] [INFO ] Invariant cache hit.
[2023-04-07 08:05:13] [INFO ] [Real]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-04-07 08:05:13] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 0 ms returned sat
[2023-04-07 08:05:13] [INFO ] After 32ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-04-07 08:05:13] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-04-07 08:05:13] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-04-07 08:05:13] [INFO ] After 13ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-04-07 08:05:13] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-04-07 08:05:13] [INFO ] After 3ms SMT Verify possible using 6 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-04-07 08:05:13] [INFO ] After 6ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 3 ms.
[2023-04-07 08:05:13] [INFO ] After 48ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 2 ms.
Support contains 2 out of 18 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 18/18 places, 21/21 transitions.
Graph (complete) has 69 edges and 18 vertex of which 3 are kept as prefixes of interest. Removing 15 places using SCC suffix rule.0 ms
Discarding 15 places :
Also discarding 16 output transitions
Drop transitions removed 16 transitions
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 3 transition count 4
Applied a total of 2 rules in 3 ms. Remains 3 /18 variables (removed 15) and now considering 4/21 (removed 17) transitions.
// Phase 1: matrix 4 rows 3 cols
[2023-04-07 08:05:13] [INFO ] Computed 0 invariants in 0 ms
[2023-04-07 08:05:13] [INFO ] Dead Transitions using invariants and state equation in 21 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 25 ms. Remains : 3/18 places, 4/21 transitions.
Incomplete random walk after 1000000 steps, including 2 resets, run finished after 540 ms. (steps per millisecond=1851 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000001 steps, including 2 resets, run finished after 414 ms. (steps per millisecond=2415 ) properties (out of 1) seen :0
Probably explored full state space saw : 6 states, properties seen :0
Probabilistic random walk after 14 steps, saw 6 distinct states, run finished after 4 ms. (steps per millisecond=3 ) properties seen :0
Explored full state space saw : 6 states, properties seen :0
Exhaustive walk after 14 steps, saw 6 distinct states, run finished after 1 ms. (steps per millisecond=14 ) properties seen :0
FORMULA Murphy-PT-D2N050-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
Parikh walk visited 0 properties in 0 ms.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
// Phase 1: matrix 21 rows 18 cols
[2023-04-07 08:05:14] [INFO ] Computed 4 invariants in 1 ms
[2023-04-07 08:05:14] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 1 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:14] [INFO ] Invariant cache hit.
[2023-04-07 08:05:14] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 25 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:14] [INFO ] Invariant cache hit.
[2023-04-07 08:05:14] [INFO ] Dead Transitions using invariants and state equation in 21 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 1 ms
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:14] [INFO ] Invariant cache hit.
[2023-04-07 08:05:14] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 25 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 1 ms
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:14] [INFO ] Invariant cache hit.
[2023-04-07 08:05:14] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 2 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:14] [INFO ] Invariant cache hit.
[2023-04-07 08:05:14] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 1 ms
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 1 ms
[2023-04-07 08:05:14] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:14] [INFO ] Invariant cache hit.
[2023-04-07 08:05:14] [INFO ] Dead Transitions using invariants and state equation in 20 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in LTL mode, iteration 0 : 18/18 places, 21/21 transitions.
Applied a total of 0 rules in 0 ms. Remains 18 /18 variables (removed 0) and now considering 21/21 (removed 0) transitions.
[2023-04-07 08:05:14] [INFO ] Invariant cache hit.
[2023-04-07 08:05:14] [INFO ] Dead Transitions using invariants and state equation in 21 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 18/18 places, 21/21 transitions.
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 1 ms
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Input system was already deterministic with 21 transitions.
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 2 ms
[2023-04-07 08:05:14] [INFO ] Flatten gal took : 1 ms
[2023-04-07 08:05:14] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-04-07 08:05:14] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 18 places, 21 transitions and 81 arcs took 0 ms.
Total runtime 12604 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Murphy-PT-D2N050
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA Murphy-PT-D2N050-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Murphy-PT-D2N050-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Murphy-PT-D2N050-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Murphy-PT-D2N050-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1680854931123

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 4 (type EXCL) for 3 Murphy-PT-D2N050-CTLFireability-01
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/240 8/32 Murphy-PT-D2N050-CTLFireability-01 1758363 m, 351672 m/sec, 6963633 t fired, .

Time elapsed: 5 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/240 13/32 Murphy-PT-D2N050-CTLFireability-01 3033540 m, 255035 m/sec, 12729509 t fired, .

Time elapsed: 10 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/240 20/32 Murphy-PT-D2N050-CTLFireability-01 4645040 m, 322300 m/sec, 18664749 t fired, .

Time elapsed: 15 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/240 26/32 Murphy-PT-D2N050-CTLFireability-01 6141782 m, 299348 m/sec, 24898814 t fired, .

Time elapsed: 20 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/240 31/32 Murphy-PT-D2N050-CTLFireability-01 7310990 m, 233841 m/sec, 30966525 t fired, .

Time elapsed: 25 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 4 (type EXCL) for Murphy-PT-D2N050-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 45 (type EXCL) for 44 Murphy-PT-D2N050-CTLFireability-15
lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for Murphy-PT-D2N050-CTLFireability-15
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 Murphy-PT-D2N050-CTLFireability-13
lola: time limit : 274 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/274 8/32 Murphy-PT-D2N050-CTLFireability-13 1841796 m, 368359 m/sec, 6891108 t fired, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/274 15/32 Murphy-PT-D2N050-CTLFireability-13 3423285 m, 316297 m/sec, 13324874 t fired, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 15/274 21/32 Murphy-PT-D2N050-CTLFireability-13 4826094 m, 280561 m/sec, 19669558 t fired, .

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 20/274 27/32 Murphy-PT-D2N050-CTLFireability-13 6288834 m, 292548 m/sec, 25935591 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 42 (type EXCL) for Murphy-PT-D2N050-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 36 (type EXCL) for 31 Murphy-PT-D2N050-CTLFireability-11
lola: time limit : 295 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for Murphy-PT-D2N050-CTLFireability-11
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 Murphy-PT-D2N050-CTLFireability-10
lola: time limit : 354 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for Murphy-PT-D2N050-CTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 Murphy-PT-D2N050-CTLFireability-08
lola: time limit : 393 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 5/393 12/32 Murphy-PT-D2N050-CTLFireability-08 2645036 m, 529007 m/sec, 6735876 t fired, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 10/393 21/32 Murphy-PT-D2N050-CTLFireability-08 4835515 m, 438095 m/sec, 12728731 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 15/393 31/32 Murphy-PT-D2N050-CTLFireability-08 7154562 m, 463809 m/sec, 18887442 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 26 (type EXCL) for Murphy-PT-D2N050-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 23 (type EXCL) for 18 Murphy-PT-D2N050-CTLFireability-07
lola: time limit : 440 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for Murphy-PT-D2N050-CTLFireability-07
lola: result : false
lola: markings : 4
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 Murphy-PT-D2N050-CTLFireability-06
lola: time limit : 503 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/503 14/32 Murphy-PT-D2N050-CTLFireability-06 3124561 m, 624912 m/sec, 5707769 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/503 25/32 Murphy-PT-D2N050-CTLFireability-06 5867786 m, 548645 m/sec, 10722250 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 16 (type EXCL) for Murphy-PT-D2N050-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 1 (type EXCL) for 0 Murphy-PT-D2N050-CTLFireability-00
lola: time limit : 585 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/585 12/32 Murphy-PT-D2N050-CTLFireability-00 2632821 m, 526564 m/sec, 8344091 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/585 22/32 Murphy-PT-D2N050-CTLFireability-00 5056901 m, 484816 m/sec, 16027969 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/585 31/32 Murphy-PT-D2N050-CTLFireability-00 7371989 m, 463017 m/sec, 23357888 t fired, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 1 (type EXCL) for Murphy-PT-D2N050-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 47 (type EXCL) for 38 Murphy-PT-D2N050-CTLFireability-12
lola: time limit : 698 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for Murphy-PT-D2N050-CTLFireability-12
lola: result : true
lola: markings : 7
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 Murphy-PT-D2N050-CTLFireability-04
lola: time limit : 872 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/872 7/32 Murphy-PT-D2N050-CTLFireability-04 1518841 m, 303768 m/sec, 7301771 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/872 12/32 Murphy-PT-D2N050-CTLFireability-04 2810757 m, 258383 m/sec, 13882604 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/872 17/32 Murphy-PT-D2N050-CTLFireability-04 3944527 m, 226754 m/sec, 20250020 t fired, .

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/872 22/32 Murphy-PT-D2N050-CTLFireability-04 5148684 m, 240831 m/sec, 26626977 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/872 28/32 Murphy-PT-D2N050-CTLFireability-04 6438295 m, 257922 m/sec, 33054598 t fired, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 13 (type EXCL) for Murphy-PT-D2N050-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 7 (type EXCL) for 6 Murphy-PT-D2N050-CTLFireability-02
lola: time limit : 1153 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/1153 8/32 Murphy-PT-D2N050-CTLFireability-02 1663304 m, 332660 m/sec, 8883598 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/1153 14/32 Murphy-PT-D2N050-CTLFireability-02 3171901 m, 301719 m/sec, 16968471 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/1153 20/32 Murphy-PT-D2N050-CTLFireability-02 4636341 m, 292888 m/sec, 24803537 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/1153 26/32 Murphy-PT-D2N050-CTLFireability-02 6046909 m, 282113 m/sec, 32363663 t fired, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/1153 32/32 Murphy-PT-D2N050-CTLFireability-02 7460231 m, 282664 m/sec, 39920032 t fired, .

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 7 (type EXCL) for Murphy-PT-D2N050-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 1 0 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 21 (type EXCL) for 18 Murphy-PT-D2N050-CTLFireability-07
lola: time limit : 1715 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 0 1 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 5/1715 9/32 Murphy-PT-D2N050-CTLFireability-07 2131585 m, 426317 m/sec, 7267595 t fired, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 0 1 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 10/1715 17/32 Murphy-PT-D2N050-CTLFireability-07 4009759 m, 375634 m/sec, 13449909 t fired, .

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 0 1 0 3 0 0 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 15/1715 25/32 Murphy-PT-D2N050-CTLFireability-07 5832504 m, 364549 m/sec, 19456833 t fired, .

Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 21 (type EXCL) for Murphy-PT-D2N050-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 0 0 0 3 0 1 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 10 (type EXCL) for 9 Murphy-PT-D2N050-CTLFireability-03
lola: time limit : 3410 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 0 0 0 3 0 1 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/3410 8/32 Murphy-PT-D2N050-CTLFireability-03 1792807 m, 358561 m/sec, 8713136 t fired, .

Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 0 0 0 3 0 1 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/3410 15/32 Murphy-PT-D2N050-CTLFireability-03 3427381 m, 326914 m/sec, 16620745 t fired, .

Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 0 0 0 3 0 1 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/3410 22/32 Murphy-PT-D2N050-CTLFireability-03 5019668 m, 318457 m/sec, 24353319 t fired, .

Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 0 0 0 3 0 1 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/3410 28/32 Murphy-PT-D2N050-CTLFireability-03 6565307 m, 309127 m/sec, 31832632 t fired, .

Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 10 (type EXCL) for Murphy-PT-D2N050-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Murphy-PT-D2N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-07: DISJ 0 0 0 0 3 0 1 0
Murphy-PT-D2N050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Murphy-PT-D2N050-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: Portfolio finished: no open tasks 13

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Murphy-PT-D2N050-CTLFireability-00: CTL unknown AGGR
Murphy-PT-D2N050-CTLFireability-01: CTL unknown AGGR
Murphy-PT-D2N050-CTLFireability-02: CTL unknown AGGR
Murphy-PT-D2N050-CTLFireability-03: CTL unknown AGGR
Murphy-PT-D2N050-CTLFireability-04: CTL unknown AGGR
Murphy-PT-D2N050-CTLFireability-06: CTL unknown AGGR
Murphy-PT-D2N050-CTLFireability-07: DISJ unknown DISJ
Murphy-PT-D2N050-CTLFireability-08: CTL unknown AGGR
Murphy-PT-D2N050-CTLFireability-10: CTL true CTL model checker
Murphy-PT-D2N050-CTLFireability-11: DISJ true CTL model checker
Murphy-PT-D2N050-CTLFireability-12: AGAF false state space /EFEG
Murphy-PT-D2N050-CTLFireability-13: CTL unknown AGGR
Murphy-PT-D2N050-CTLFireability-15: CTL true CTL model checker


Time elapsed: 215 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Murphy-PT-D2N050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Murphy-PT-D2N050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r519-tall-167987245100338"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Murphy-PT-D2N050.tgz
mv Murphy-PT-D2N050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;