About the Execution of LoLa+red for Anderson-PT-08
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
3023.396 | 223351.00 | 318498.00 | 2264.80 | FT?FF?T?TFFTFFT? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r519-tall-167987244700034.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Anderson-PT-08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r519-tall-167987244700034
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 5.5K Mar 23 15:19 CTLCardinality.txt
-rw-r--r-- 1 mcc users 50K Mar 23 15:19 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.0K Mar 23 15:18 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Mar 23 15:18 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Mar 23 07:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 23 07:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Mar 23 07:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 23 07:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 17K Mar 23 15:20 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 170K Mar 23 15:20 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Mar 23 15:19 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Mar 23 15:19 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 23 07:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 23 07:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 667K Mar 31 16:48 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Anderson-PT-08-CTLFireability-00
FORMULA_NAME Anderson-PT-08-CTLFireability-01
FORMULA_NAME Anderson-PT-08-CTLFireability-02
FORMULA_NAME Anderson-PT-08-CTLFireability-03
FORMULA_NAME Anderson-PT-08-CTLFireability-04
FORMULA_NAME Anderson-PT-08-CTLFireability-05
FORMULA_NAME Anderson-PT-08-CTLFireability-06
FORMULA_NAME Anderson-PT-08-CTLFireability-07
FORMULA_NAME Anderson-PT-08-CTLFireability-08
FORMULA_NAME Anderson-PT-08-CTLFireability-09
FORMULA_NAME Anderson-PT-08-CTLFireability-10
FORMULA_NAME Anderson-PT-08-CTLFireability-11
FORMULA_NAME Anderson-PT-08-CTLFireability-12
FORMULA_NAME Anderson-PT-08-CTLFireability-13
FORMULA_NAME Anderson-PT-08-CTLFireability-14
FORMULA_NAME Anderson-PT-08-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1680828474816
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Anderson-PT-08
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2023-04-07 00:47:56] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-04-07 00:47:56] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-04-07 00:47:56] [INFO ] Load time of PNML (sax parser for PT used): 99 ms
[2023-04-07 00:47:56] [INFO ] Transformed 401 places.
[2023-04-07 00:47:56] [INFO ] Transformed 1328 transitions.
[2023-04-07 00:47:56] [INFO ] Found NUPN structural information;
[2023-04-07 00:47:56] [INFO ] Parsed PT model containing 401 places and 1328 transitions and 5088 arcs in 166 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 107 out of 401 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 401/401 places, 1328/1328 transitions.
Discarding 54 places :
Symmetric choice reduction at 0 with 54 rule applications. Total rules 54 place count 347 transition count 1148
Iterating global reduction 0 with 54 rules applied. Total rules applied 108 place count 347 transition count 1148
Applied a total of 108 rules in 58 ms. Remains 347 /401 variables (removed 54) and now considering 1148/1328 (removed 180) transitions.
// Phase 1: matrix 1148 rows 347 cols
[2023-04-07 00:47:56] [INFO ] Computed 19 invariants in 45 ms
[2023-04-07 00:47:56] [INFO ] Implicit Places using invariants in 350 ms returned []
[2023-04-07 00:47:56] [INFO ] Invariant cache hit.
[2023-04-07 00:47:57] [INFO ] State equation strengthened by 56 read => feed constraints.
[2023-04-07 00:47:57] [INFO ] Implicit Places using invariants and state equation in 980 ms returned []
Implicit Place search using SMT with State Equation took 1353 ms to find 0 implicit places.
[2023-04-07 00:47:57] [INFO ] Invariant cache hit.
[2023-04-07 00:47:58] [INFO ] Dead Transitions using invariants and state equation in 514 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 347/401 places, 1148/1328 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1930 ms. Remains : 347/401 places, 1148/1328 transitions.
Support contains 107 out of 347 places after structural reductions.
[2023-04-07 00:47:58] [INFO ] Flatten gal took : 191 ms
[2023-04-07 00:47:58] [INFO ] Flatten gal took : 79 ms
[2023-04-07 00:47:58] [INFO ] Input system was already deterministic with 1148 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 555 ms. (steps per millisecond=18 ) properties (out of 102) seen :39
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 63) seen :7
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 56) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 53) seen :4
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 49) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 46) seen :2
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 44) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 40) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 37) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :3
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 33) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 32) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 31) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 29) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 28) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 28) seen :2
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 26) seen :3
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 23) seen :0
Running SMT prover for 23 properties.
[2023-04-07 00:47:59] [INFO ] Invariant cache hit.
[2023-04-07 00:48:00] [INFO ] [Real]Absence check using 9 positive place invariants in 6 ms returned sat
[2023-04-07 00:48:00] [INFO ] [Real]Absence check using 9 positive and 10 generalized place invariants in 13 ms returned sat
[2023-04-07 00:48:00] [INFO ] After 599ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:22
[2023-04-07 00:48:00] [INFO ] [Nat]Absence check using 9 positive place invariants in 6 ms returned sat
[2023-04-07 00:48:00] [INFO ] [Nat]Absence check using 9 positive and 10 generalized place invariants in 14 ms returned sat
[2023-04-07 00:48:02] [INFO ] After 1610ms SMT Verify possible using state equation in natural domain returned unsat :7 sat :16
[2023-04-07 00:48:02] [INFO ] State equation strengthened by 56 read => feed constraints.
[2023-04-07 00:48:03] [INFO ] After 1468ms SMT Verify possible using 56 Read/Feed constraints in natural domain returned unsat :7 sat :16
[2023-04-07 00:48:05] [INFO ] After 3136ms SMT Verify possible using trap constraints in natural domain returned unsat :7 sat :16
Attempting to minimize the solution found.
Minimization took 1271 ms.
[2023-04-07 00:48:06] [INFO ] After 6319ms SMT Verify possible using all constraints in natural domain returned unsat :7 sat :16
Fused 23 Parikh solutions to 16 different solutions.
Parikh walk visited 0 properties in 306 ms.
Support contains 23 out of 347 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Performed 56 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 56 Pre rules applied. Total rules applied 0 place count 347 transition count 1092
Deduced a syphon composed of 56 places in 1 ms
Reduce places removed 56 places and 0 transitions.
Iterating global reduction 0 with 112 rules applied. Total rules applied 112 place count 291 transition count 1092
Discarding 41 places :
Symmetric choice reduction at 0 with 41 rule applications. Total rules 153 place count 250 transition count 631
Iterating global reduction 0 with 41 rules applied. Total rules applied 194 place count 250 transition count 631
Applied a total of 194 rules in 75 ms. Remains 250 /347 variables (removed 97) and now considering 631/1148 (removed 517) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 75 ms. Remains : 250/347 places, 631/1148 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 199 ms. (steps per millisecond=50 ) properties (out of 16) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 15) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 14) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 13) seen :1
Running SMT prover for 12 properties.
// Phase 1: matrix 631 rows 250 cols
[2023-04-07 00:48:07] [INFO ] Computed 19 invariants in 8 ms
[2023-04-07 00:48:07] [INFO ] [Real]Absence check using 9 positive place invariants in 9 ms returned sat
[2023-04-07 00:48:07] [INFO ] [Real]Absence check using 9 positive and 10 generalized place invariants in 10 ms returned sat
[2023-04-07 00:48:07] [INFO ] After 304ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:12
[2023-04-07 00:48:07] [INFO ] [Nat]Absence check using 9 positive place invariants in 4 ms returned sat
[2023-04-07 00:48:07] [INFO ] [Nat]Absence check using 9 positive and 10 generalized place invariants in 9 ms returned sat
[2023-04-07 00:48:08] [INFO ] After 638ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :12
[2023-04-07 00:48:08] [INFO ] State equation strengthened by 56 read => feed constraints.
[2023-04-07 00:48:09] [INFO ] After 571ms SMT Verify possible using 56 Read/Feed constraints in natural domain returned unsat :0 sat :12
[2023-04-07 00:48:09] [INFO ] After 1276ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :12
Attempting to minimize the solution found.
Minimization took 494 ms.
[2023-04-07 00:48:10] [INFO ] After 2551ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :12
Parikh walk visited 2 properties in 107 ms.
Support contains 17 out of 250 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 250/250 places, 631/631 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 245 transition count 556
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 245 transition count 556
Applied a total of 10 rules in 24 ms. Remains 245 /250 variables (removed 5) and now considering 556/631 (removed 75) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 24 ms. Remains : 245/250 places, 556/631 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 137 ms. (steps per millisecond=72 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 72 ms. (steps per millisecond=138 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 59 ms. (steps per millisecond=169 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 74 ms. (steps per millisecond=135 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 10) seen :0
Interrupted probabilistic random walk after 262654 steps, run timeout after 3001 ms. (steps per millisecond=87 ) properties seen :{2=1}
Probabilistic random walk after 262654 steps, saw 172361 distinct states, run finished after 3002 ms. (steps per millisecond=87 ) properties seen :1
Running SMT prover for 9 properties.
// Phase 1: matrix 556 rows 245 cols
[2023-04-07 00:48:14] [INFO ] Computed 19 invariants in 4 ms
[2023-04-07 00:48:14] [INFO ] [Real]Absence check using 9 positive place invariants in 4 ms returned sat
[2023-04-07 00:48:14] [INFO ] [Real]Absence check using 9 positive and 10 generalized place invariants in 8 ms returned sat
[2023-04-07 00:48:14] [INFO ] After 246ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:9
[2023-04-07 00:48:14] [INFO ] [Nat]Absence check using 9 positive place invariants in 3 ms returned sat
[2023-04-07 00:48:14] [INFO ] [Nat]Absence check using 9 positive and 10 generalized place invariants in 7 ms returned sat
[2023-04-07 00:48:15] [INFO ] After 506ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :9
[2023-04-07 00:48:15] [INFO ] State equation strengthened by 56 read => feed constraints.
[2023-04-07 00:48:15] [INFO ] After 364ms SMT Verify possible using 56 Read/Feed constraints in natural domain returned unsat :0 sat :9
[2023-04-07 00:48:16] [INFO ] After 800ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :9
Attempting to minimize the solution found.
Minimization took 316 ms.
[2023-04-07 00:48:16] [INFO ] After 1750ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :9
Parikh walk visited 0 properties in 65 ms.
Support contains 16 out of 245 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 245/245 places, 556/556 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 244 transition count 541
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 244 transition count 541
Applied a total of 2 rules in 19 ms. Remains 244 /245 variables (removed 1) and now considering 541/556 (removed 15) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 20 ms. Remains : 244/245 places, 541/556 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 158 ms. (steps per millisecond=63 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 64 ms. (steps per millisecond=156 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 58 ms. (steps per millisecond=172 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 9) seen :0
Interrupted probabilistic random walk after 266641 steps, run timeout after 3001 ms. (steps per millisecond=88 ) properties seen :{7=1}
Probabilistic random walk after 266641 steps, saw 175775 distinct states, run finished after 3002 ms. (steps per millisecond=88 ) properties seen :1
Running SMT prover for 8 properties.
// Phase 1: matrix 541 rows 244 cols
[2023-04-07 00:48:20] [INFO ] Computed 19 invariants in 4 ms
[2023-04-07 00:48:20] [INFO ] [Real]Absence check using 9 positive place invariants in 3 ms returned sat
[2023-04-07 00:48:20] [INFO ] [Real]Absence check using 9 positive and 10 generalized place invariants in 10 ms returned sat
[2023-04-07 00:48:20] [INFO ] After 239ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:8
[2023-04-07 00:48:20] [INFO ] [Nat]Absence check using 9 positive place invariants in 4 ms returned sat
[2023-04-07 00:48:20] [INFO ] [Nat]Absence check using 9 positive and 10 generalized place invariants in 11 ms returned sat
[2023-04-07 00:48:20] [INFO ] After 423ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :8
[2023-04-07 00:48:20] [INFO ] State equation strengthened by 56 read => feed constraints.
[2023-04-07 00:48:21] [INFO ] After 298ms SMT Verify possible using 56 Read/Feed constraints in natural domain returned unsat :0 sat :8
[2023-04-07 00:48:21] [INFO ] After 675ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :8
Attempting to minimize the solution found.
Minimization took 275 ms.
[2023-04-07 00:48:21] [INFO ] After 1494ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :8
Parikh walk visited 0 properties in 20 ms.
Support contains 14 out of 244 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 244/244 places, 541/541 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 243 transition count 526
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 243 transition count 526
Applied a total of 2 rules in 19 ms. Remains 243 /244 variables (removed 1) and now considering 526/541 (removed 15) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 19 ms. Remains : 243/244 places, 526/541 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 148 ms. (steps per millisecond=67 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 69 ms. (steps per millisecond=144 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 8) seen :0
Interrupted probabilistic random walk after 321686 steps, run timeout after 3001 ms. (steps per millisecond=107 ) properties seen :{1=1}
Probabilistic random walk after 321686 steps, saw 211316 distinct states, run finished after 3001 ms. (steps per millisecond=107 ) properties seen :1
Running SMT prover for 7 properties.
// Phase 1: matrix 526 rows 243 cols
[2023-04-07 00:48:25] [INFO ] Computed 19 invariants in 7 ms
[2023-04-07 00:48:25] [INFO ] [Real]Absence check using 9 positive place invariants in 4 ms returned sat
[2023-04-07 00:48:25] [INFO ] [Real]Absence check using 9 positive and 10 generalized place invariants in 18 ms returned sat
[2023-04-07 00:48:26] [INFO ] After 447ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:7
[2023-04-07 00:48:26] [INFO ] [Nat]Absence check using 9 positive place invariants in 4 ms returned sat
[2023-04-07 00:48:26] [INFO ] [Nat]Absence check using 9 positive and 10 generalized place invariants in 11 ms returned sat
[2023-04-07 00:48:26] [INFO ] After 330ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :7
[2023-04-07 00:48:26] [INFO ] State equation strengthened by 56 read => feed constraints.
[2023-04-07 00:48:26] [INFO ] After 301ms SMT Verify possible using 56 Read/Feed constraints in natural domain returned unsat :0 sat :7
[2023-04-07 00:48:27] [INFO ] After 609ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :7
Attempting to minimize the solution found.
Minimization took 212 ms.
[2023-04-07 00:48:27] [INFO ] After 1262ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :7
Parikh walk visited 0 properties in 31 ms.
Support contains 9 out of 243 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 243/243 places, 526/526 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 240 transition count 481
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 240 transition count 481
Applied a total of 6 rules in 16 ms. Remains 240 /243 variables (removed 3) and now considering 481/526 (removed 45) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 17 ms. Remains : 240/243 places, 481/526 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 227 ms. (steps per millisecond=44 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 107 ms. (steps per millisecond=93 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 7) seen :0
Interrupted probabilistic random walk after 400077 steps, run timeout after 3001 ms. (steps per millisecond=133 ) properties seen :{0=1, 1=1, 4=1, 5=1, 6=1}
Probabilistic random walk after 400077 steps, saw 261872 distinct states, run finished after 3001 ms. (steps per millisecond=133 ) properties seen :5
Running SMT prover for 2 properties.
// Phase 1: matrix 481 rows 240 cols
[2023-04-07 00:48:30] [INFO ] Computed 19 invariants in 4 ms
[2023-04-07 00:48:31] [INFO ] [Real]Absence check using 9 positive place invariants in 3 ms returned sat
[2023-04-07 00:48:31] [INFO ] [Real]Absence check using 9 positive and 10 generalized place invariants in 9 ms returned sat
[2023-04-07 00:48:31] [INFO ] After 176ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:1
[2023-04-07 00:48:31] [INFO ] State equation strengthened by 56 read => feed constraints.
[2023-04-07 00:48:31] [INFO ] After 48ms SMT Verify possible using 56 Read/Feed constraints in real domain returned unsat :0 sat :0 real:2
[2023-04-07 00:48:31] [INFO ] After 291ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-04-07 00:48:31] [INFO ] [Nat]Absence check using 9 positive place invariants in 4 ms returned sat
[2023-04-07 00:48:31] [INFO ] [Nat]Absence check using 9 positive and 10 generalized place invariants in 9 ms returned sat
[2023-04-07 00:48:31] [INFO ] After 170ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-04-07 00:48:31] [INFO ] After 137ms SMT Verify possible using 56 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-04-07 00:48:31] [INFO ] After 246ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 59 ms.
[2023-04-07 00:48:31] [INFO ] After 553ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 8 ms.
Support contains 4 out of 240 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 240/240 places, 481/481 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 235 transition count 406
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 235 transition count 406
Applied a total of 10 rules in 12 ms. Remains 235 /240 variables (removed 5) and now considering 406/481 (removed 75) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 12 ms. Remains : 235/240 places, 406/481 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 58 ms. (steps per millisecond=172 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 644315 steps, run timeout after 3001 ms. (steps per millisecond=214 ) properties seen :{1=1}
Probabilistic random walk after 644315 steps, saw 423913 distinct states, run finished after 3001 ms. (steps per millisecond=214 ) properties seen :1
Running SMT prover for 1 properties.
// Phase 1: matrix 406 rows 235 cols
[2023-04-07 00:48:34] [INFO ] Computed 19 invariants in 6 ms
[2023-04-07 00:48:34] [INFO ] [Real]Absence check using 10 positive place invariants in 4 ms returned sat
[2023-04-07 00:48:34] [INFO ] [Real]Absence check using 10 positive and 9 generalized place invariants in 7 ms returned sat
[2023-04-07 00:48:35] [INFO ] After 173ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-04-07 00:48:35] [INFO ] [Nat]Absence check using 10 positive place invariants in 4 ms returned sat
[2023-04-07 00:48:35] [INFO ] [Nat]Absence check using 10 positive and 9 generalized place invariants in 7 ms returned sat
[2023-04-07 00:48:35] [INFO ] After 110ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-04-07 00:48:35] [INFO ] State equation strengthened by 56 read => feed constraints.
[2023-04-07 00:48:35] [INFO ] After 81ms SMT Verify possible using 56 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-04-07 00:48:35] [INFO ] After 117ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 26 ms.
[2023-04-07 00:48:35] [INFO ] After 310ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 2 out of 235 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 235/235 places, 406/406 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 234 transition count 391
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 234 transition count 391
Applied a total of 2 rules in 19 ms. Remains 234 /235 variables (removed 1) and now considering 391/406 (removed 15) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 20 ms. Remains : 234/235 places, 391/406 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=1250 ) properties (out of 1) seen :0
Finished probabilistic random walk after 756153 steps, run visited all 1 properties in 1666 ms. (steps per millisecond=453 )
Probabilistic random walk after 756153 steps, saw 491539 distinct states, run finished after 1666 ms. (steps per millisecond=453 ) properties seen :1
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 7 atomic propositions for a total of 16 simplifications.
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 47 ms
[2023-04-07 00:48:37] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA Anderson-PT-08-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 48 ms
[2023-04-07 00:48:37] [INFO ] Input system was already deterministic with 1148 transitions.
Support contains 98 out of 347 places (down from 102) after GAL structural reductions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Performed 56 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 56 Pre rules applied. Total rules applied 0 place count 347 transition count 1092
Deduced a syphon composed of 56 places in 0 ms
Reduce places removed 56 places and 0 transitions.
Iterating global reduction 0 with 112 rules applied. Total rules applied 112 place count 291 transition count 1092
Discarding 57 places :
Symmetric choice reduction at 0 with 57 rule applications. Total rules 169 place count 234 transition count 391
Iterating global reduction 0 with 57 rules applied. Total rules applied 226 place count 234 transition count 391
Applied a total of 226 rules in 25 ms. Remains 234 /347 variables (removed 113) and now considering 391/1148 (removed 757) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 234/347 places, 391/1148 transitions.
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 13 ms
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 13 ms
[2023-04-07 00:48:37] [INFO ] Input system was already deterministic with 391 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Performed 55 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 55 Pre rules applied. Total rules applied 0 place count 347 transition count 1093
Deduced a syphon composed of 55 places in 0 ms
Reduce places removed 55 places and 0 transitions.
Iterating global reduction 0 with 110 rules applied. Total rules applied 110 place count 292 transition count 1093
Discarding 53 places :
Symmetric choice reduction at 0 with 53 rule applications. Total rules 163 place count 239 transition count 452
Iterating global reduction 0 with 53 rules applied. Total rules applied 216 place count 239 transition count 452
Applied a total of 216 rules in 23 ms. Remains 239 /347 variables (removed 108) and now considering 452/1148 (removed 696) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 239/347 places, 452/1148 transitions.
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 13 ms
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 14 ms
[2023-04-07 00:48:37] [INFO ] Input system was already deterministic with 452 transitions.
Starting structural reductions in LTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Discarding 55 places :
Symmetric choice reduction at 0 with 55 rule applications. Total rules 55 place count 292 transition count 477
Iterating global reduction 0 with 55 rules applied. Total rules applied 110 place count 292 transition count 477
Applied a total of 110 rules in 6 ms. Remains 292 /347 variables (removed 55) and now considering 477/1148 (removed 671) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 292/347 places, 477/1148 transitions.
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 13 ms
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 14 ms
[2023-04-07 00:48:37] [INFO ] Input system was already deterministic with 477 transitions.
Starting structural reductions in LTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Discarding 53 places :
Symmetric choice reduction at 0 with 53 rule applications. Total rules 53 place count 294 transition count 493
Iterating global reduction 0 with 53 rules applied. Total rules applied 106 place count 294 transition count 493
Applied a total of 106 rules in 7 ms. Remains 294 /347 variables (removed 53) and now considering 493/1148 (removed 655) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 294/347 places, 493/1148 transitions.
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 14 ms
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 15 ms
[2023-04-07 00:48:37] [INFO ] Input system was already deterministic with 493 transitions.
Starting structural reductions in LTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Discarding 51 places :
Symmetric choice reduction at 0 with 51 rule applications. Total rules 51 place count 296 transition count 537
Iterating global reduction 0 with 51 rules applied. Total rules applied 102 place count 296 transition count 537
Applied a total of 102 rules in 6 ms. Remains 296 /347 variables (removed 51) and now considering 537/1148 (removed 611) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 296/347 places, 537/1148 transitions.
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 16 ms
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 17 ms
[2023-04-07 00:48:37] [INFO ] Input system was already deterministic with 537 transitions.
Starting structural reductions in LTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Discarding 42 places :
Symmetric choice reduction at 0 with 42 rule applications. Total rules 42 place count 305 transition count 672
Iterating global reduction 0 with 42 rules applied. Total rules applied 84 place count 305 transition count 672
Applied a total of 84 rules in 7 ms. Remains 305 /347 variables (removed 42) and now considering 672/1148 (removed 476) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 305/347 places, 672/1148 transitions.
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 20 ms
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 21 ms
[2023-04-07 00:48:37] [INFO ] Input system was already deterministic with 672 transitions.
Starting structural reductions in LTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Discarding 56 places :
Symmetric choice reduction at 0 with 56 rule applications. Total rules 56 place count 291 transition count 462
Iterating global reduction 0 with 56 rules applied. Total rules applied 112 place count 291 transition count 462
Applied a total of 112 rules in 7 ms. Remains 291 /347 variables (removed 56) and now considering 462/1148 (removed 686) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 291/347 places, 462/1148 transitions.
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 13 ms
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 14 ms
[2023-04-07 00:48:37] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Discarding 43 places :
Symmetric choice reduction at 0 with 43 rule applications. Total rules 43 place count 304 transition count 615
Iterating global reduction 0 with 43 rules applied. Total rules applied 86 place count 304 transition count 615
Applied a total of 86 rules in 7 ms. Remains 304 /347 variables (removed 43) and now considering 615/1148 (removed 533) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 304/347 places, 615/1148 transitions.
[2023-04-07 00:48:37] [INFO ] Flatten gal took : 17 ms
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 19 ms
[2023-04-07 00:48:38] [INFO ] Input system was already deterministic with 615 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Performed 54 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 54 Pre rules applied. Total rules applied 0 place count 347 transition count 1094
Deduced a syphon composed of 54 places in 1 ms
Reduce places removed 54 places and 0 transitions.
Iterating global reduction 0 with 108 rules applied. Total rules applied 108 place count 293 transition count 1094
Discarding 54 places :
Symmetric choice reduction at 0 with 54 rule applications. Total rules 162 place count 239 transition count 424
Iterating global reduction 0 with 54 rules applied. Total rules applied 216 place count 239 transition count 424
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 218 place count 238 transition count 423
Applied a total of 218 rules in 24 ms. Remains 238 /347 variables (removed 109) and now considering 423/1148 (removed 725) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 238/347 places, 423/1148 transitions.
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 12 ms
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 13 ms
[2023-04-07 00:48:38] [INFO ] Input system was already deterministic with 423 transitions.
Starting structural reductions in LTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Discarding 57 places :
Symmetric choice reduction at 0 with 57 rule applications. Total rules 57 place count 290 transition count 447
Iterating global reduction 0 with 57 rules applied. Total rules applied 114 place count 290 transition count 447
Applied a total of 114 rules in 7 ms. Remains 290 /347 variables (removed 57) and now considering 447/1148 (removed 701) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 290/347 places, 447/1148 transitions.
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 11 ms
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 13 ms
[2023-04-07 00:48:38] [INFO ] Input system was already deterministic with 447 transitions.
Starting structural reductions in LTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Discarding 49 places :
Symmetric choice reduction at 0 with 49 rule applications. Total rules 49 place count 298 transition count 539
Iterating global reduction 0 with 49 rules applied. Total rules applied 98 place count 298 transition count 539
Applied a total of 98 rules in 7 ms. Remains 298 /347 variables (removed 49) and now considering 539/1148 (removed 609) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 298/347 places, 539/1148 transitions.
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 14 ms
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 15 ms
[2023-04-07 00:48:38] [INFO ] Input system was already deterministic with 539 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Performed 56 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 56 Pre rules applied. Total rules applied 0 place count 347 transition count 1092
Deduced a syphon composed of 56 places in 1 ms
Reduce places removed 56 places and 0 transitions.
Iterating global reduction 0 with 112 rules applied. Total rules applied 112 place count 291 transition count 1092
Discarding 57 places :
Symmetric choice reduction at 0 with 57 rule applications. Total rules 169 place count 234 transition count 391
Iterating global reduction 0 with 57 rules applied. Total rules applied 226 place count 234 transition count 391
Applied a total of 226 rules in 25 ms. Remains 234 /347 variables (removed 113) and now considering 391/1148 (removed 757) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 234/347 places, 391/1148 transitions.
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 10 ms
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 12 ms
[2023-04-07 00:48:38] [INFO ] Input system was already deterministic with 391 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=1000 ) properties (out of 1) seen :0
Finished probabilistic random walk after 34570 steps, run visited all 1 properties in 84 ms. (steps per millisecond=411 )
Probabilistic random walk after 34570 steps, saw 25509 distinct states, run finished after 84 ms. (steps per millisecond=411 ) properties seen :1
FORMULA Anderson-PT-08-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
Parikh walk visited 0 properties in 0 ms.
Starting structural reductions in LTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 299 transition count 554
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 299 transition count 554
Applied a total of 96 rules in 13 ms. Remains 299 /347 variables (removed 48) and now considering 554/1148 (removed 594) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 299/347 places, 554/1148 transitions.
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 17 ms
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 17 ms
[2023-04-07 00:48:38] [INFO ] Input system was already deterministic with 554 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Performed 56 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 56 Pre rules applied. Total rules applied 0 place count 347 transition count 1092
Deduced a syphon composed of 56 places in 1 ms
Reduce places removed 56 places and 0 transitions.
Iterating global reduction 0 with 112 rules applied. Total rules applied 112 place count 291 transition count 1092
Discarding 57 places :
Symmetric choice reduction at 0 with 57 rule applications. Total rules 169 place count 234 transition count 391
Iterating global reduction 0 with 57 rules applied. Total rules applied 226 place count 234 transition count 391
Applied a total of 226 rules in 24 ms. Remains 234 /347 variables (removed 113) and now considering 391/1148 (removed 757) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 234/347 places, 391/1148 transitions.
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 10 ms
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 12 ms
[2023-04-07 00:48:38] [INFO ] Input system was already deterministic with 391 transitions.
Starting structural reductions in LTL mode, iteration 0 : 347/347 places, 1148/1148 transitions.
Discarding 54 places :
Symmetric choice reduction at 0 with 54 rule applications. Total rules 54 place count 293 transition count 492
Iterating global reduction 0 with 54 rules applied. Total rules applied 108 place count 293 transition count 492
Applied a total of 108 rules in 12 ms. Remains 293 /347 variables (removed 54) and now considering 492/1148 (removed 656) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 293/347 places, 492/1148 transitions.
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 12 ms
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 13 ms
[2023-04-07 00:48:38] [INFO ] Input system was already deterministic with 492 transitions.
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 32 ms
[2023-04-07 00:48:38] [INFO ] Flatten gal took : 33 ms
[2023-04-07 00:48:38] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-04-07 00:48:38] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 347 places, 1148 transitions and 4458 arcs took 5 ms.
Total runtime 42633 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Anderson-PT-08
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
FORMULA Anderson-PT-08-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Anderson-PT-08-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Anderson-PT-08-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Anderson-PT-08-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Anderson-PT-08-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Anderson-PT-08-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Anderson-PT-08-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Anderson-PT-08-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Anderson-PT-08-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Anderson-PT-08-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1680828698167
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 6 (type EXCL) for 3 Anderson-PT-08-CTLFireability-01
lola: time limit : 79 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 95 (type FNDP) for 58 Anderson-PT-08-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 98 (type EQUN) for 58 Anderson-PT-08-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 101 (type SRCH) for 58 Anderson-PT-08-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 95 (type FNDP) for Anderson-PT-08-CTLFireability-06
lola: result : true
lola: fired transitions : 179
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 98 (type EQUN) for Anderson-PT-08-CTLFireability-06 (obsolete)
lola: CANCELED task # 101 (type SRCH) for Anderson-PT-08-CTLFireability-06 (obsolete)
lola: LAUNCH task # 96 (type FNDP) for 23 Anderson-PT-08-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 97 (type EQUN) for 23 Anderson-PT-08-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 102 (type SRCH) for 23 Anderson-PT-08-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 96 (type FNDP) for Anderson-PT-08-CTLFireability-05
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 97 (type EQUN) for Anderson-PT-08-CTLFireability-05 (obsolete)
lola: CANCELED task # 102 (type SRCH) for Anderson-PT-08-CTLFireability-05 (obsolete)
lola: FINISHED task # 102 (type SRCH) for Anderson-PT-08-CTLFireability-05
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/373/CTLFireability-98.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/373/CTLFireability-97.sara.
lola: Created skeleton in 1.000000 secs.
lola: FINISHED task # 98 (type EQUN) for Anderson-PT-08-CTLFireability-06
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 105 (type FNDP) for 3 Anderson-PT-08-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 106 (type EQUN) for 3 Anderson-PT-08-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 108 (type SRCH) for 3 Anderson-PT-08-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 105 (type FNDP) for Anderson-PT-08-CTLFireability-01
lola: result : true
lola: fired transitions : 13
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 6 (type EXCL) for Anderson-PT-08-CTLFireability-01 (obsolete)
lola: CANCELED task # 106 (type EQUN) for Anderson-PT-08-CTLFireability-01 (obsolete)
lola: CANCELED task # 108 (type SRCH) for Anderson-PT-08-CTLFireability-01 (obsolete)
lola: LAUNCH task # 92 (type EXCL) for 91 Anderson-PT-08-CTLFireability-15
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: FINISHED task # 108 (type SRCH) for Anderson-PT-08-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 97 (type EQUN) for Anderson-PT-08-CTLFireability-05
lola: result : true
sara: try reading problem file /home/mcc/execution/373/CTLFireability-106.sara.
lola: Created skeleton in 0.000000 secs.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Anderson-PT-08-CTLFireability-01: DISJ true findpath
Anderson-PT-08-CTLFireability-06: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Anderson-PT-08-CTLFireability-00: F 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
Anderson-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-05: DISJ 0 8 0 0 12 0 0 1
Anderson-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-13: F 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
92 CTL EXCL 3/179 7/32 Anderson-PT-08-CTLFireability-15 782747 m, 156549 m/sec, 872958 t fired, .
Time elapsed: 6 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Anderson-PT-08-CTLFireability-01: DISJ true findpath
Anderson-PT-08-CTLFireability-06: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Anderson-PT-08-CTLFireability-00: F 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
Anderson-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-05: DISJ 0 8 0 0 12 0 0 1
Anderson-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-13: F 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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Anderson-PT-08-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
Anderson-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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Anderson-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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Anderson-PT-08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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Anderson-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
Anderson-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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Anderson-PT-08-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
Anderson-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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Anderson-PT-08-CTLFireability-13: F 0 1 0 0 1 0 0 0
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Anderson-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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Anderson-PT-08-CTLFireability-13: F 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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Anderson-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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Anderson-PT-08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
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Anderson-PT-08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Anderson-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-13: F 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 30/864 29/32 Anderson-PT-08-CTLFireability-02 3205234 m, 101643 m/sec, 7525622 t fired, .
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# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 11 (type EXCL) for Anderson-PT-08-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Anderson-PT-08-CTLFireability-01: DISJ true findpath
Anderson-PT-08-CTLFireability-03: DISJ false DISJ
Anderson-PT-08-CTLFireability-04: CTL false CTL model checker
Anderson-PT-08-CTLFireability-06: DISJ true findpath
Anderson-PT-08-CTLFireability-09: CTL false CTL model checker
Anderson-PT-08-CTLFireability-10: CTL false CTL model checker
Anderson-PT-08-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Anderson-PT-08-CTLFireability-00: F 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Anderson-PT-08-CTLFireability-05: DISJ 0 0 0 0 16 0 2 3
Anderson-PT-08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Anderson-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-13: F 0 1 0 0 1 0 0 0
Anderson-PT-08-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 103 (type EXCL) for 88 Anderson-PT-08-CTLFireability-13
lola: time limit : 1141 sec
lola: memory limit: 32 pages
lola: FINISHED task # 103 (type EXCL) for Anderson-PT-08-CTLFireability-13
lola: result : true
lola: markings : 70
lola: fired transitions : 70
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 94 (type EXCL) for 0 Anderson-PT-08-CTLFireability-00
lola: time limit : 1711 sec
lola: memory limit: 32 pages
lola: FINISHED task # 94 (type EXCL) for Anderson-PT-08-CTLFireability-00
lola: result : true
lola: markings : 99
lola: fired transitions : 99
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 77 (type EXCL) for 76 Anderson-PT-08-CTLFireability-08
lola: time limit : 3423 sec
lola: memory limit: 32 pages
lola: FINISHED task # 77 (type EXCL) for Anderson-PT-08-CTLFireability-08
lola: result : true
lola: markings : 75
lola: fired transitions : 150
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Anderson-PT-08-CTLFireability-00: F false state space / EG
Anderson-PT-08-CTLFireability-01: DISJ true findpath
Anderson-PT-08-CTLFireability-02: CTL unknown AGGR
Anderson-PT-08-CTLFireability-03: DISJ false DISJ
Anderson-PT-08-CTLFireability-04: CTL false CTL model checker
Anderson-PT-08-CTLFireability-05: DISJ unknown DISJ
Anderson-PT-08-CTLFireability-06: DISJ true findpath
Anderson-PT-08-CTLFireability-07: CTL unknown AGGR
Anderson-PT-08-CTLFireability-08: CTL true CTL model checker
Anderson-PT-08-CTLFireability-09: CTL false CTL model checker
Anderson-PT-08-CTLFireability-10: CTL false CTL model checker
Anderson-PT-08-CTLFireability-12: CTL false CTL model checker
Anderson-PT-08-CTLFireability-13: F false state space / EG
Anderson-PT-08-CTLFireability-15: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Anderson-PT-08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Anderson-PT-08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r519-tall-167987244700034"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Anderson-PT-08.tgz
mv Anderson-PT-08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;