About the Execution of 2022-gold for UtilityControlRoom-COL-Z4T3N10
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16226.668 | 3593026.00 | 10172854.00 | 4927.10 | ?TF????FFF?FF?FF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r510-tall-167912735100782.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-5348
Executing tool gold2022
Input is UtilityControlRoom-COL-Z4T3N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r510-tall-167912735100782
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 528K
-rw-r--r-- 1 mcc users 8.4K Feb 26 14:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Feb 26 14:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 26 14:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 26 14:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.4K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml
-rw-r--r-- 1 mcc users 18K Feb 26 14:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 166K Feb 26 14:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 14:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 26 14:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:25 UpperBounds.xml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679440037298
gold2022
Got BK_BIN_PATH=/home/mcc/BenchKit/bin/
---> gold2022 --- TAPAAL v5
Setting MODEL_PATH=.
Setting VERIFYPN=/home/mcc/BenchKit/bin/verifypn
Got BK_TIME_CONFINEMENT=3600
Setting TEMPDIR=/home/mcc/BenchKit/bin/tmp
Got BK_MEMORY_CONFINEMENT=16384
Limiting to 16265216 kB
Total timeout: 3590
Time left: 3590
*************************************
* TAPAAL verifying CTLFireability *
*************************************
TEMPDIR=/home/mcc/BenchKit/bin/tmp
QF=/home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE
MF=/home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE
Time left: 3590
---------------------------------------------------
Step -1: Stripping Colors
---------------------------------------------------
Verifying stripped models (16 in total)
/home/mcc/BenchKit/bin/verifypn -n -c -q 718 -l 29 -d 299 -z 4 -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-15
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-14
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-13
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-12
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-11
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-10
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-09
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-08
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-07
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-06
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-05
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-04
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-03
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-02
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-01
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping UtilityControlRoom-COL-Z4T3N10-CTLFireability-00
WARNING: Could not run CPN over-approximation on any queries, terminating.
Time left: 3590
---------------------------------------------------
Step 0: Parallel Simplification
---------------------------------------------------
Doing parallel simplification (16 in total)
Total simplification timout is 718 -- reduction timeout is 299
timeout 3590 /home/mcc/BenchKit/bin/verifypn -n -q 718 -l 29 -d 299 -z 4 -s OverApprox --binary-query-io 2 --write-simplified /home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE --write-reduced /home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
Time left: 2872
---------------------------------------------------
Step 1: Parallel processing
---------------------------------------------------
Doing parallel verification of individual queries (16 in total)
Each query is verified by 4 parallel strategies for 299 seconds
------------------- QUERY 1 ----------------------
No solution found
Command terminated by signal 9
@@@117.26,6162684@@@
Command terminated by signal 9
@@@176.73,9059412@@@
Time left: 2570
------------------- QUERY 2 ----------------------
No solution found
Command terminated by signal 9
@@@97.98,6615012@@@
Command terminated by signal 9
@@@163.87,9271296@@@
Time left: 2268
------------------- QUERY 3 ----------------------
No solution found
Command terminated by signal 9
@@@101.89,5832256@@@
Command terminated by signal 9
@@@177.29,8445772@@@
Time left: 1967
------------------- QUERY 4 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 0.062752 on verification
@@@0.09,60728@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE /home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE --binary-query-io 1 -x 4 -n
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 1966
------------------- QUERY 5 ----------------------
No solution found
Command terminated by signal 9
@@@116.92,7361032@@@
Command terminated by signal 9
@@@244.09,11208512@@@
Time left: 1664
------------------- QUERY 6 ----------------------
No solution found
Time left: 1362
------------------- QUERY 7 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 0.082282 on verification
@@@0.10,60596@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE /home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE --binary-query-io 1 -x 7 -n
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 1362
------------------- QUERY 8 ----------------------
No solution found
Command terminated by signal 9
@@@280.66,11035192@@@
Time left: 1061
------------------- QUERY 9 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 0.054187 on verification
@@@0.09,60640@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE /home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE --binary-query-io 1 -x 9 -n
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 1061
------------------- QUERY 10 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is satisfied.
Spent 0.0517 on verification
@@@0.07,60656@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE /home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE --binary-query-io 1 -x 10 -n
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 1060
------------------- QUERY 11 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 0.049664 on verification
@@@0.07,60724@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE /home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE --binary-query-io 1 -x 11 -n
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 1060
------------------- QUERY 12 ----------------------
No solution found
Time left: 758
------------------- QUERY 13 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 0.066308 on verification
@@@0.10,60848@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE /home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE --binary-query-io 1 -x 13 -n
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 758
------------------- QUERY 14 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 0.056296 on verification
@@@0.08,60884@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE /home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE --binary-query-io 1 -x 14 -n
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 757
------------------- QUERY 15 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 0.066398 on verification
@@@0.09,60852@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE /home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE --binary-query-io 1 -x 15 -n
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 757
------------------- QUERY 16 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 1.65435 on verification
@@@1.67,66324@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.1FeMBRb3LE /home/mcc/BenchKit/bin/tmp/tmp.irlpvRk7QE --binary-query-io 1 -x 16 -n
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 755
---------------------------------------------------
Step 2: Sequential processing
---------------------------------------------------
Remaining 7 queries are verified sequentially.
Each query is verified for a dynamic timeout (at least 598 seconds)
Time left: 755
------------------- QUERY 1 ----------------------
Running query 1 for 598 seconds. Remaining: 7 queries and 755 seconds
No solution found
Command terminated by signal 9
@@@124.65,8894120@@@
Command terminated by signal 9
@@@299.09,16147788@@@
Time left: 456
------------------- QUERY 2 ----------------------
Time left: 456
---------------------------------------------------
Step 4: Random Parallel processing
---------------------------------------------------
Doing random parallel verification of individual queries (7 in total)
Each query is verified by 4 parallel strategies for 65 seconds
------------------- QUERY 1 ----------------------
No solution found
Command terminated by signal 9
@@@59.14,4296620@@@
Time left: 388
------------------- QUERY 2 ----------------------
No solution found
Command terminated by signal 9
@@@60.81,4305444@@@
Time left: 320
------------------- QUERY 3 ----------------------
No solution found
Time left: 252
------------------- QUERY 5 ----------------------
No solution found
Time left: 184
------------------- QUERY 6 ----------------------
No solution found
Time left: 116
------------------- QUERY 8 ----------------------
No solution found
Time left: 49
------------------- QUERY 12 ----------------------
No solution found
Time left: -3
Out of time, terminating!
terminated-with-cleanup
BK_STOP 1679443630324
--------------------
content from stderr:
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z4T3N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="gold2022"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool gold2022"
echo " Input is UtilityControlRoom-COL-Z4T3N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r510-tall-167912735100782"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z4T3N10.tgz
mv UtilityControlRoom-COL-Z4T3N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;