Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r491-tall-167912711501207.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool smartxred
Input is UtilityControlRoom-PT-Z4T4N06, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r491-tall-167912711501207
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.0M
-rw-r--r-- 1 mcc users 21K Feb 26 14:24 CTLCardinality.txt
-rw-r--r-- 1 mcc users 112K Feb 26 14:24 CTLCardinality.xml
-rw-r--r-- 1 mcc users 64K Feb 26 14:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 255K Feb 26 14:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 20K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 34K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 92K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 51K Feb 26 14:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 245K Feb 26 14:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 158K Feb 26 14:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 585K Feb 26 14:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 5.3K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 12K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 191K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-15

=== Now, execution of the tool begins

BK_START 1679317455314

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=smartxred
BK_EXAMINATION=ReachabilityFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z4T4N06
Applying reductions before tool smart
Invoking reducer
Running Version 202303021504
[2023-03-20 13:04:17] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityFireability, -timeout, 360, -rebuildPNML]
[2023-03-20 13:04:17] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-20 13:04:17] [INFO ] Load time of PNML (sax parser for PT used): 69 ms
[2023-03-20 13:04:17] [INFO ] Transformed 228 places.
[2023-03-20 13:04:17] [INFO ] Transformed 450 transitions.
[2023-03-20 13:04:17] [INFO ] Parsed PT model containing 228 places and 450 transitions and 1446 arcs in 144 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityFireability.xml in 30 ms.
Working with output stream class java.io.PrintStream
[2023-03-20 13:04:17] [INFO ] Reduced 18 identical enabling conditions.
[2023-03-20 13:04:17] [INFO ] Reduced 18 identical enabling conditions.
Ensure Unique test removed 96 transitions
Reduce redundant transitions removed 96 transitions.
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 495 ms. (steps per millisecond=20 ) properties (out of 15) seen :10
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-15 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-12 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-07 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-04 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-03 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-01 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 5) seen :1
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-08 TRUE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 4) seen :1
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-09 TRUE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 75 ms. (steps per millisecond=133 ) properties (out of 3) seen :1
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-10 FALSE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
// Phase 1: matrix 354 rows 228 cols
[2023-03-20 13:04:18] [INFO ] Computed 15 place invariants in 26 ms
[2023-03-20 13:04:18] [INFO ] [Real]Absence check using 15 positive place invariants in 9 ms returned sat
[2023-03-20 13:04:18] [INFO ] After 240ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-20 13:04:18] [INFO ] [Nat]Absence check using 15 positive place invariants in 8 ms returned sat
[2023-03-20 13:04:18] [INFO ] After 151ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :1
[2023-03-20 13:04:18] [INFO ] After 241ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :1
Attempting to minimize the solution found.
Minimization took 77 ms.
[2023-03-20 13:04:19] [INFO ] After 398ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :1
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-13 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 2 Parikh solutions to 1 different solutions.
Finished Parikh walk after 22 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=11 )
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-11 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 1 properties in 3 ms.
All properties solved without resorting to model-checking.
Total runtime 1783 ms.
======================================================
========== this is Smart for the MCC'2018 ============
======================================================
Running UtilityControlRoom (PT), instance Z4T4N06
Examination ReachabilityFireability
Parser /home/mcc/BenchKit/bin//../reducer/bin//../../smart/bin//parser/Fireability.jar
Model checker /home/mcc/BenchKit/bin//../reducer/bin//../../smart/bin//rem_exec//smart

GOT IT HERE. BS
Petri model created: 228 places, 450 transitions, 1446 arcs.
Final Score: 5980.761
Took : 21 seconds
Reachability Fireability file is: ReachabilityFireability.xml
READY TO PARSE. BS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-00 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-01 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-02 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-03 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-04 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-05 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-06 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-07 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-08 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-09 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-10 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-11 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-12 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-13 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-14 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA UtilityControlRoom-PT-Z4T4N06-ReachabilityFireability-15 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS

BK_STOP 1679317575128

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityFireability -timeout 360 -rebuildPNML

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N06"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="smartxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool smartxred"
echo " Input is UtilityControlRoom-PT-Z4T4N06, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r491-tall-167912711501207"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N06.tgz
mv UtilityControlRoom-PT-Z4T4N06 execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;