Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r489-tall-167912707300786.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool ltsminxred
Input is TwoPhaseLocking-PT-nC00010vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r489-tall-167912707300786
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 424K
-rw-r--r-- 1 mcc users 7.5K Feb 25 17:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K Feb 25 17:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 17:26 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K Feb 25 17:26 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:22 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 17:22 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:22 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 17:22 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.6K Feb 25 17:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 91K Feb 25 17:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.7K Feb 25 17:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Feb 25 17:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC00010vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679319373978

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC00010vD
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202303021504
[2023-03-20 13:36:15] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-20 13:36:15] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-20 13:36:15] [INFO ] Load time of PNML (sax parser for PT used): 18 ms
[2023-03-20 13:36:15] [INFO ] Transformed 8 places.
[2023-03-20 13:36:15] [INFO ] Transformed 6 transitions.
[2023-03-20 13:36:15] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 77 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
Initial state reduction rules removed 2 formulas.
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 8 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-20 13:36:15] [INFO ] Computed 3 place invariants in 5 ms
[2023-03-20 13:36:15] [INFO ] Implicit Places using invariants in 332 ms returned []
[2023-03-20 13:36:15] [INFO ] Invariant cache hit.
[2023-03-20 13:36:15] [INFO ] Implicit Places using invariants and state equation in 45 ms returned []
Implicit Place search using SMT with State Equation took 403 ms to find 0 implicit places.
[2023-03-20 13:36:16] [INFO ] Invariant cache hit.
[2023-03-20 13:36:16] [INFO ] Dead Transitions using invariants and state equation in 46 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 460 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 14 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 3 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 117 steps, including 1 resets, run visited all 23 properties in 31 ms. (steps per millisecond=3 )
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 2 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 4 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 0 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 3 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 0 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 3 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 0 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 0 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 3 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 0 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 0 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 0 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 2 ms
[2023-03-20 13:36:16] [INFO ] Flatten gal took : 1 ms
[2023-03-20 13:36:16] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-20 13:36:16] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 0 ms.
Total runtime 1019 ms.
There are residual formulas that ITS could not solve within timeout
pnml2lts-sym model.pnml --lace-workers=4 --vset=lddmc --saturation=sat -rbs,w2W,ru,hf --sylvan-sizes=20,28,20,28 --ctl=/tmp/461/ctl_0_ --ctl=/tmp/461/ctl_1_ --ctl=/tmp/461/ctl_2_ --ctl=/tmp/461/ctl_3_ --ctl=/tmp/461/ctl_4_ --ctl=/tmp/461/ctl_5_ --ctl=/tmp/461/ctl_6_ --ctl=/tmp/461/ctl_7_ --ctl=/tmp/461/ctl_8_ --ctl=/tmp/461/ctl_9_ --ctl=/tmp/461/ctl_10_ --ctl=/tmp/461/ctl_11_ --ctl=/tmp/461/ctl_12_ --ctl=/tmp/461/ctl_13_ --mu-par --mu-opt
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-03 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-06 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-07 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-08 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-10 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-12 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-13 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-14 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA TwoPhaseLocking-PT-nC00010vD-CTLFireability-15 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN

BK_STOP 1679319377902

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2023
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-00
ctl formula formula --ctl=/tmp/461/ctl_0_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-01
ctl formula formula --ctl=/tmp/461/ctl_1_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-02
ctl formula formula --ctl=/tmp/461/ctl_2_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-03
ctl formula formula --ctl=/tmp/461/ctl_3_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-05
ctl formula formula --ctl=/tmp/461/ctl_4_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-06
ctl formula formula --ctl=/tmp/461/ctl_5_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-07
ctl formula formula --ctl=/tmp/461/ctl_6_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-08
ctl formula formula --ctl=/tmp/461/ctl_7_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-10
ctl formula formula --ctl=/tmp/461/ctl_8_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-11
ctl formula formula --ctl=/tmp/461/ctl_9_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-12
ctl formula formula --ctl=/tmp/461/ctl_10_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-13
ctl formula formula --ctl=/tmp/461/ctl_11_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-14
ctl formula formula --ctl=/tmp/461/ctl_12_
ctl formula name TwoPhaseLocking-PT-nC00010vD-CTLFireability-15
ctl formula formula --ctl=/tmp/461/ctl_13_
pnml2lts-sym: Exploration order is bfs-prev
pnml2lts-sym: Saturation strategy is sat
pnml2lts-sym: Guided search strategy is unguided
pnml2lts-sym: Attractor strategy is default
pnml2lts-sym: opening model.pnml
pnml2lts-sym: Edge label is id
Warning: program compiled against libxml 210 using older 209
pnml2lts-sym: Petri net has 8 places, 6 transitions and 18 arcs
pnml2lts-sym: Petri net Petri analyzed
pnml2lts-sym: There are no safe places
pnml2lts-sym: Loading Petri net took 0.000 real 0.000 user 0.000 sys
pnml2lts-sym: Initializing regrouping layer
pnml2lts-sym: Regroup specification: bs,w2W,ru,hf
pnml2lts-sym: Regroup Boost's Sloan
pnml2lts-sym: Regroup over-approximate must-write to may-write
pnml2lts-sym: Regroup Row sUbsume
pnml2lts-sym: Reqroup Horizontal Flip
pnml2lts-sym: Regrouping: 6->6 groups
pnml2lts-sym: Regrouping took 0.000 real 0.000 user 0.000 sys
pnml2lts-sym: state vector length is 8; there are 6 groups
pnml2lts-sym: Creating a multi-core ListDD domain.
pnml2lts-sym: Sylvan allocates 15.000 GB virtual memory for nodes table and operation cache.
pnml2lts-sym: Initial nodes table and operation cache requires 60.00 MB.
pnml2lts-sym: Using GBgetTransitionsShortR2W as next-state function
pnml2lts-sym: got initial state
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: Exploration took 806 group checks and 0 next state calls
pnml2lts-sym: reachability took 0.050 real 0.140 user 0.050 sys
pnml2lts-sym: counting visited states...
pnml2lts-sym: counting took 0.000 real 0.010 user 0.000 sys
pnml2lts-sym: state space has 503 states, 501 nodes
pnml2lts-sym: Formula /tmp/461/ctl_2_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_3_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_0_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_13_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_5_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_4_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_12_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_11_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_7_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_6_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_8_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_1_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_9_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_10_ does not hold for the initial state
pnml2lts-sym: group_next: 426 nodes total
pnml2lts-sym: group_explored: 341 nodes, 613 short vectors total
pnml2lts-sym: max token count: 10

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00010vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool ltsminxred"
echo " Input is TwoPhaseLocking-PT-nC00010vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r489-tall-167912707300786"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00010vD.tgz
mv TwoPhaseLocking-PT-nC00010vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;