Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912704101218.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-PT-Z4T4N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912704101218
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.6M
-rw-r--r-- 1 mcc users 55K Feb 26 14:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 271K Feb 26 14:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 139K Feb 26 14:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 525K Feb 26 14:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 25 17:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 54K Feb 25 17:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 48K Feb 25 17:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 132K Feb 25 17:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 71K Feb 26 15:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 329K Feb 26 15:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 141K Feb 26 15:06 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 477K Feb 26 15:06 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 6.1K Feb 25 17:26 UpperBounds.txt
-rw-r--r-- 1 mcc users 13K Feb 25 17:26 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 319K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679241427002

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z4T4N10
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 15:57:08] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 15:57:08] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 15:57:08] [INFO ] Load time of PNML (sax parser for PT used): 64 ms
[2023-03-19 15:57:08] [INFO ] Transformed 376 places.
[2023-03-19 15:57:08] [INFO ] Transformed 750 transitions.
[2023-03-19 15:57:08] [INFO ] Parsed PT model containing 376 places and 750 transitions and 2410 arcs in 131 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 26 ms.
[2023-03-19 15:57:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 15:57:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 15:57:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 15:57:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 15:57:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 15:57:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 15:57:08] [INFO ] Reduced 30 identical enabling conditions.
Ensure Unique test removed 160 transitions
Reduce redundant transitions removed 160 transitions.
Support contains 376 out of 376 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 14 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
// Phase 1: matrix 590 rows 376 cols
[2023-03-19 15:57:08] [INFO ] Computed 23 place invariants in 34 ms
[2023-03-19 15:57:09] [INFO ] Implicit Places using invariants in 451 ms returned []
[2023-03-19 15:57:09] [INFO ] Invariant cache hit.
[2023-03-19 15:57:09] [INFO ] Implicit Places using invariants and state equation in 189 ms returned []
Implicit Place search using SMT with State Equation took 662 ms to find 0 implicit places.
[2023-03-19 15:57:09] [INFO ] Invariant cache hit.
[2023-03-19 15:57:09] [INFO ] Dead Transitions using invariants and state equation in 229 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 908 ms. Remains : 376/376 places, 590/590 transitions.
Support contains 376 out of 376 places after structural reductions.
[2023-03-19 15:57:09] [INFO ] Flatten gal took : 105 ms
[2023-03-19 15:57:10] [INFO ] Flatten gal took : 70 ms
[2023-03-19 15:57:10] [INFO ] Input system was already deterministic with 590 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 427 ms. (steps per millisecond=23 ) properties (out of 77) seen :70
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=666 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
[2023-03-19 15:57:11] [INFO ] Invariant cache hit.
[2023-03-19 15:57:11] [INFO ] [Real]Absence check using 23 positive place invariants in 10 ms returned sat
[2023-03-19 15:57:11] [INFO ] After 146ms SMT Verify possible using state equation in real domain returned unsat :2 sat :1
[2023-03-19 15:57:11] [INFO ] After 199ms SMT Verify possible using trap constraints in real domain returned unsat :2 sat :1
Attempting to minimize the solution found.
Minimization took 25 ms.
[2023-03-19 15:57:11] [INFO ] After 326ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :1
Fused 3 Parikh solutions to 1 different solutions.
Finished Parikh walk after 27 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=13 )
Parikh walk visited 1 properties in 2 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-19 15:57:11] [INFO ] Flatten gal took : 47 ms
[2023-03-19 15:57:12] [INFO ] Flatten gal took : 63 ms
[2023-03-19 15:57:12] [INFO ] Input system was already deterministic with 590 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 16 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 15:57:12] [INFO ] Flatten gal took : 23 ms
[2023-03-19 15:57:12] [INFO ] Flatten gal took : 24 ms
[2023-03-19 15:57:12] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Drop transitions removed 160 transitions
Trivial Post-agglo rules discarded 160 transitions
Performed 160 trivial Post agglomeration. Transition count delta: 160
Iterating post reduction 0 with 160 rules applied. Total rules applied 160 place count 376 transition count 430
Reduce places removed 160 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 200 rules applied. Total rules applied 360 place count 216 transition count 390
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 363 place count 213 transition count 270
Iterating global reduction 2 with 3 rules applied. Total rules applied 366 place count 213 transition count 270
Discarding 30 places :
Symmetric choice reduction at 2 with 30 rule applications. Total rules 396 place count 183 transition count 240
Iterating global reduction 2 with 30 rules applied. Total rules applied 426 place count 183 transition count 240
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 1 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 446 place count 173 transition count 230
Applied a total of 446 rules in 45 ms. Remains 173 /376 variables (removed 203) and now considering 230/590 (removed 360) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 45 ms. Remains : 173/376 places, 230/590 transitions.
[2023-03-19 15:57:12] [INFO ] Flatten gal took : 7 ms
[2023-03-19 15:57:12] [INFO ] Flatten gal took : 7 ms
[2023-03-19 15:57:12] [INFO ] Input system was already deterministic with 230 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 3 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 15:57:12] [INFO ] Flatten gal took : 20 ms
[2023-03-19 15:57:12] [INFO ] Flatten gal took : 22 ms
[2023-03-19 15:57:12] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 12 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 19 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 21 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 6 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 16 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 19 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 9 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 14 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 2 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 19 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 29 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Performed 160 Post agglomeration using F-continuation condition.Transition count delta: 160
Iterating post reduction 0 with 160 rules applied. Total rules applied 160 place count 376 transition count 430
Reduce places removed 160 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 200 rules applied. Total rules applied 360 place count 216 transition count 390
Applied a total of 360 rules in 26 ms. Remains 216 /376 variables (removed 160) and now considering 390/590 (removed 200) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 216/376 places, 390/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 13 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 17 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 390 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 118 places :
Symmetric choice reduction at 0 with 118 rule applications. Total rules 118 place count 258 transition count 472
Iterating global reduction 0 with 118 rules applied. Total rules applied 236 place count 258 transition count 472
Applied a total of 236 rules in 9 ms. Remains 258 /376 variables (removed 118) and now considering 472/590 (removed 118) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 258/376 places, 472/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 13 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 14 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 472 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 119 places :
Symmetric choice reduction at 0 with 119 rule applications. Total rules 119 place count 257 transition count 471
Iterating global reduction 0 with 119 rules applied. Total rules applied 238 place count 257 transition count 471
Applied a total of 238 rules in 8 ms. Remains 257 /376 variables (removed 119) and now considering 471/590 (removed 119) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 257/376 places, 471/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 13 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 13 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 471 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 8 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 118 places :
Symmetric choice reduction at 0 with 118 rule applications. Total rules 118 place count 258 transition count 472
Iterating global reduction 0 with 118 rules applied. Total rules applied 236 place count 258 transition count 472
Applied a total of 236 rules in 8 ms. Remains 258 /376 variables (removed 118) and now considering 472/590 (removed 118) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 258/376 places, 472/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 472 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 117 places :
Symmetric choice reduction at 0 with 117 rule applications. Total rules 117 place count 259 transition count 473
Iterating global reduction 0 with 117 rules applied. Total rules applied 234 place count 259 transition count 473
Applied a total of 234 rules in 8 ms. Remains 259 /376 variables (removed 117) and now considering 473/590 (removed 117) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 259/376 places, 473/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 473 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 119 places :
Symmetric choice reduction at 0 with 119 rule applications. Total rules 119 place count 257 transition count 471
Iterating global reduction 0 with 119 rules applied. Total rules applied 238 place count 257 transition count 471
Applied a total of 238 rules in 8 ms. Remains 257 /376 variables (removed 119) and now considering 471/590 (removed 119) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 257/376 places, 471/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 471 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 117 places :
Symmetric choice reduction at 0 with 117 rule applications. Total rules 117 place count 259 transition count 473
Iterating global reduction 0 with 117 rules applied. Total rules applied 234 place count 259 transition count 473
Applied a total of 234 rules in 8 ms. Remains 259 /376 variables (removed 117) and now considering 473/590 (removed 117) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 259/376 places, 473/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 473 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 115 places :
Symmetric choice reduction at 0 with 115 rule applications. Total rules 115 place count 261 transition count 475
Iterating global reduction 0 with 115 rules applied. Total rules applied 230 place count 261 transition count 475
Applied a total of 230 rules in 8 ms. Remains 261 /376 variables (removed 115) and now considering 475/590 (removed 115) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 261/376 places, 475/590 transitions.
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:57:13] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:57:13] [INFO ] Input system was already deterministic with 475 transitions.
[2023-03-19 15:57:14] [INFO ] Flatten gal took : 53 ms
[2023-03-19 15:57:14] [INFO ] Flatten gal took : 48 ms
[2023-03-19 15:57:14] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 25 ms.
[2023-03-19 15:57:14] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 376 places, 590 transitions and 1770 arcs took 2 ms.
Total runtime 6352 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-PT-Z4T4N10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679241916238

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 81 (type SKEL/FNDP) for 24 UtilityControlRoom-PT-Z4T4N10-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type SKEL/EQUN) for 24 UtilityControlRoom-PT-Z4T4N10-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 83 (type SKEL/SRCH) for 24 UtilityControlRoom-PT-Z4T4N10-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SKEL/SRCH) for 24 UtilityControlRoom-PT-Z4T4N10-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 83 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T4N10-CTLFireability-08
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 81 (type FNDP) for UtilityControlRoom-PT-Z4T4N10-CTLFireability-08 (obsolete)
lola: CANCELED task # 82 (type EQUN) for UtilityControlRoom-PT-Z4T4N10-CTLFireability-08 (obsolete)
lola: CANCELED task # 84 (type SRCH) for UtilityControlRoom-PT-Z4T4N10-CTLFireability-08 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 81 (type SKEL/FNDP) for UtilityControlRoom-PT-Z4T4N10-CTLFireability-08
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-PT-Z4T4N10-CTLFireability-01
lola: time limit : 105 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: try reading problem file /home/mcc/execution/374/CTLFireability-82.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 82 (type SKEL/EQUN) for UtilityControlRoom-PT-Z4T4N10-CTLFireability-08
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:754
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
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sara: try reading problem file /home/mcc/execution/374/CTLFireability-88.sara.
sara: place or transition ordering is non-deterministic

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 4 0 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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4 EG EXCL 5/162 2/32 UtilityControlRoom-PT-Z4T4N10-CTLFireability-01 372493 m, 74498 m/sec, 1367070 t fired, .

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 4 0 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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4 EG EXCL 10/162 4/32 UtilityControlRoom-PT-Z4T4N10-CTLFireability-01 746775 m, 74856 m/sec, 2814446 t fired, .

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 4 0 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 4 0 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 4 0 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 4 0 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 4 0 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 4 0 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 4 0 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 4 0 0 4 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 1 0 0 7 0 0 4
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ 0 1 0 0 5 0 0 2
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ 0 1 0 0 3 0 0 0

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UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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UtilityControlRoom-PT-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09: CONJ false CTL model checker
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10: CONJ false state space /EXEG
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ false CTL model checker
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ false state space / EG
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ 0 0 0 0 7 0 1 4
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01: EG unknown AGGR
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02: CTL unknown AGGR
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04: CTL unknown AGGR
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06: CTL unknown AGGR
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07: CTL unknown AGGR
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08: CONJ unknown CONJ
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09: CONJ false CTL model checker
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10: CONJ false state space /EXEG
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11: CTL unknown AGGR
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12: CONJ false CTL model checker
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13: CTL unknown AGGR
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14: CONJ false state space / EG
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-PT-Z4T4N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912704101218"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N10.tgz
mv UtilityControlRoom-PT-Z4T4N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;