About the Execution of LoLa+red for UtilityControlRoom-PT-Z4T4N06
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4866.279 | 291020.00 | 288183.00 | 1051.00 | ?T?TTTFTFFF??TT? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r487-tall-167912704101202.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-PT-Z4T4N06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912704101202
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.0M
-rw-r--r-- 1 mcc users 21K Feb 26 14:24 CTLCardinality.txt
-rw-r--r-- 1 mcc users 112K Feb 26 14:24 CTLCardinality.xml
-rw-r--r-- 1 mcc users 64K Feb 26 14:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 255K Feb 26 14:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 20K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 34K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 92K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 51K Feb 26 14:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 245K Feb 26 14:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 158K Feb 26 14:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 585K Feb 26 14:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 5.3K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 12K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 191K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679240340117
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z4T4N06
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 15:39:01] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 15:39:01] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 15:39:01] [INFO ] Load time of PNML (sax parser for PT used): 61 ms
[2023-03-19 15:39:01] [INFO ] Transformed 228 places.
[2023-03-19 15:39:01] [INFO ] Transformed 450 transitions.
[2023-03-19 15:39:01] [INFO ] Parsed PT model containing 228 places and 450 transitions and 1446 arcs in 123 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 21 ms.
[2023-03-19 15:39:01] [INFO ] Reduced 18 identical enabling conditions.
[2023-03-19 15:39:01] [INFO ] Reduced 18 identical enabling conditions.
[2023-03-19 15:39:01] [INFO ] Reduced 18 identical enabling conditions.
[2023-03-19 15:39:01] [INFO ] Reduced 18 identical enabling conditions.
[2023-03-19 15:39:01] [INFO ] Reduced 18 identical enabling conditions.
[2023-03-19 15:39:01] [INFO ] Reduced 18 identical enabling conditions.
Ensure Unique test removed 96 transitions
Reduce redundant transitions removed 96 transitions.
Support contains 228 out of 228 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Applied a total of 0 rules in 98 ms. Remains 228 /228 variables (removed 0) and now considering 354/354 (removed 0) transitions.
// Phase 1: matrix 354 rows 228 cols
[2023-03-19 15:39:02] [INFO ] Computed 15 place invariants in 18 ms
[2023-03-19 15:39:02] [INFO ] Implicit Places using invariants in 215 ms returned []
[2023-03-19 15:39:02] [INFO ] Invariant cache hit.
[2023-03-19 15:39:02] [INFO ] Implicit Places using invariants and state equation in 129 ms returned []
Implicit Place search using SMT with State Equation took 464 ms to find 0 implicit places.
[2023-03-19 15:39:02] [INFO ] Invariant cache hit.
[2023-03-19 15:39:02] [INFO ] Dead Transitions using invariants and state equation in 191 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 757 ms. Remains : 228/228 places, 354/354 transitions.
Support contains 228 out of 228 places after structural reductions.
[2023-03-19 15:39:02] [INFO ] Flatten gal took : 63 ms
[2023-03-19 15:39:03] [INFO ] Flatten gal took : 49 ms
[2023-03-19 15:39:03] [INFO ] Input system was already deterministic with 354 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 340 ms. (steps per millisecond=29 ) properties (out of 59) seen :56
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 3) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-19 15:39:03] [INFO ] Invariant cache hit.
[2023-03-19 15:39:03] [INFO ] [Real]Absence check using 15 positive place invariants in 11 ms returned sat
[2023-03-19 15:39:03] [INFO ] After 114ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 15:39:03] [INFO ] Flatten gal took : 26 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 35 ms
[2023-03-19 15:39:04] [INFO ] Input system was already deterministic with 354 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Performed 24 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 24 Pre rules applied. Total rules applied 0 place count 228 transition count 330
Deduced a syphon composed of 24 places in 0 ms
Reduce places removed 24 places and 0 transitions.
Iterating global reduction 0 with 48 rules applied. Total rules applied 48 place count 204 transition count 330
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 0 with 12 rules applied. Total rules applied 60 place count 198 transition count 324
Applied a total of 60 rules in 43 ms. Remains 198 /228 variables (removed 30) and now considering 324/354 (removed 30) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 43 ms. Remains : 198/228 places, 324/354 transitions.
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 16 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 16 ms
[2023-03-19 15:39:04] [INFO ] Input system was already deterministic with 324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Applied a total of 0 rules in 2 ms. Remains 228 /228 variables (removed 0) and now considering 354/354 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 228/228 places, 354/354 transitions.
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 21 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 17 ms
[2023-03-19 15:39:04] [INFO ] Input system was already deterministic with 354 transitions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Discarding 72 places :
Symmetric choice reduction at 0 with 72 rule applications. Total rules 72 place count 156 transition count 282
Iterating global reduction 0 with 72 rules applied. Total rules applied 144 place count 156 transition count 282
Applied a total of 144 rules in 13 ms. Remains 156 /228 variables (removed 72) and now considering 282/354 (removed 72) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 156/228 places, 282/354 transitions.
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:39:04] [INFO ] Input system was already deterministic with 282 transitions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Applied a total of 0 rules in 2 ms. Remains 228 /228 variables (removed 0) and now considering 354/354 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 228/228 places, 354/354 transitions.
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 14 ms
[2023-03-19 15:39:04] [INFO ] Input system was already deterministic with 354 transitions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Discarding 72 places :
Symmetric choice reduction at 0 with 72 rule applications. Total rules 72 place count 156 transition count 282
Iterating global reduction 0 with 72 rules applied. Total rules applied 144 place count 156 transition count 282
Applied a total of 144 rules in 8 ms. Remains 156 /228 variables (removed 72) and now considering 282/354 (removed 72) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 156/228 places, 282/354 transitions.
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 9 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:39:04] [INFO ] Input system was already deterministic with 282 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Drop transitions removed 96 transitions
Trivial Post-agglo rules discarded 96 transitions
Performed 96 trivial Post agglomeration. Transition count delta: 96
Iterating post reduction 0 with 96 rules applied. Total rules applied 96 place count 228 transition count 258
Reduce places removed 96 places and 0 transitions.
Ensure Unique test removed 24 transitions
Reduce isomorphic transitions removed 24 transitions.
Iterating post reduction 1 with 120 rules applied. Total rules applied 216 place count 132 transition count 234
Performed 24 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 24 Pre rules applied. Total rules applied 216 place count 132 transition count 210
Deduced a syphon composed of 24 places in 0 ms
Reduce places removed 24 places and 0 transitions.
Iterating global reduction 2 with 48 rules applied. Total rules applied 264 place count 108 transition count 210
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 267 place count 105 transition count 138
Iterating global reduction 2 with 3 rules applied. Total rules applied 270 place count 105 transition count 138
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 288 place count 87 transition count 120
Iterating global reduction 2 with 18 rules applied. Total rules applied 306 place count 87 transition count 120
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 324 place count 69 transition count 84
Iterating global reduction 2 with 18 rules applied. Total rules applied 342 place count 69 transition count 84
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 360 place count 51 transition count 66
Iterating global reduction 2 with 18 rules applied. Total rules applied 378 place count 51 transition count 66
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 2 with 18 rules applied. Total rules applied 396 place count 51 transition count 48
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 6 Pre rules applied. Total rules applied 396 place count 51 transition count 42
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 3 with 12 rules applied. Total rules applied 408 place count 45 transition count 42
Applied a total of 408 rules in 17 ms. Remains 45 /228 variables (removed 183) and now considering 42/354 (removed 312) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 45/228 places, 42/354 transitions.
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 2 ms
[2023-03-19 15:39:04] [INFO ] Input system was already deterministic with 42 transitions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Discarding 72 places :
Symmetric choice reduction at 0 with 72 rule applications. Total rules 72 place count 156 transition count 282
Iterating global reduction 0 with 72 rules applied. Total rules applied 144 place count 156 transition count 282
Applied a total of 144 rules in 3 ms. Remains 156 /228 variables (removed 72) and now considering 282/354 (removed 72) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 156/228 places, 282/354 transitions.
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 10 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:39:04] [INFO ] Input system was already deterministic with 282 transitions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Discarding 72 places :
Symmetric choice reduction at 0 with 72 rule applications. Total rules 72 place count 156 transition count 282
Iterating global reduction 0 with 72 rules applied. Total rules applied 144 place count 156 transition count 282
Applied a total of 144 rules in 5 ms. Remains 156 /228 variables (removed 72) and now considering 282/354 (removed 72) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 156/228 places, 282/354 transitions.
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 15 ms
[2023-03-19 15:39:04] [INFO ] Input system was already deterministic with 282 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Drop transitions removed 95 transitions
Trivial Post-agglo rules discarded 95 transitions
Performed 95 trivial Post agglomeration. Transition count delta: 95
Iterating post reduction 0 with 95 rules applied. Total rules applied 95 place count 228 transition count 259
Reduce places removed 95 places and 0 transitions.
Ensure Unique test removed 24 transitions
Reduce isomorphic transitions removed 24 transitions.
Iterating post reduction 1 with 119 rules applied. Total rules applied 214 place count 133 transition count 235
Performed 24 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 24 Pre rules applied. Total rules applied 214 place count 133 transition count 211
Deduced a syphon composed of 24 places in 0 ms
Reduce places removed 24 places and 0 transitions.
Iterating global reduction 2 with 48 rules applied. Total rules applied 262 place count 109 transition count 211
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 264 place count 107 transition count 163
Iterating global reduction 2 with 2 rules applied. Total rules applied 266 place count 107 transition count 163
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 278 place count 95 transition count 151
Iterating global reduction 2 with 12 rules applied. Total rules applied 290 place count 95 transition count 151
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 302 place count 83 transition count 127
Iterating global reduction 2 with 12 rules applied. Total rules applied 314 place count 83 transition count 127
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 325 place count 72 transition count 105
Iterating global reduction 2 with 11 rules applied. Total rules applied 336 place count 72 transition count 105
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 2 with 11 rules applied. Total rules applied 347 place count 72 transition count 94
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 3 with 12 rules applied. Total rules applied 359 place count 66 transition count 88
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 3 with 13 rules applied. Total rules applied 372 place count 59 transition count 82
Performed 12 Post agglomeration using F-continuation condition.Transition count delta: 12
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 3 with 24 rules applied. Total rules applied 396 place count 47 transition count 70
Applied a total of 396 rules in 21 ms. Remains 47 /228 variables (removed 181) and now considering 70/354 (removed 284) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 21 ms. Remains : 47/228 places, 70/354 transitions.
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 3 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 3 ms
[2023-03-19 15:39:04] [INFO ] Input system was already deterministic with 70 transitions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Discarding 72 places :
Symmetric choice reduction at 0 with 72 rule applications. Total rules 72 place count 156 transition count 282
Iterating global reduction 0 with 72 rules applied. Total rules applied 144 place count 156 transition count 282
Applied a total of 144 rules in 4 ms. Remains 156 /228 variables (removed 72) and now considering 282/354 (removed 72) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 156/228 places, 282/354 transitions.
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:39:04] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:39:05] [INFO ] Input system was already deterministic with 282 transitions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Discarding 70 places :
Symmetric choice reduction at 0 with 70 rule applications. Total rules 70 place count 158 transition count 284
Iterating global reduction 0 with 70 rules applied. Total rules applied 140 place count 158 transition count 284
Applied a total of 140 rules in 5 ms. Remains 158 /228 variables (removed 70) and now considering 284/354 (removed 70) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 158/228 places, 284/354 transitions.
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:39:05] [INFO ] Input system was already deterministic with 284 transitions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Discarding 68 places :
Symmetric choice reduction at 0 with 68 rule applications. Total rules 68 place count 160 transition count 286
Iterating global reduction 0 with 68 rules applied. Total rules applied 136 place count 160 transition count 286
Applied a total of 136 rules in 4 ms. Remains 160 /228 variables (removed 68) and now considering 286/354 (removed 68) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 160/228 places, 286/354 transitions.
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 9 ms
[2023-03-19 15:39:05] [INFO ] Input system was already deterministic with 286 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Drop transitions removed 96 transitions
Trivial Post-agglo rules discarded 96 transitions
Performed 96 trivial Post agglomeration. Transition count delta: 96
Iterating post reduction 0 with 96 rules applied. Total rules applied 96 place count 228 transition count 258
Reduce places removed 96 places and 0 transitions.
Ensure Unique test removed 24 transitions
Reduce isomorphic transitions removed 24 transitions.
Iterating post reduction 1 with 120 rules applied. Total rules applied 216 place count 132 transition count 234
Performed 24 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 24 Pre rules applied. Total rules applied 216 place count 132 transition count 210
Deduced a syphon composed of 24 places in 0 ms
Reduce places removed 24 places and 0 transitions.
Iterating global reduction 2 with 48 rules applied. Total rules applied 264 place count 108 transition count 210
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 267 place count 105 transition count 138
Iterating global reduction 2 with 3 rules applied. Total rules applied 270 place count 105 transition count 138
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 288 place count 87 transition count 120
Iterating global reduction 2 with 18 rules applied. Total rules applied 306 place count 87 transition count 120
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 324 place count 69 transition count 84
Iterating global reduction 2 with 18 rules applied. Total rules applied 342 place count 69 transition count 84
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 360 place count 51 transition count 66
Iterating global reduction 2 with 18 rules applied. Total rules applied 378 place count 51 transition count 66
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 2 with 18 rules applied. Total rules applied 396 place count 51 transition count 48
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 5 Pre rules applied. Total rules applied 396 place count 51 transition count 43
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 10 rules applied. Total rules applied 406 place count 46 transition count 43
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Ensure Unique test removed 1 places
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 3 with 13 rules applied. Total rules applied 419 place count 39 transition count 37
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 10 rules applied. Total rules applied 429 place count 34 transition count 32
Applied a total of 429 rules in 14 ms. Remains 34 /228 variables (removed 194) and now considering 32/354 (removed 322) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 34/228 places, 32/354 transitions.
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 1 ms
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 1 ms
[2023-03-19 15:39:05] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Drop transitions removed 96 transitions
Trivial Post-agglo rules discarded 96 transitions
Performed 96 trivial Post agglomeration. Transition count delta: 96
Iterating post reduction 0 with 96 rules applied. Total rules applied 96 place count 228 transition count 258
Reduce places removed 96 places and 0 transitions.
Ensure Unique test removed 24 transitions
Reduce isomorphic transitions removed 24 transitions.
Iterating post reduction 1 with 120 rules applied. Total rules applied 216 place count 132 transition count 234
Performed 24 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 24 Pre rules applied. Total rules applied 216 place count 132 transition count 210
Deduced a syphon composed of 24 places in 0 ms
Reduce places removed 24 places and 0 transitions.
Iterating global reduction 2 with 48 rules applied. Total rules applied 264 place count 108 transition count 210
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 267 place count 105 transition count 138
Iterating global reduction 2 with 3 rules applied. Total rules applied 270 place count 105 transition count 138
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 288 place count 87 transition count 120
Iterating global reduction 2 with 18 rules applied. Total rules applied 306 place count 87 transition count 120
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 324 place count 69 transition count 84
Iterating global reduction 2 with 18 rules applied. Total rules applied 342 place count 69 transition count 84
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 360 place count 51 transition count 66
Iterating global reduction 2 with 18 rules applied. Total rules applied 378 place count 51 transition count 66
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 2 with 18 rules applied. Total rules applied 396 place count 51 transition count 48
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 5 Pre rules applied. Total rules applied 396 place count 51 transition count 43
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 10 rules applied. Total rules applied 406 place count 46 transition count 43
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 10 rules applied. Total rules applied 416 place count 41 transition count 38
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 10 rules applied. Total rules applied 426 place count 36 transition count 33
Applied a total of 426 rules in 18 ms. Remains 36 /228 variables (removed 192) and now considering 33/354 (removed 321) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 36/228 places, 33/354 transitions.
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 1 ms
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 1 ms
[2023-03-19 15:39:05] [INFO ] Input system was already deterministic with 33 transitions.
Starting structural reductions in LTL mode, iteration 0 : 228/228 places, 354/354 transitions.
Discarding 72 places :
Symmetric choice reduction at 0 with 72 rule applications. Total rules 72 place count 156 transition count 282
Iterating global reduction 0 with 72 rules applied. Total rules applied 144 place count 156 transition count 282
Applied a total of 144 rules in 3 ms. Remains 156 /228 variables (removed 72) and now considering 282/354 (removed 72) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 156/228 places, 282/354 transitions.
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 7 ms
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 7 ms
[2023-03-19 15:39:05] [INFO ] Input system was already deterministic with 282 transitions.
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 27 ms
[2023-03-19 15:39:05] [INFO ] Flatten gal took : 27 ms
[2023-03-19 15:39:05] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 26 ms.
[2023-03-19 15:39:05] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 228 places, 354 transitions and 1062 arcs took 1 ms.
Total runtime 4007 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-PT-Z4T4N06
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/364
CTLFireability
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679240631137
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/364/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/364/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/364/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 20 (type EXCL) for 19 UtilityControlRoom-PT-Z4T4N06-CTLFireability-05
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 20 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-CTLFireability-05
lola: result : true
lola: markings : 43
lola: fired transitions : 43
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 UtilityControlRoom-PT-Z4T4N06-CTLFireability-07
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-CTLFireability-07
lola: result : true
lola: markings : 49
lola: fired transitions : 55
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 44 (type EXCL) for 43 UtilityControlRoom-PT-Z4T4N06-CTLFireability-14
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-CTLFireability-14
lola: result : true
lola: markings : 34
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 3 (type EXCL) for 0 UtilityControlRoom-PT-Z4T4N06-CTLFireability-00
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N06-CTLFireability-05: EG true state space / EG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N06-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-08: AGAF 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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UtilityControlRoom-PT-Z4T4N06-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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47 CTL EXCL 35/3376 21/32 UtilityControlRoom-PT-Z4T4N06-CTLFireability-15 4749144 m, 120337 m/sec, 22620554 t fired, .
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UtilityControlRoom-PT-Z4T4N06-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-05: EG true state space / EG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-08: AGAF false state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-09: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-13: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-14: CTL true CTL model checker
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UtilityControlRoom-PT-Z4T4N06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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UtilityControlRoom-PT-Z4T4N06-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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47 CTL EXCL 40/3376 24/32 UtilityControlRoom-PT-Z4T4N06-CTLFireability-15 5337697 m, 117710 m/sec, 25621643 t fired, .
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UtilityControlRoom-PT-Z4T4N06-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-05: EG true state space / EG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-08: AGAF false state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-09: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-13: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-14: CTL true CTL model checker
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UtilityControlRoom-PT-Z4T4N06-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-05: EG true state space / EG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-08: AGAF false state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-09: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-13: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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UtilityControlRoom-PT-Z4T4N06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N06-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-05: EG true state space / EG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-08: AGAF false state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-09: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-13: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N06-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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47 CTL EXCL 55/3376 31/32 UtilityControlRoom-PT-Z4T4N06-CTLFireability-15 7050745 m, 112620 m/sec, 34482349 t fired, .
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lola: CANCELED task # 47 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N06-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-05: EG true state space / EG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-08: AGAF false state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-09: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-13: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N06-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N06-CTLFireability-00: DISJ unknown DISJ
UtilityControlRoom-PT-Z4T4N06-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-02: CTL unknown AGGR
UtilityControlRoom-PT-Z4T4N06-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-05: EG true state space / EG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-08: AGAF false state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-09: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-11: CTL unknown AGGR
UtilityControlRoom-PT-Z4T4N06-CTLFireability-12: CTL unknown AGGR
UtilityControlRoom-PT-Z4T4N06-CTLFireability-13: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T4N06-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N06-CTLFireability-15: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-PT-Z4T4N06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912704101202"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N06.tgz
mv UtilityControlRoom-PT-Z4T4N06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;