About the Execution of LoLa+red for UtilityControlRoom-PT-Z4T4N04
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2571.636 | 126545.00 | 128535.00 | 544.50 | FT?TFFFFFFF?FFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r487-tall-167912704101194.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-PT-Z4T4N04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912704101194
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 20K Feb 26 14:33 CTLCardinality.txt
-rw-r--r-- 1 mcc users 111K Feb 26 14:33 CTLCardinality.xml
-rw-r--r-- 1 mcc users 51K Feb 26 14:32 CTLFireability.txt
-rw-r--r-- 1 mcc users 184K Feb 26 14:32 CTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 53K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 14:37 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 26 14:37 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 94K Feb 26 14:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 357K Feb 26 14:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.4K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 128K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679238936881
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z4T4N04
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 15:15:38] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 15:15:38] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 15:15:38] [INFO ] Load time of PNML (sax parser for PT used): 50 ms
[2023-03-19 15:15:38] [INFO ] Transformed 154 places.
[2023-03-19 15:15:38] [INFO ] Transformed 300 transitions.
[2023-03-19 15:15:38] [INFO ] Parsed PT model containing 154 places and 300 transitions and 964 arcs in 111 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 17 ms.
[2023-03-19 15:15:38] [INFO ] Reduced 12 identical enabling conditions.
[2023-03-19 15:15:38] [INFO ] Reduced 12 identical enabling conditions.
[2023-03-19 15:15:38] [INFO ] Reduced 12 identical enabling conditions.
[2023-03-19 15:15:38] [INFO ] Reduced 12 identical enabling conditions.
Ensure Unique test removed 64 transitions
Reduce redundant transitions removed 64 transitions.
Support contains 154 out of 154 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Applied a total of 0 rules in 36 ms. Remains 154 /154 variables (removed 0) and now considering 236/236 (removed 0) transitions.
// Phase 1: matrix 236 rows 154 cols
[2023-03-19 15:15:38] [INFO ] Computed 11 place invariants in 19 ms
[2023-03-19 15:15:38] [INFO ] Implicit Places using invariants in 189 ms returned []
[2023-03-19 15:15:38] [INFO ] Invariant cache hit.
[2023-03-19 15:15:38] [INFO ] Implicit Places using invariants and state equation in 104 ms returned []
Implicit Place search using SMT with State Equation took 318 ms to find 0 implicit places.
[2023-03-19 15:15:38] [INFO ] Invariant cache hit.
[2023-03-19 15:15:39] [INFO ] Dead Transitions using invariants and state equation in 132 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 487 ms. Remains : 154/154 places, 236/236 transitions.
Support contains 154 out of 154 places after structural reductions.
[2023-03-19 15:15:39] [INFO ] Flatten gal took : 45 ms
[2023-03-19 15:15:39] [INFO ] Flatten gal took : 37 ms
[2023-03-19 15:15:39] [INFO ] Input system was already deterministic with 236 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 355 ms. (steps per millisecond=28 ) properties (out of 62) seen :61
Finished Best-First random walk after 3487 steps, including 1 resets, run visited all 1 properties in 10 ms. (steps per millisecond=348 )
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 16 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 22 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 236 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 150 transition count 232
Applied a total of 8 rules in 23 ms. Remains 150 /154 variables (removed 4) and now considering 232/236 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 150/154 places, 232/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 232 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Performed 64 Post agglomeration using F-continuation condition.Transition count delta: 64
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 154 transition count 172
Reduce places removed 64 places and 0 transitions.
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 80 rules applied. Total rules applied 144 place count 90 transition count 156
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 152 place count 86 transition count 152
Applied a total of 152 rules in 20 ms. Remains 86 /154 variables (removed 68) and now considering 152/236 (removed 84) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 86/154 places, 152/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 152 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 5 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 9 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 7 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Applied a total of 0 rules in 1 ms. Remains 154 /154 variables (removed 0) and now considering 236/236 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 154/154 places, 236/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 9 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 23 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 236 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 8 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 9 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 150 transition count 232
Applied a total of 8 rules in 11 ms. Remains 150 /154 variables (removed 4) and now considering 232/236 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 150/154 places, 232/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 232 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Applied a total of 0 rules in 1 ms. Remains 154 /154 variables (removed 0) and now considering 236/236 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 154/154 places, 236/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 10 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 236 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 108 transition count 190
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 108 transition count 190
Applied a total of 92 rules in 6 ms. Remains 108 /154 variables (removed 46) and now considering 190/236 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 108/154 places, 190/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 6 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 6 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 190 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 47 places :
Symmetric choice reduction at 0 with 47 rule applications. Total rules 47 place count 107 transition count 189
Iterating global reduction 0 with 47 rules applied. Total rules applied 94 place count 107 transition count 189
Applied a total of 94 rules in 6 ms. Remains 107 /154 variables (removed 47) and now considering 189/236 (removed 47) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 107/154 places, 189/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 6 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 6 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 189 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 4 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 4 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 108 transition count 190
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 108 transition count 190
Applied a total of 92 rules in 3 ms. Remains 108 /154 variables (removed 46) and now considering 190/236 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 108/154 places, 190/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 6 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 190 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 45 places :
Symmetric choice reduction at 0 with 45 rule applications. Total rules 45 place count 109 transition count 191
Iterating global reduction 0 with 45 rules applied. Total rules applied 90 place count 109 transition count 191
Applied a total of 90 rules in 3 ms. Remains 109 /154 variables (removed 45) and now considering 191/236 (removed 45) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 109/154 places, 191/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 6 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 191 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Performed 61 Post agglomeration using F-continuation condition.Transition count delta: 61
Iterating post reduction 0 with 61 rules applied. Total rules applied 61 place count 154 transition count 175
Reduce places removed 61 places and 0 transitions.
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 77 rules applied. Total rules applied 138 place count 93 transition count 159
Performed 15 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 15 Pre rules applied. Total rules applied 138 place count 93 transition count 144
Deduced a syphon composed of 15 places in 1 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 2 with 30 rules applied. Total rules applied 168 place count 78 transition count 144
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 176 place count 74 transition count 140
Applied a total of 176 rules in 11 ms. Remains 74 /154 variables (removed 80) and now considering 140/236 (removed 96) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 74/154 places, 140/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 140 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 108 transition count 190
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 108 transition count 190
Applied a total of 92 rules in 2 ms. Remains 108 /154 variables (removed 46) and now considering 190/236 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 108/154 places, 190/236 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 6 ms
[2023-03-19 15:15:40] [INFO ] Input system was already deterministic with 190 transitions.
[2023-03-19 15:15:40] [INFO ] Flatten gal took : 15 ms
[2023-03-19 15:15:41] [INFO ] Flatten gal took : 14 ms
[2023-03-19 15:15:41] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 14 ms.
[2023-03-19 15:15:41] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 154 places, 236 transitions and 708 arcs took 2 ms.
Total runtime 2867 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-PT-Z4T4N04
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679239063426
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 45 (type EXCL) for 44 UtilityControlRoom-PT-Z4T4N04-CTLFireability-12
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-CTLFireability-12
lola: result : false
lola: markings : 39
lola: fired transitions : 42
lola: time used : 0.000000
lola: memory pages used : 1
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 30 (type EXCL) for 29 UtilityControlRoom-PT-Z4T4N04-CTLFireability-07
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 61 (type SKEL/SRCH) for 15 UtilityControlRoom-PT-Z4T4N04-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 61 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T4N04-CTLFireability-05
lola: result : false
lola: markings : 22
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 30 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-CTLFireability-07
lola: result : false
lola: markings : 945
lola: fired transitions : 2974
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 UtilityControlRoom-PT-Z4T4N04-CTLFireability-03
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 10 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-CTLFireability-03
lola: result : true
lola: markings : 2283
lola: fired transitions : 5017
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 58 (type EXCL) for 57 UtilityControlRoom-PT-Z4T4N04-CTLFireability-15
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 58 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-CTLFireability-15
lola: result : true
lola: markings : 23041
lola: fired transitions : 100936
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 47 UtilityControlRoom-PT-Z4T4N04-CTLFireability-13
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-CTLFireability-13
lola: result : true
lola: markings : 42
lola: fired transitions : 45
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 UtilityControlRoom-PT-Z4T4N04-CTLFireability-11
lola: time limit : 257 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-08: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z4T4N04-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/257 5/32 UtilityControlRoom-PT-Z4T4N04-CTLFireability-11 1028489 m, 205697 m/sec, 1861665 t fired, .
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UtilityControlRoom-PT-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-08: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/257 9/32 UtilityControlRoom-PT-Z4T4N04-CTLFireability-11 1883055 m, 170913 m/sec, 3624663 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-08: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 15/257 13/32 UtilityControlRoom-PT-Z4T4N04-CTLFireability-11 2619191 m, 147227 m/sec, 5261974 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-08: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 20/257 16/32 UtilityControlRoom-PT-Z4T4N04-CTLFireability-11 3304188 m, 136999 m/sec, 6886369 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N04-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-08: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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FINAL RESULTS
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-PT-Z4T4N04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912704101194"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N04.tgz
mv UtilityControlRoom-PT-Z4T4N04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;