fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r487-tall-167912703901082
Last Updated
May 14, 2023

About the Execution of LoLa+red for UtilityControlRoom-COL-Z4T4N10

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
13514.472 709833.00 695331.00 2210.90 T??T?T???????T?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703901082.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-COL-Z4T4N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703901082
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 8.7K Feb 26 14:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 26 14:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Feb 26 14:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 78K Feb 26 14:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 17:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 17:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 10K Feb 26 15:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 26 15:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Feb 26 15:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 26 15:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:26 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:26 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679232011026

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-COL-Z4T4N10
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 13:20:12] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 13:20:12] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 13:20:12] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-19 13:20:12] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-19 13:20:13] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 607 ms
[2023-03-19 13:20:13] [INFO ] Imported 13 HL places and 12 HL transitions for a total of 376 PT places and 750.0 transition bindings in 12 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
[2023-03-19 13:20:13] [INFO ] Built PT skeleton of HLPN with 13 places and 12 transitions 37 arcs in 4 ms.
[2023-03-19 13:20:13] [INFO ] Skeletonized 16 HLPN properties in 3 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 7 properties that can be checked using skeleton over-approximation.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 903 steps, including 0 resets, run visited all 17 properties in 21 ms. (steps per millisecond=43 )
[2023-03-19 13:20:13] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:20:13] [INFO ] Flatten gal took : 4 ms
Transition timeout forces synchronizations/join behavior on parameter c of sort Cli
Domain [Cli(10), Z(4), Z(4)] of place MovetoZ breaks symmetries in sort Z
[2023-03-19 13:20:13] [INFO ] Unfolded HLPN to a Petri net with 376 places and 750 transitions 2410 arcs in 27 ms.
[2023-03-19 13:20:13] [INFO ] Unfolded 16 HLPN properties in 3 ms.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 13:20:13] [INFO ] Reduced 30 identical enabling conditions.
Ensure Unique test removed 160 transitions
Reduce redundant transitions removed 160 transitions.
Support contains 376 out of 376 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 20 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
// Phase 1: matrix 590 rows 376 cols
[2023-03-19 13:20:13] [INFO ] Computed 23 place invariants in 26 ms
[2023-03-19 13:20:13] [INFO ] Implicit Places using invariants in 229 ms returned []
[2023-03-19 13:20:13] [INFO ] Invariant cache hit.
[2023-03-19 13:20:13] [INFO ] Implicit Places using invariants and state equation in 206 ms returned []
Implicit Place search using SMT with State Equation took 474 ms to find 0 implicit places.
[2023-03-19 13:20:13] [INFO ] Invariant cache hit.
[2023-03-19 13:20:14] [INFO ] Dead Transitions using invariants and state equation in 299 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 796 ms. Remains : 376/376 places, 590/590 transitions.
Support contains 376 out of 376 places after structural reductions.
[2023-03-19 13:20:14] [INFO ] Flatten gal took : 114 ms
[2023-03-19 13:20:15] [INFO ] Flatten gal took : 109 ms
[2023-03-19 13:20:16] [INFO ] Input system was already deterministic with 590 transitions.
Finished random walk after 571 steps, including 0 resets, run visited all 48 properties in 44 ms. (steps per millisecond=12 )
[2023-03-19 13:20:16] [INFO ] Flatten gal took : 67 ms
[2023-03-19 13:20:17] [INFO ] Flatten gal took : 111 ms
[2023-03-19 13:20:18] [INFO ] Input system was already deterministic with 590 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 18 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 24 ms
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 24 ms
[2023-03-19 13:20:18] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Drop transitions removed 160 transitions
Trivial Post-agglo rules discarded 160 transitions
Performed 160 trivial Post agglomeration. Transition count delta: 160
Iterating post reduction 0 with 160 rules applied. Total rules applied 160 place count 376 transition count 430
Reduce places removed 160 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 200 rules applied. Total rules applied 360 place count 216 transition count 390
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 363 place count 213 transition count 270
Iterating global reduction 2 with 3 rules applied. Total rules applied 366 place count 213 transition count 270
Discarding 30 places :
Symmetric choice reduction at 2 with 30 rule applications. Total rules 396 place count 183 transition count 240
Iterating global reduction 2 with 30 rules applied. Total rules applied 426 place count 183 transition count 240
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 446 place count 173 transition count 230
Applied a total of 446 rules in 49 ms. Remains 173 /376 variables (removed 203) and now considering 230/590 (removed 360) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 49 ms. Remains : 173/376 places, 230/590 transitions.
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:20:18] [INFO ] Input system was already deterministic with 230 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 3 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 20 ms
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 24 ms
[2023-03-19 13:20:18] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 12 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 19 ms
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 21 ms
[2023-03-19 13:20:18] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 7 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 22 ms
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 20 ms
[2023-03-19 13:20:18] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 11 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 14 ms
[2023-03-19 13:20:18] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 2 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 19 ms
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 23 ms
[2023-03-19 13:20:18] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Performed 160 Post agglomeration using F-continuation condition.Transition count delta: 160
Iterating post reduction 0 with 160 rules applied. Total rules applied 160 place count 376 transition count 430
Reduce places removed 160 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 200 rules applied. Total rules applied 360 place count 216 transition count 390
Applied a total of 360 rules in 27 ms. Remains 216 /376 variables (removed 160) and now considering 390/590 (removed 200) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 216/376 places, 390/590 transitions.
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 17 ms
[2023-03-19 13:20:18] [INFO ] Input system was already deterministic with 390 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 8 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 18 ms
[2023-03-19 13:20:18] [INFO ] Flatten gal took : 22 ms
[2023-03-19 13:20:18] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 4 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 16 ms
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 21 ms
[2023-03-19 13:20:19] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 7 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 15 ms
[2023-03-19 13:20:19] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 4 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 15 ms
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 18 ms
[2023-03-19 13:20:19] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 2 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 15 ms
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 16 ms
[2023-03-19 13:20:19] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 2 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 19 ms
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 28 ms
[2023-03-19 13:20:19] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 8 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 14 ms
[2023-03-19 13:20:19] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 6 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 14 ms
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 21 ms
[2023-03-19 13:20:19] [INFO ] Input system was already deterministic with 470 transitions.
[2023-03-19 13:20:19] [INFO ] Flatten gal took : 90 ms
[2023-03-19 13:20:20] [INFO ] Flatten gal took : 91 ms
[2023-03-19 13:20:21] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 41 ms.
[2023-03-19 13:20:21] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 376 places, 590 transitions and 1770 arcs took 2 ms.
Total runtime 8809 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-COL-Z4T4N10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

FORMULA UtilityControlRoom-COL-Z4T4N10-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N10-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N10-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N10-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679232720859

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 16 (type EXCL) for 15 UtilityControlRoom-COL-Z4T4N10-CTLFireability-05
lola: time limit : 178 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 16 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-05
lola: result : true
lola: markings : 43023
lola: fired transitions : 74215
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 UtilityControlRoom-COL-Z4T4N10-CTLFireability-13
lola: time limit : 222 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 40 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-13
lola: result : true
lola: markings : 6437
lola: fired transitions : 10058
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14
lola: time limit : 254 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 4/254 8/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 1264727 m, 252945 m/sec, 1461376 t fired, .

Time elapsed: 37 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 9/254 13/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 2223759 m, 191806 m/sec, 2840171 t fired, .

Time elapsed: 42 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 14/254 15/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 2693675 m, 93983 m/sec, 3900885 t fired, .

Time elapsed: 47 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 19/254 17/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 3140709 m, 89406 m/sec, 4985661 t fired, .

Time elapsed: 52 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 24/254 20/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 3590403 m, 89938 m/sec, 6076646 t fired, .

Time elapsed: 57 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 29/254 22/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 4025955 m, 87110 m/sec, 7189982 t fired, .

Time elapsed: 62 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 34/254 24/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 4467340 m, 88277 m/sec, 8294333 t fired, .

Time elapsed: 67 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 39/254 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 4912516 m, 89035 m/sec, 9393788 t fired, .

Time elapsed: 72 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 44/254 28/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 5331412 m, 83779 m/sec, 10519856 t fired, .

Time elapsed: 77 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 49/254 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 5761488 m, 86015 m/sec, 11628536 t fired, .

Time elapsed: 82 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 54/254 32/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 6168360 m, 81374 m/sec, 12755895 t fired, .

Time elapsed: 87 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 92 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15
lola: time limit : 269 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/269 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 1731168 m, 346233 m/sec, 1980764 t fired, .

Time elapsed: 97 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/269 15/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 2563664 m, 166499 m/sec, 3482934 t fired, .

Time elapsed: 102 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/269 17/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 3006304 m, 88528 m/sec, 4833287 t fired, .

Time elapsed: 107 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 20/269 19/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 3437879 m, 86315 m/sec, 6170824 t fired, .

Time elapsed: 112 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/269 21/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 3853921 m, 83208 m/sec, 7540844 t fired, .

Time elapsed: 117 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 30/269 23/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 4278993 m, 85014 m/sec, 8886194 t fired, .

Time elapsed: 122 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 35/269 25/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 4692264 m, 82654 m/sec, 10298608 t fired, .

Time elapsed: 127 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 40/269 27/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 5077354 m, 77018 m/sec, 11655182 t fired, .

Time elapsed: 132 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 45/269 29/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 5483166 m, 81162 m/sec, 13032118 t fired, .

Time elapsed: 137 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 50/269 31/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 5905738 m, 84514 m/sec, 14399264 t fired, .

Time elapsed: 142 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 46 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 147 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 37 (type EXCL) for 36 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12
lola: time limit : 287 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/287 5/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 767849 m, 153569 m/sec, 1405772 t fired, .

Time elapsed: 152 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/287 9/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 1413970 m, 129224 m/sec, 2617903 t fired, .

Time elapsed: 157 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/287 13/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 2047947 m, 126795 m/sec, 3817506 t fired, .

Time elapsed: 162 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/287 16/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 2637944 m, 117999 m/sec, 4937001 t fired, .

Time elapsed: 167 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/287 20/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 3253334 m, 123078 m/sec, 6109794 t fired, .

Time elapsed: 172 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 30/287 23/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 3849526 m, 119238 m/sec, 7246865 t fired, .

Time elapsed: 177 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 35/287 27/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 4396120 m, 109318 m/sec, 8292879 t fired, .

Time elapsed: 182 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 40/287 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 4966388 m, 114053 m/sec, 9385614 t fired, .

Time elapsed: 187 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 37 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 192 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 34 (type EXCL) for 33 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11
lola: time limit : 309 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/309 4/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 577306 m, 115461 m/sec, 1799320 t fired, .

Time elapsed: 197 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/309 8/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 1133349 m, 111208 m/sec, 3567750 t fired, .

Time elapsed: 202 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/309 11/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 1653974 m, 104125 m/sec, 5240384 t fired, .

Time elapsed: 207 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 20/309 14/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 2162028 m, 101610 m/sec, 6866234 t fired, .

Time elapsed: 212 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 25/309 17/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 2677838 m, 103162 m/sec, 8525105 t fired, .

Time elapsed: 217 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 30/309 20/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 3198239 m, 104080 m/sec, 10207866 t fired, .

Time elapsed: 222 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 35/309 23/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 3695575 m, 99467 m/sec, 11817115 t fired, .

Time elapsed: 227 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 40/309 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 4187302 m, 98345 m/sec, 13412764 t fired, .

Time elapsed: 232 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 45/309 29/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 4674034 m, 97346 m/sec, 15002251 t fired, .

Time elapsed: 237 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 50/309 32/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 5166359 m, 98465 m/sec, 16603020 t fired, .

Time elapsed: 242 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 34 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 247 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 30 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10
lola: time limit : 335 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/335 5/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 764390 m, 152878 m/sec, 1399255 t fired, .

Time elapsed: 252 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/335 9/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 1442332 m, 135588 m/sec, 2671856 t fired, .

Time elapsed: 257 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/335 13/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 2057916 m, 123116 m/sec, 3836580 t fired, .

Time elapsed: 262 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/335 16/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 2657202 m, 119857 m/sec, 4973442 t fired, .

Time elapsed: 267 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 25/335 20/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 3264578 m, 121475 m/sec, 6130255 t fired, .

Time elapsed: 272 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 30/335 23/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 3832680 m, 113620 m/sec, 7214602 t fired, .

Time elapsed: 277 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 35/335 27/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 4395410 m, 112546 m/sec, 8291557 t fired, .

Time elapsed: 282 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 40/335 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 4983537 m, 117625 m/sec, 9418178 t fired, .

Time elapsed: 287 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 292 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 27 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09
lola: time limit : 367 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 6/367 3/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 464518 m, 92903 m/sec, 1358705 t fired, .

Time elapsed: 298 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 11/367 5/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 891851 m, 85466 m/sec, 2613614 t fired, .

Time elapsed: 303 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 16/367 7/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 1306782 m, 82986 m/sec, 3830962 t fired, .

Time elapsed: 308 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 21/367 9/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 1715158 m, 81675 m/sec, 5025977 t fired, .

Time elapsed: 313 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 26/367 11/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 2120048 m, 80978 m/sec, 6219070 t fired, .

Time elapsed: 318 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 31/367 13/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 2519182 m, 79826 m/sec, 7402236 t fired, .

Time elapsed: 323 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 36/367 15/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 2917540 m, 79671 m/sec, 8579122 t fired, .

Time elapsed: 328 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 41/367 17/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 3312390 m, 78970 m/sec, 9745423 t fired, .

Time elapsed: 333 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 46/367 19/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 3705516 m, 78625 m/sec, 10910201 t fired, .

Time elapsed: 338 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 51/367 21/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 4097784 m, 78453 m/sec, 12066655 t fired, .

Time elapsed: 343 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 56/367 23/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 4491170 m, 78677 m/sec, 13220252 t fired, .

Time elapsed: 348 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 61/367 25/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 4879246 m, 77615 m/sec, 14368009 t fired, .

Time elapsed: 353 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 66/367 27/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 5270450 m, 78240 m/sec, 15520907 t fired, .

Time elapsed: 358 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 71/367 29/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 5659738 m, 77857 m/sec, 16675297 t fired, .

Time elapsed: 363 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 76/367 31/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 6056985 m, 79449 m/sec, 17851490 t fired, .

Time elapsed: 368 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 373 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08
lola: time limit : 403 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/403 5/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 800857 m, 160171 m/sec, 1466978 t fired, .

Time elapsed: 378 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/403 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 1502873 m, 140403 m/sec, 2786518 t fired, .

Time elapsed: 383 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/403 14/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 2160931 m, 131611 m/sec, 4031115 t fired, .

Time elapsed: 388 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/403 17/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 2790807 m, 125975 m/sec, 5229752 t fired, .

Time elapsed: 393 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/403 21/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 3405375 m, 122913 m/sec, 6398573 t fired, .

Time elapsed: 398 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 30/403 24/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 4002886 m, 119502 m/sec, 7539525 t fired, .

Time elapsed: 403 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 35/403 28/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 4590894 m, 117601 m/sec, 8664271 t fired, .

Time elapsed: 408 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 40/403 31/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 5169039 m, 115629 m/sec, 9773600 t fired, .

Time elapsed: 413 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 418 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06
lola: time limit : 454 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/454 4/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 646235 m, 129247 m/sec, 1570957 t fired, .

Time elapsed: 423 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/454 7/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 1209998 m, 112752 m/sec, 3148108 t fired, .

Time elapsed: 428 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/454 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 1770427 m, 112085 m/sec, 4714098 t fired, .

Time elapsed: 433 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/454 13/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 2361238 m, 118162 m/sec, 6206272 t fired, .

Time elapsed: 438 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/454 15/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 2916174 m, 110987 m/sec, 7724069 t fired, .

Time elapsed: 443 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/454 18/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 3457453 m, 108255 m/sec, 9230222 t fired, .

Time elapsed: 448 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/454 21/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 4028901 m, 114289 m/sec, 10725936 t fired, .

Time elapsed: 453 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 40/454 24/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 4592971 m, 112814 m/sec, 12228231 t fired, .

Time elapsed: 458 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 45/454 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 5134790 m, 108363 m/sec, 13706756 t fired, .

Time elapsed: 463 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 50/454 29/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 5684684 m, 109978 m/sec, 15214422 t fired, .

Time elapsed: 468 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 55/454 32/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 6265562 m, 116175 m/sec, 16677996 t fired, .

Time elapsed: 473 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 478 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04
lola: time limit : 520 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/520 5/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 779729 m, 155945 m/sec, 1347555 t fired, .

Time elapsed: 483 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/520 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 1579214 m, 159897 m/sec, 2631769 t fired, .

Time elapsed: 488 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/520 15/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 2391997 m, 162556 m/sec, 3915933 t fired, .

Time elapsed: 493 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/520 20/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 3178545 m, 157309 m/sec, 5164576 t fired, .

Time elapsed: 498 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/520 25/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 3991292 m, 162549 m/sec, 6450709 t fired, .

Time elapsed: 503 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/520 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 4839572 m, 169656 m/sec, 7796036 t fired, .

Time elapsed: 508 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 513 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02
lola: time limit : 617 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/617 6/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 1092930 m, 218586 m/sec, 2061922 t fired, .

Time elapsed: 518 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/617 11/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 2123973 m, 206208 m/sec, 4176398 t fired, .

Time elapsed: 523 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/617 16/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 3162056 m, 207616 m/sec, 6298620 t fired, .

Time elapsed: 528 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/617 21/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 4166119 m, 200812 m/sec, 8280377 t fired, .

Time elapsed: 533 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/617 25/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 5029005 m, 172577 m/sec, 10183476 t fired, .

Time elapsed: 538 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/617 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 6017372 m, 197673 m/sec, 12050351 t fired, .

Time elapsed: 543 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 548 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01
lola: time limit : 763 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 5/763 2/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 378742 m, 75748 m/sec, 1364161 t fired, .

Time elapsed: 553 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 10/763 4/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 736094 m, 71470 m/sec, 2747569 t fired, .

Time elapsed: 558 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 15/763 5/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 1000939 m, 52969 m/sec, 4144911 t fired, .

Time elapsed: 563 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 20/763 7/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 1383468 m, 76505 m/sec, 5521002 t fired, .

Time elapsed: 568 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 25/763 9/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 1718690 m, 67044 m/sec, 6896272 t fired, .

Time elapsed: 573 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 30/763 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 1979490 m, 52160 m/sec, 8225130 t fired, .

Time elapsed: 578 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 35/763 12/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 2360653 m, 76232 m/sec, 9593983 t fired, .

Time elapsed: 583 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 40/763 13/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 2683616 m, 64592 m/sec, 10952827 t fired, .

Time elapsed: 588 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 45/763 14/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 2949021 m, 53081 m/sec, 12280321 t fired, .

Time elapsed: 593 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 50/763 16/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 3326770 m, 75549 m/sec, 13619304 t fired, .

Time elapsed: 598 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 55/763 17/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 3651013 m, 64848 m/sec, 14972336 t fired, .

Time elapsed: 603 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 60/763 19/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 3920758 m, 53949 m/sec, 16324821 t fired, .

Time elapsed: 608 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 65/763 20/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 4304966 m, 76841 m/sec, 17687962 t fired, .

Time elapsed: 613 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 70/763 22/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 4607116 m, 60430 m/sec, 18994250 t fired, .

Time elapsed: 618 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 75/763 23/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 4848665 m, 48309 m/sec, 20284745 t fired, .

Time elapsed: 623 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 80/763 25/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 5235081 m, 77283 m/sec, 21675172 t fired, .

Time elapsed: 628 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 85/763 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 5583758 m, 69735 m/sec, 23094740 t fired, .

Time elapsed: 633 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 90/763 27/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 5822457 m, 47739 m/sec, 24412759 t fired, .

Time elapsed: 638 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 95/763 29/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 6203916 m, 76291 m/sec, 25783692 t fired, .

Time elapsed: 643 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 100/763 31/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 6575298 m, 74276 m/sec, 27220901 t fired, .

Time elapsed: 648 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 105/763 32/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 6809999 m, 46940 m/sec, 28529114 t fired, .

Time elapsed: 653 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 658 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 UtilityControlRoom-COL-Z4T4N10-CTLFireability-03
lola: time limit : 980 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-03
lola: result : true
lola: markings : 2722
lola: fired transitions : 5323
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-COL-Z4T4N10-CTLFireability-00
lola: time limit : 1471 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-00
lola: result : true
lola: markings : 41994
lola: fired transitions : 46092
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07
lola: time limit : 2942 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/2942 5/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 910867 m, 182173 m/sec, 2463470 t fired, .

Time elapsed: 663 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/2942 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 1789659 m, 175758 m/sec, 4873668 t fired, .

Time elapsed: 668 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/2942 14/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 2650175 m, 172103 m/sec, 7250998 t fired, .

Time elapsed: 673 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/2942 19/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 3471916 m, 164348 m/sec, 9543884 t fired, .

Time elapsed: 678 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 25/2942 23/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 4264303 m, 158477 m/sec, 11779506 t fired, .

Time elapsed: 683 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 30/2942 27/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 5044975 m, 156134 m/sec, 13982761 t fired, .

Time elapsed: 688 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 35/2942 31/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 5812798 m, 153564 m/sec, 16155480 t fired, .

Time elapsed: 693 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 22 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 698 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL unknown AGGR


Time elapsed: 698 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z4T4N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-COL-Z4T4N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703901082"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z4T4N10.tgz
mv UtilityControlRoom-COL-Z4T4N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;