fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r487-tall-167912703901074
Last Updated
May 14, 2023

About the Execution of LoLa+red for UtilityControlRoom-COL-Z4T4N08

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
9251.060 456071.00 450473.00 1417.30 ????????FTFT?T?T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703901074.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-COL-Z4T4N08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703901074
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 500K
-rw-r--r-- 1 mcc users 6.2K Feb 26 14:44 CTLCardinality.txt
-rw-r--r-- 1 mcc users 51K Feb 26 14:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 26 14:42 CTLFireability.txt
-rw-r--r-- 1 mcc users 63K Feb 26 14:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 17:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 26 14:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 140K Feb 26 14:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 14:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 85K Feb 26 14:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:26 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:26 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z4T4N08-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679231580161

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-COL-Z4T4N08
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 13:13:01] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 13:13:01] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 13:13:01] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-19 13:13:01] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-19 13:13:02] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 597 ms
[2023-03-19 13:13:02] [INFO ] Imported 13 HL places and 12 HL transitions for a total of 302 PT places and 600.0 transition bindings in 12 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 12 ms.
[2023-03-19 13:13:02] [INFO ] Built PT skeleton of HLPN with 13 places and 12 transitions 37 arcs in 3 ms.
[2023-03-19 13:13:02] [INFO ] Skeletonized 16 HLPN properties in 3 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 8 properties that can be checked using skeleton over-approximation.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 6780 steps, including 2 resets, run visited all 14 properties in 43 ms. (steps per millisecond=157 )
[2023-03-19 13:13:02] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:13:02] [INFO ] Flatten gal took : 2 ms
Transition timeout forces synchronizations/join behavior on parameter c of sort Cli
Domain [Cli(8), Z(4), Z(4)] of place MovetoZ breaks symmetries in sort Z
[2023-03-19 13:13:02] [INFO ] Unfolded HLPN to a Petri net with 302 places and 600 transitions 1928 arcs in 21 ms.
[2023-03-19 13:13:02] [INFO ] Unfolded 16 HLPN properties in 1 ms.
[2023-03-19 13:13:02] [INFO ] Reduced 24 identical enabling conditions.
[2023-03-19 13:13:02] [INFO ] Reduced 24 identical enabling conditions.
[2023-03-19 13:13:02] [INFO ] Reduced 24 identical enabling conditions.
[2023-03-19 13:13:02] [INFO ] Reduced 24 identical enabling conditions.
[2023-03-19 13:13:02] [INFO ] Reduced 24 identical enabling conditions.
[2023-03-19 13:13:02] [INFO ] Reduced 24 identical enabling conditions.
[2023-03-19 13:13:02] [INFO ] Reduced 24 identical enabling conditions.
[2023-03-19 13:13:02] [INFO ] Reduced 24 identical enabling conditions.
[2023-03-19 13:13:02] [INFO ] Reduced 24 identical enabling conditions.
Ensure Unique test removed 128 transitions
Reduce redundant transitions removed 128 transitions.
Support contains 302 out of 302 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Applied a total of 0 rules in 8 ms. Remains 302 /302 variables (removed 0) and now considering 472/472 (removed 0) transitions.
// Phase 1: matrix 472 rows 302 cols
[2023-03-19 13:13:02] [INFO ] Computed 19 place invariants in 26 ms
[2023-03-19 13:13:02] [INFO ] Implicit Places using invariants in 214 ms returned []
[2023-03-19 13:13:02] [INFO ] Invariant cache hit.
[2023-03-19 13:13:02] [INFO ] Implicit Places using invariants and state equation in 164 ms returned []
Implicit Place search using SMT with State Equation took 398 ms to find 0 implicit places.
[2023-03-19 13:13:02] [INFO ] Invariant cache hit.
[2023-03-19 13:13:03] [INFO ] Dead Transitions using invariants and state equation in 253 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 662 ms. Remains : 302/302 places, 472/472 transitions.
Support contains 302 out of 302 places after structural reductions.
[2023-03-19 13:13:03] [INFO ] Flatten gal took : 78 ms
[2023-03-19 13:13:03] [INFO ] Flatten gal took : 76 ms
[2023-03-19 13:13:04] [INFO ] Input system was already deterministic with 472 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 250 ms. (steps per millisecond=40 ) properties (out of 33) seen :31
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 82 ms. (steps per millisecond=121 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 69 ms. (steps per millisecond=144 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-19 13:13:04] [INFO ] Invariant cache hit.
[2023-03-19 13:13:05] [INFO ] After 55ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-19 13:13:05] [INFO ] Flatten gal took : 61 ms
[2023-03-19 13:13:05] [INFO ] Flatten gal took : 71 ms
[2023-03-19 13:13:06] [INFO ] Input system was already deterministic with 472 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Discarding 96 places :
Symmetric choice reduction at 0 with 96 rule applications. Total rules 96 place count 206 transition count 376
Iterating global reduction 0 with 96 rules applied. Total rules applied 192 place count 206 transition count 376
Applied a total of 192 rules in 14 ms. Remains 206 /302 variables (removed 96) and now considering 376/472 (removed 96) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 206/302 places, 376/472 transitions.
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 15 ms
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 16 ms
[2023-03-19 13:13:06] [INFO ] Input system was already deterministic with 376 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Discarding 96 places :
Symmetric choice reduction at 0 with 96 rule applications. Total rules 96 place count 206 transition count 376
Iterating global reduction 0 with 96 rules applied. Total rules applied 192 place count 206 transition count 376
Applied a total of 192 rules in 24 ms. Remains 206 /302 variables (removed 96) and now considering 376/472 (removed 96) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 206/302 places, 376/472 transitions.
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 16 ms
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 17 ms
[2023-03-19 13:13:06] [INFO ] Input system was already deterministic with 376 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Discarding 96 places :
Symmetric choice reduction at 0 with 96 rule applications. Total rules 96 place count 206 transition count 376
Iterating global reduction 0 with 96 rules applied. Total rules applied 192 place count 206 transition count 376
Applied a total of 192 rules in 17 ms. Remains 206 /302 variables (removed 96) and now considering 376/472 (removed 96) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 206/302 places, 376/472 transitions.
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 12 ms
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 12 ms
[2023-03-19 13:13:06] [INFO ] Input system was already deterministic with 376 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Discarding 96 places :
Symmetric choice reduction at 0 with 96 rule applications. Total rules 96 place count 206 transition count 376
Iterating global reduction 0 with 96 rules applied. Total rules applied 192 place count 206 transition count 376
Applied a total of 192 rules in 5 ms. Remains 206 /302 variables (removed 96) and now considering 376/472 (removed 96) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 206/302 places, 376/472 transitions.
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 16 ms
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 20 ms
[2023-03-19 13:13:06] [INFO ] Input system was already deterministic with 376 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Applied a total of 0 rules in 1 ms. Remains 302 /302 variables (removed 0) and now considering 472/472 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 302/302 places, 472/472 transitions.
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 16 ms
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 17 ms
[2023-03-19 13:13:06] [INFO ] Input system was already deterministic with 472 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Applied a total of 0 rules in 2 ms. Remains 302 /302 variables (removed 0) and now considering 472/472 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 302/302 places, 472/472 transitions.
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 14 ms
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 16 ms
[2023-03-19 13:13:06] [INFO ] Input system was already deterministic with 472 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Discarding 96 places :
Symmetric choice reduction at 0 with 96 rule applications. Total rules 96 place count 206 transition count 376
Iterating global reduction 0 with 96 rules applied. Total rules applied 192 place count 206 transition count 376
Applied a total of 192 rules in 15 ms. Remains 206 /302 variables (removed 96) and now considering 376/472 (removed 96) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 206/302 places, 376/472 transitions.
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 11 ms
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 11 ms
[2023-03-19 13:13:06] [INFO ] Input system was already deterministic with 376 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Applied a total of 0 rules in 2 ms. Remains 302 /302 variables (removed 0) and now considering 472/472 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 302/302 places, 472/472 transitions.
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 16 ms
[2023-03-19 13:13:06] [INFO ] Flatten gal took : 19 ms
[2023-03-19 13:13:07] [INFO ] Input system was already deterministic with 472 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Discarding 96 places :
Symmetric choice reduction at 0 with 96 rule applications. Total rules 96 place count 206 transition count 376
Iterating global reduction 0 with 96 rules applied. Total rules applied 192 place count 206 transition count 376
Applied a total of 192 rules in 3 ms. Remains 206 /302 variables (removed 96) and now considering 376/472 (removed 96) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 206/302 places, 376/472 transitions.
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 16 ms
[2023-03-19 13:13:07] [INFO ] Input system was already deterministic with 376 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Applied a total of 0 rules in 2 ms. Remains 302 /302 variables (removed 0) and now considering 472/472 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 302/302 places, 472/472 transitions.
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 17 ms
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 21 ms
[2023-03-19 13:13:07] [INFO ] Input system was already deterministic with 472 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Performed 128 Post agglomeration using F-continuation condition.Transition count delta: 128
Iterating post reduction 0 with 128 rules applied. Total rules applied 128 place count 302 transition count 344
Reduce places removed 128 places and 0 transitions.
Ensure Unique test removed 32 transitions
Reduce isomorphic transitions removed 32 transitions.
Iterating post reduction 1 with 160 rules applied. Total rules applied 288 place count 174 transition count 312
Performed 32 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 32 Pre rules applied. Total rules applied 288 place count 174 transition count 280
Deduced a syphon composed of 32 places in 0 ms
Reduce places removed 32 places and 0 transitions.
Iterating global reduction 2 with 64 rules applied. Total rules applied 352 place count 142 transition count 280
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 368 place count 134 transition count 272
Applied a total of 368 rules in 32 ms. Remains 134 /302 variables (removed 168) and now considering 272/472 (removed 200) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 33 ms. Remains : 134/302 places, 272/472 transitions.
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 8 ms
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 10 ms
[2023-03-19 13:13:07] [INFO ] Input system was already deterministic with 272 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Discarding 96 places :
Symmetric choice reduction at 0 with 96 rule applications. Total rules 96 place count 206 transition count 376
Iterating global reduction 0 with 96 rules applied. Total rules applied 192 place count 206 transition count 376
Applied a total of 192 rules in 5 ms. Remains 206 /302 variables (removed 96) and now considering 376/472 (removed 96) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 206/302 places, 376/472 transitions.
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 11 ms
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:13:07] [INFO ] Input system was already deterministic with 376 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Applied a total of 0 rules in 9 ms. Remains 302 /302 variables (removed 0) and now considering 472/472 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 302/302 places, 472/472 transitions.
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 14 ms
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 15 ms
[2023-03-19 13:13:07] [INFO ] Input system was already deterministic with 472 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Applied a total of 0 rules in 2 ms. Remains 302 /302 variables (removed 0) and now considering 472/472 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 302/302 places, 472/472 transitions.
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 12 ms
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:13:07] [INFO ] Input system was already deterministic with 472 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Discarding 96 places :
Symmetric choice reduction at 0 with 96 rule applications. Total rules 96 place count 206 transition count 376
Iterating global reduction 0 with 96 rules applied. Total rules applied 192 place count 206 transition count 376
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 0 with 16 rules applied. Total rules applied 208 place count 198 transition count 368
Applied a total of 208 rules in 16 ms. Remains 198 /302 variables (removed 104) and now considering 368/472 (removed 104) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 198/302 places, 368/472 transitions.
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 11 ms
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 12 ms
[2023-03-19 13:13:07] [INFO ] Input system was already deterministic with 368 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 302/302 places, 472/472 transitions.
Performed 128 Post agglomeration using F-continuation condition.Transition count delta: 128
Iterating post reduction 0 with 128 rules applied. Total rules applied 128 place count 302 transition count 344
Reduce places removed 128 places and 0 transitions.
Ensure Unique test removed 32 transitions
Reduce isomorphic transitions removed 32 transitions.
Iterating post reduction 1 with 160 rules applied. Total rules applied 288 place count 174 transition count 312
Applied a total of 288 rules in 13 ms. Remains 174 /302 variables (removed 128) and now considering 312/472 (removed 160) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 174/302 places, 312/472 transitions.
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 8 ms
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 9 ms
[2023-03-19 13:13:07] [INFO ] Input system was already deterministic with 312 transitions.
[2023-03-19 13:13:07] [INFO ] Flatten gal took : 61 ms
[2023-03-19 13:13:08] [INFO ] Flatten gal took : 58 ms
[2023-03-19 13:13:08] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 36 ms.
[2023-03-19 13:13:08] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 302 places, 472 transitions and 1416 arcs took 2 ms.
Total runtime 7177 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-COL-Z4T4N08
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA UtilityControlRoom-COL-Z4T4N08-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N08-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N08-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N08-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N08-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N08-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679232036232

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 13 (type EXCL) for 12 UtilityControlRoom-COL-Z4T4N08-CTLFireability-04
lola: time limit : 155 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/224 6/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-04 893551 m, 178710 m/sec, 1640134 t fired, .

Time elapsed: 21 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/224 11/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-04 1720148 m, 165319 m/sec, 3196792 t fired, .

Time elapsed: 26 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/224 16/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-04 2501793 m, 156329 m/sec, 4678769 t fired, .

Time elapsed: 31 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/224 20/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-04 3251659 m, 149973 m/sec, 6106825 t fired, .

Time elapsed: 36 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/224 24/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-04 3973075 m, 144283 m/sec, 7482619 t fired, .

Time elapsed: 41 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/224 29/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-04 4678804 m, 141145 m/sec, 8834514 t fired, .

Time elapsed: 46 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 48 (type EXCL) for 33 UtilityControlRoom-COL-Z4T4N08-CTLFireability-11
lola: time limit : 236 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-11
lola: result : false
lola: markings : 291
lola: fired transitions : 1066
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 UtilityControlRoom-COL-Z4T4N08-CTLFireability-13
lola: time limit : 253 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-13
lola: result : true
lola: markings : 9
lola: fired transitions : 53
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 UtilityControlRoom-COL-Z4T4N08-CTLFireability-09
lola: time limit : 273 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-09
lola: result : true
lola: markings : 146736
lola: fired transitions : 321717
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 UtilityControlRoom-COL-Z4T4N08-CTLFireability-08
lola: time limit : 295 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-08
lola: result : false
lola: markings : 146529
lola: fired transitions : 344724
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 UtilityControlRoom-COL-Z4T4N08-CTLFireability-07
lola: time limit : 322 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 3/322 5/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-07 832047 m, 166409 m/sec, 1612032 t fired, .

Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 8/322 10/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-07 1914323 m, 216455 m/sec, 3861170 t fired, .

Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 13/322 15/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-07 2971970 m, 211529 m/sec, 6110392 t fired, .

Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 18/322 20/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-07 3978189 m, 201243 m/sec, 8314619 t fired, .

Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 23/322 24/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-07 4892549 m, 182872 m/sec, 10516017 t fired, .

Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 28/322 29/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-07 5865074 m, 194505 m/sec, 12775660 t fired, .

Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 22 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 UtilityControlRoom-COL-Z4T4N08-CTLFireability-05
lola: time limit : 351 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/351 8/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-05 1148201 m, 229640 m/sec, 1958510 t fired, .

Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/351 14/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-05 2219153 m, 214190 m/sec, 3802372 t fired, .

Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/351 21/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-05 3218516 m, 199872 m/sec, 5563920 t fired, .

Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/351 26/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-05 4168607 m, 190018 m/sec, 7245928 t fired, .

Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/351 32/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-05 5118355 m, 189949 m/sec, 8931762 t fired, .

Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 UtilityControlRoom-COL-Z4T4N08-CTLFireability-03
lola: time limit : 387 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/387 7/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-03 1021804 m, 204360 m/sec, 1527911 t fired, .

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/387 14/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-03 1995928 m, 194824 m/sec, 3028713 t fired, .

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/387 20/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-03 2947694 m, 190353 m/sec, 4506590 t fired, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/387 26/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-03 3877745 m, 186010 m/sec, 5963002 t fired, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/387 32/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-03 4819914 m, 188433 m/sec, 7414668 t fired, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02
lola: time limit : 431 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/431 3/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 387684 m, 77536 m/sec, 2149792 t fired, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/431 5/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 743689 m, 71201 m/sec, 4197214 t fired, .

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/431 7/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 1089840 m, 69230 m/sec, 6195793 t fired, .

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/431 9/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 1428525 m, 67737 m/sec, 8165916 t fired, .

Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/431 11/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 1761413 m, 66577 m/sec, 10107841 t fired, .

Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/431 13/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 2084721 m, 64661 m/sec, 12015877 t fired, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/431 15/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 2410878 m, 65231 m/sec, 13915895 t fired, .

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/431 17/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 2731800 m, 64184 m/sec, 15783071 t fired, .

Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/431 18/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 3051318 m, 63903 m/sec, 17647550 t fired, .

Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/431 20/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 3357772 m, 61290 m/sec, 19474620 t fired, .

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 55/431 22/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 3664245 m, 61294 m/sec, 21293988 t fired, .

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 60/431 24/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 3967623 m, 60675 m/sec, 23098378 t fired, .

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 65/431 25/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 4272035 m, 60882 m/sec, 24903435 t fired, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 70/431 27/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 4598318 m, 65256 m/sec, 26785278 t fired, .

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 75/431 29/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 4901591 m, 60654 m/sec, 28581053 t fired, .

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 80/431 31/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 5211785 m, 62038 m/sec, 30362530 t fired, .

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 85/431 32/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 5512202 m, 60083 m/sec, 32120681 t fired, .

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-COL-Z4T4N08-CTLFireability-00
lola: time limit : 480 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/480 5/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-00 825030 m, 165006 m/sec, 2044196 t fired, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/480 9/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-00 1522217 m, 139437 m/sec, 4049109 t fired, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/480 13/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-00 2221261 m, 139808 m/sec, 6015259 t fired, .

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/480 17/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-00 2892276 m, 134203 m/sec, 7946169 t fired, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/480 20/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-00 3556232 m, 132791 m/sec, 9885185 t fired, .

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/480 24/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-00 4216497 m, 132053 m/sec, 11791089 t fired, .

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/480 27/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-00 4837015 m, 124103 m/sec, 13653816 t fired, .

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/480 31/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-00 5445500 m, 121697 m/sec, 15477411 t fired, .

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 30 UtilityControlRoom-COL-Z4T4N08-CTLFireability-10
lola: time limit : 553 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-10
lola: result : false
lola: markings : 49
lola: fired transitions : 172
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14
lola: time limit : 663 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/663 4/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 691205 m, 138241 m/sec, 1320906 t fired, .

Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/663 7/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 1327737 m, 127306 m/sec, 2567238 t fired, .

Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/663 11/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 1949684 m, 124389 m/sec, 3854537 t fired, .

Time elapsed: 296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/663 14/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 2564263 m, 122915 m/sec, 5101609 t fired, .

Time elapsed: 301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/663 17/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 3170695 m, 121286 m/sec, 6323584 t fired, .

Time elapsed: 306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/663 20/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 3771573 m, 120175 m/sec, 7554887 t fired, .

Time elapsed: 311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 35/663 23/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 4365390 m, 118763 m/sec, 8772966 t fired, .

Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 40/663 26/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 4952653 m, 117452 m/sec, 9995715 t fired, .

Time elapsed: 321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 45/663 29/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 5529504 m, 115370 m/sec, 11233559 t fired, .

Time elapsed: 326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 50/663 32/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 6115812 m, 117261 m/sec, 12440808 t fired, .

Time elapsed: 331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 UtilityControlRoom-COL-Z4T4N08-CTLFireability-06
lola: time limit : 816 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/816 5/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-06 864363 m, 172872 m/sec, 1960454 t fired, .

Time elapsed: 341 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/816 9/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-06 1686878 m, 164503 m/sec, 3841826 t fired, .

Time elapsed: 346 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/816 13/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-06 2488832 m, 160390 m/sec, 5713237 t fired, .

Time elapsed: 351 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/816 17/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-06 3217021 m, 145637 m/sec, 7627291 t fired, .

Time elapsed: 356 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/816 21/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-06 3970127 m, 150621 m/sec, 9586285 t fired, .

Time elapsed: 361 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/816 25/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-06 4728174 m, 151609 m/sec, 11494711 t fired, .

Time elapsed: 366 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/816 29/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-06 5460897 m, 146544 m/sec, 13378212 t fired, .

Time elapsed: 371 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 376 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 UtilityControlRoom-COL-Z4T4N08-CTLFireability-15
lola: time limit : 1074 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-15
lola: result : true
lola: markings : 198512
lola: fired transitions : 1032990
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-COL-Z4T4N08-CTLFireability-01
lola: time limit : 1611 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 3/1611 4/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-01 696398 m, 139279 m/sec, 1331626 t fired, .

Time elapsed: 381 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 8/1611 9/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-01 1748960 m, 210512 m/sec, 3505816 t fired, .

Time elapsed: 386 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 13/1611 14/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-01 2796671 m, 209542 m/sec, 5706435 t fired, .

Time elapsed: 391 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 18/1611 19/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-01 3797674 m, 200200 m/sec, 7897998 t fired, .

Time elapsed: 396 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 23/1611 23/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-01 4712965 m, 183058 m/sec, 10069791 t fired, .

Time elapsed: 401 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 28/1611 28/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-01 5689340 m, 195275 m/sec, 12338773 t fired, .

Time elapsed: 406 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 411 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 37 (type EXCL) for 36 UtilityControlRoom-COL-Z4T4N08-CTLFireability-12
lola: time limit : 3189 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/3189 6/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-12 761486 m, 152297 m/sec, 1914290 t fired, .

Time elapsed: 416 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/3189 10/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-12 1499068 m, 147516 m/sec, 3790488 t fired, .

Time elapsed: 421 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/3189 15/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-12 2224294 m, 145045 m/sec, 5643199 t fired, .

Time elapsed: 426 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/3189 20/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-12 2944766 m, 144094 m/sec, 7492604 t fired, .

Time elapsed: 431 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/3189 24/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-12 3656872 m, 142421 m/sec, 9320678 t fired, .

Time elapsed: 436 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 30/3189 29/32 UtilityControlRoom-COL-Z4T4N08-CTLFireability-12 4383471 m, 145319 m/sec, 11156664 t fired, .

Time elapsed: 441 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 37 (type EXCL) for UtilityControlRoom-COL-Z4T4N08-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 446 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N08-CTLFireability-00: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N08-CTLFireability-01: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N08-CTLFireability-02: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N08-CTLFireability-03: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N08-CTLFireability-04: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N08-CTLFireability-05: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N08-CTLFireability-06: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N08-CTLFireability-07: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-11: AXAF true state space /EXEG
UtilityControlRoom-COL-Z4T4N08-CTLFireability-12: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N08-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N08-CTLFireability-14: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N08-CTLFireability-15: CTL true CTL model checker


Time elapsed: 446 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z4T4N08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-COL-Z4T4N08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703901074"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z4T4N08.tgz
mv UtilityControlRoom-COL-Z4T4N08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;