Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703901058.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-COL-Z4T4N04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703901058
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 408K
-rw-r--r-- 1 mcc users 6.8K Feb 26 14:33 CTLCardinality.txt
-rw-r--r-- 1 mcc users 59K Feb 26 14:33 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 26 14:31 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 26 14:31 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.5K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.8K Feb 26 14:37 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 61K Feb 26 14:37 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 26 14:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Feb 26 14:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z4T4N04-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679230879939

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-COL-Z4T4N04
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 13:01:21] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 13:01:21] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 13:01:21] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-19 13:01:21] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-19 13:01:21] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 595 ms
[2023-03-19 13:01:21] [INFO ] Imported 13 HL places and 12 HL transitions for a total of 154 PT places and 300.0 transition bindings in 13 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
[2023-03-19 13:01:22] [INFO ] Built PT skeleton of HLPN with 13 places and 12 transitions 37 arcs in 3 ms.
[2023-03-19 13:01:22] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 11 properties that can be checked using skeleton over-approximation.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Incomplete random walk after 10000 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 12) seen :11
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 11 rows 13 cols
[2023-03-19 13:01:22] [INFO ] Computed 5 place invariants in 6 ms
[2023-03-19 13:01:22] [INFO ] After 115ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 11 simplifications.
[2023-03-19 13:01:22] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:01:22] [INFO ] Flatten gal took : 2 ms
Transition timeout forces synchronizations/join behavior on parameter c of sort Cli
Domain [Cli(4), Z(4), Z(4)] of place MovetoZ breaks symmetries in sort Z
[2023-03-19 13:01:22] [INFO ] Unfolded HLPN to a Petri net with 154 places and 300 transitions 964 arcs in 13 ms.
[2023-03-19 13:01:22] [INFO ] Unfolded 16 HLPN properties in 1 ms.
[2023-03-19 13:01:22] [INFO ] Reduced 12 identical enabling conditions.
[2023-03-19 13:01:22] [INFO ] Reduced 12 identical enabling conditions.
[2023-03-19 13:01:22] [INFO ] Reduced 12 identical enabling conditions.
[2023-03-19 13:01:22] [INFO ] Reduced 12 identical enabling conditions.
[2023-03-19 13:01:22] [INFO ] Reduced 12 identical enabling conditions.
Ensure Unique test removed 64 transitions
Reduce redundant transitions removed 64 transitions.
Support contains 154 out of 154 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Applied a total of 0 rules in 6 ms. Remains 154 /154 variables (removed 0) and now considering 236/236 (removed 0) transitions.
// Phase 1: matrix 236 rows 154 cols
[2023-03-19 13:01:22] [INFO ] Computed 11 place invariants in 14 ms
[2023-03-19 13:01:22] [INFO ] Implicit Places using invariants in 82 ms returned []
[2023-03-19 13:01:22] [INFO ] Invariant cache hit.
[2023-03-19 13:01:22] [INFO ] Implicit Places using invariants and state equation in 118 ms returned []
Implicit Place search using SMT with State Equation took 204 ms to find 0 implicit places.
[2023-03-19 13:01:22] [INFO ] Invariant cache hit.
[2023-03-19 13:01:22] [INFO ] Dead Transitions using invariants and state equation in 158 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 371 ms. Remains : 154/154 places, 236/236 transitions.
Support contains 154 out of 154 places after structural reductions.
[2023-03-19 13:01:22] [INFO ] Flatten gal took : 29 ms
[2023-03-19 13:01:23] [INFO ] Flatten gal took : 34 ms
[2023-03-19 13:01:23] [INFO ] Input system was already deterministic with 236 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 100 ms. (steps per millisecond=100 ) properties (out of 27) seen :26
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 98 ms. (steps per millisecond=102 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-19 13:01:23] [INFO ] Invariant cache hit.
[2023-03-19 13:01:23] [INFO ] After 131ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-19 13:01:23] [INFO ] Flatten gal took : 34 ms
[2023-03-19 13:01:23] [INFO ] Flatten gal took : 32 ms
[2023-03-19 13:01:23] [INFO ] Input system was already deterministic with 236 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 150 transition count 232
Applied a total of 8 rules in 22 ms. Remains 150 /154 variables (removed 4) and now considering 232/236 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 150/154 places, 232/236 transitions.
[2023-03-19 13:01:23] [INFO ] Flatten gal took : 12 ms
[2023-03-19 13:01:23] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 232 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Performed 64 Post agglomeration using F-continuation condition.Transition count delta: 64
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 154 transition count 172
Reduce places removed 64 places and 0 transitions.
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 80 rules applied. Total rules applied 144 place count 90 transition count 156
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 152 place count 86 transition count 152
Applied a total of 152 rules in 22 ms. Remains 86 /154 variables (removed 68) and now considering 152/236 (removed 84) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 86/154 places, 152/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 152 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 5 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 8 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 8 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 7 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 8 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 8 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Applied a total of 0 rules in 1 ms. Remains 154 /154 variables (removed 0) and now considering 236/236 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 154/154 places, 236/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 22 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 10 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 236 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 8 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 9 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 150 transition count 232
Applied a total of 8 rules in 11 ms. Remains 150 /154 variables (removed 4) and now considering 232/236 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 150/154 places, 232/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 11 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 232 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Applied a total of 0 rules in 2 ms. Remains 154 /154 variables (removed 0) and now considering 236/236 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 154/154 places, 236/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 8 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 10 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 236 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 4 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 9 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Drop transitions removed 64 transitions
Trivial Post-agglo rules discarded 64 transitions
Performed 64 trivial Post agglomeration. Transition count delta: 64
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 154 transition count 172
Reduce places removed 64 places and 0 transitions.
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 80 rules applied. Total rules applied 144 place count 90 transition count 156
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 16 Pre rules applied. Total rules applied 144 place count 90 transition count 140
Deduced a syphon composed of 16 places in 1 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 2 with 32 rules applied. Total rules applied 176 place count 74 transition count 140
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 179 place count 71 transition count 92
Iterating global reduction 2 with 3 rules applied. Total rules applied 182 place count 71 transition count 92
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 194 place count 59 transition count 80
Iterating global reduction 2 with 12 rules applied. Total rules applied 206 place count 59 transition count 80
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 218 place count 47 transition count 56
Iterating global reduction 2 with 12 rules applied. Total rules applied 230 place count 47 transition count 56
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 242 place count 35 transition count 44
Iterating global reduction 2 with 12 rules applied. Total rules applied 254 place count 35 transition count 44
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 266 place count 35 transition count 32
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 4 Pre rules applied. Total rules applied 266 place count 35 transition count 28
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 274 place count 31 transition count 28
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 282 place count 27 transition count 24
Applied a total of 282 rules in 13 ms. Remains 27 /154 variables (removed 127) and now considering 24/236 (removed 212) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 27/154 places, 24/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 1 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 1 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 24 transitions.
Finished random walk after 4 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=4 )
FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Applied a total of 0 rules in 2 ms. Remains 154 /154 variables (removed 0) and now considering 236/236 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 154/154 places, 236/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 236 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 104 place count 102 transition count 184
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 0 with 9 rules applied. Total rules applied 113 place count 97 transition count 180
Performed 16 Post agglomeration using F-continuation condition.Transition count delta: 16
Deduced a syphon composed of 16 places in 0 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 0 with 32 rules applied. Total rules applied 145 place count 81 transition count 164
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 161 place count 81 transition count 148
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 164 place count 78 transition count 100
Ensure Unique test removed 1 places
Iterating global reduction 0 with 4 rules applied. Total rules applied 168 place count 77 transition count 100
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 180 place count 65 transition count 76
Iterating global reduction 0 with 12 rules applied. Total rules applied 192 place count 65 transition count 76
Applied a total of 192 rules in 28 ms. Remains 65 /154 variables (removed 89) and now considering 76/236 (removed 160) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 65/154 places, 76/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 2 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 10 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Applied a total of 0 rules in 1 ms. Remains 154 /154 variables (removed 0) and now considering 236/236 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 154/154 places, 236/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 17 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 236 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Performed 64 Post agglomeration using F-continuation condition.Transition count delta: 64
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 154 transition count 172
Reduce places removed 64 places and 0 transitions.
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 80 rules applied. Total rules applied 144 place count 90 transition count 156
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 16 Pre rules applied. Total rules applied 144 place count 90 transition count 140
Deduced a syphon composed of 16 places in 0 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 2 with 32 rules applied. Total rules applied 176 place count 74 transition count 140
Applied a total of 176 rules in 20 ms. Remains 74 /154 variables (removed 80) and now considering 140/236 (removed 96) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 74/154 places, 140/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 140 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 2 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 19 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in LTL mode, iteration 0 : 154/154 places, 236/236 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 106 transition count 188
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 106 transition count 188
Applied a total of 96 rules in 4 ms. Remains 106 /154 variables (removed 48) and now considering 188/236 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 106/154 places, 188/236 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 8 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:01:24] [INFO ] Input system was already deterministic with 188 transitions.
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 25 ms
[2023-03-19 13:01:24] [INFO ] Flatten gal took : 16 ms
[2023-03-19 13:01:25] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 14 ms.
[2023-03-19 13:01:25] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 154 places, 236 transitions and 708 arcs took 4 ms.
Total runtime 3718 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-COL-Z4T4N04
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T4N04-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679231098779

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 69 (type SKEL/SRCH) for 41 UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 69 (type SKEL/SRCH) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: LAUNCH task # 71 (type SKEL/SRCH) for 15 UtilityControlRoom-COL-Z4T4N04-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 71 (type SKEL/SRCH) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-05
lola: result : false
lola: markings : 22
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 13 (type EXCL) for 12 UtilityControlRoom-COL-Z4T4N04-CTLFireability-04
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 13 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-04
lola: result : false
lola: markings : 225039
lola: fired transitions : 367720
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 67 (type EXCL) for 66 UtilityControlRoom-COL-Z4T4N04-CTLFireability-15
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 67 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-15
lola: result : false
lola: markings : 44
lola: fired transitions : 59
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 64 (type EXCL) for 63 UtilityControlRoom-COL-Z4T4N04-CTLFireability-14
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-14
lola: result : true
lola: markings : 352
lola: fired transitions : 454
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 58 (type EXCL) for 41 UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 41 UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 41 UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 41 UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-12
lola: result : true
lola: markings : 944
lola: fired transitions : 1079
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 UtilityControlRoom-COL-Z4T4N04-CTLFireability-10
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-10
lola: result : true
lola: markings : 25
lola: fired transitions : 54
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-08
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-08
lola: result : false
lola: markings : 92
lola: fired transitions : 210
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 UtilityControlRoom-COL-Z4T4N04-CTLFireability-07
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-07
lola: result : false
lola: markings : 945
lola: fired transitions : 2974
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 UtilityControlRoom-COL-Z4T4N04-CTLFireability-03
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-03
lola: result : true
lola: markings : 2283
lola: fired transitions : 5017
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 UtilityControlRoom-COL-Z4T4N04-CTLFireability-02
lola: time limit : 399 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 4/399 5/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-02 905349 m, 181069 m/sec, 1618047 t fired, .

Time elapsed: 7 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 9/399 9/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-02 1831074 m, 185145 m/sec, 3512686 t fired, .

Time elapsed: 12 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 14/399 13/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-02 2638374 m, 161460 m/sec, 5307406 t fired, .

Time elapsed: 17 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 19/399 16/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-02 3375986 m, 147522 m/sec, 7065378 t fired, .

Time elapsed: 22 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 24/399 19/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-02 4061478 m, 137098 m/sec, 8812926 t fired, .

Time elapsed: 27 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 29/399 22/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-02 4710438 m, 129792 m/sec, 10559459 t fired, .

Time elapsed: 32 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 34/399 25/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-02 5328688 m, 123650 m/sec, 12309644 t fired, .

Time elapsed: 37 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 39/399 28/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-02 5924076 m, 119077 m/sec, 14062623 t fired, .

Time elapsed: 42 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 44/399 31/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-02 6500624 m, 115309 m/sec, 15805674 t fired, .

Time elapsed: 47 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 7 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 52 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 39 (type EXCL) for 38 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11
lola: time limit : 443 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 5/443 6/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 1235103 m, 247020 m/sec, 2804558 t fired, .

Time elapsed: 57 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 10/443 9/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 2113229 m, 175625 m/sec, 5068268 t fired, .

Time elapsed: 62 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 15/443 13/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 2892578 m, 155869 m/sec, 7181903 t fired, .

Time elapsed: 67 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 20/443 16/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 3593611 m, 140206 m/sec, 9142474 t fired, .

Time elapsed: 72 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 25/443 19/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 4263381 m, 133954 m/sec, 11069965 t fired, .

Time elapsed: 77 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 30/443 21/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 4922020 m, 131727 m/sec, 13009547 t fired, .

Time elapsed: 82 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 35/443 24/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 5553590 m, 126314 m/sec, 14904084 t fired, .

Time elapsed: 87 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 40/443 27/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 6166892 m, 122660 m/sec, 16777763 t fired, .

Time elapsed: 92 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 45/443 29/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 6764666 m, 119554 m/sec, 18634284 t fired, .

Time elapsed: 97 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 50/443 32/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 7356651 m, 118397 m/sec, 20500226 t fired, .

Time elapsed: 102 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 39 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 107 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-COL-Z4T4N04-CTLFireability-01
lola: time limit : 499 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-01
lola: result : true
lola: markings : 19
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 72 (type EXCL) for 15 UtilityControlRoom-COL-Z4T4N04-CTLFireability-05
lola: time limit : 582 sec
lola: memory limit: 32 pages
lola: FINISHED task # 72 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-05
lola: result : false
lola: markings : 30
lola: fired transitions : 30
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 15 UtilityControlRoom-COL-Z4T4N04-CTLFireability-05
lola: time limit : 698 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-05
lola: result : false
lola: markings : 24
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 UtilityControlRoom-COL-Z4T4N04-CTLFireability-06
lola: time limit : 1164 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-06
lola: result : false
lola: markings : 40
lola: fired transitions : 80
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 60 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13
lola: time limit : 1746 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 5/1746 4/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 767640 m, 153528 m/sec, 4150583 t fired, .

Time elapsed: 112 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 10/1746 6/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 1338313 m, 114134 m/sec, 8014143 t fired, .

Time elapsed: 117 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 15/1746 9/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 1937130 m, 119763 m/sec, 11713632 t fired, .

Time elapsed: 122 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 20/1746 11/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 2487484 m, 110070 m/sec, 15404725 t fired, .

Time elapsed: 127 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 25/1746 13/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 2982286 m, 98960 m/sec, 19164544 t fired, .

Time elapsed: 132 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 30/1746 15/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3408971 m, 85337 m/sec, 22889769 t fired, .

Time elapsed: 137 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 35/1746 16/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3753655 m, 68936 m/sec, 27356672 t fired, .

Time elapsed: 142 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 40/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3808804 m, 11029 m/sec, 30677553 t fired, .

Time elapsed: 147 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 45/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3906992 m, 19637 m/sec, 33980470 t fired, .

Time elapsed: 152 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 50/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3979561 m, 14513 m/sec, 38039675 t fired, .

Time elapsed: 157 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 55/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 350 m/sec, 42278549 t fired, .

Time elapsed: 162 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 60/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 0 m/sec, 46436685 t fired, .

Time elapsed: 167 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 65/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 0 m/sec, 50456429 t fired, .

Time elapsed: 172 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 70/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 0 m/sec, 54283989 t fired, .

Time elapsed: 177 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 75/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 0 m/sec, 58220052 t fired, .

Time elapsed: 182 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 80/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 0 m/sec, 62233680 t fired, .

Time elapsed: 187 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 85/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 0 m/sec, 66332984 t fired, .

Time elapsed: 192 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 90/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 0 m/sec, 70417710 t fired, .

Time elapsed: 197 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 95/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 0 m/sec, 73492030 t fired, .

Time elapsed: 202 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 100/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 0 m/sec, 76673795 t fired, .

Time elapsed: 207 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 105/1746 17/32 UtilityControlRoom-COL-Z4T4N04-CTLFireability-13 3981312 m, 0 m/sec, 80067315 t fired, .

Time elapsed: 212 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: FINISHED task # 61 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-13
lola: result : false
lola: markings : 3981312
lola: fired transitions : 80986662
lola: time used : 106.000000
lola: memory pages used : 17
lola: LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-COL-Z4T4N04-CTLFireability-00
lola: time limit : 3387 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for UtilityControlRoom-COL-Z4T4N04-CTLFireability-00
lola: result : false
lola: markings : 85
lola: fired transitions : 186
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N04-CTLFireability-00: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-01: EG true state space / EG
UtilityControlRoom-COL-Z4T4N04-CTLFireability-02: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N04-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-05: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-11: AGEF unknown AGGR
UtilityControlRoom-COL-Z4T4N04-CTLFireability-12: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N04-CTLFireability-13: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N04-CTLFireability-15: CTL false CTL model checker


Time elapsed: 213 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z4T4N04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-COL-Z4T4N04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703901058"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z4T4N04.tgz
mv UtilityControlRoom-COL-Z4T4N04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;