About the Execution of LoLa+red for UtilityControlRoom-COL-Z4T4N02
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 400.792 | 8177.00 | 13616.00 | 426.10 | TFFFFTTFFFFFFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703901050.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-COL-Z4T4N02, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703901050
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 8.5K Feb 26 14:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 26 14:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 14:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 26 14:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 14:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 119K Feb 26 14:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 14:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 79K Feb 26 14:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z4T4N02-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679230811802
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-COL-Z4T4N02
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 13:00:13] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 13:00:13] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 13:00:13] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-19 13:00:13] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-19 13:00:13] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 627 ms
[2023-03-19 13:00:13] [INFO ] Imported 13 HL places and 12 HL transitions for a total of 80 PT places and 150.0 transition bindings in 13 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
[2023-03-19 13:00:13] [INFO ] Built PT skeleton of HLPN with 13 places and 12 transitions 37 arcs in 4 ms.
[2023-03-19 13:00:13] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Initial state reduction rules removed 2 formulas.
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 9 properties that can be checked using skeleton over-approximation.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Incomplete random walk after 10000 steps, including 2 resets, run finished after 76 ms. (steps per millisecond=131 ) properties (out of 14) seen :13
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 11 rows 13 cols
[2023-03-19 13:00:14] [INFO ] Computed 5 place invariants in 2 ms
[2023-03-19 13:00:14] [INFO ] [Real]Absence check using 5 positive place invariants in 2 ms returned sat
[2023-03-19 13:00:14] [INFO ] After 265ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 9 simplifications.
[2023-03-19 13:00:14] [INFO ] Flatten gal took : 23 ms
[2023-03-19 13:00:14] [INFO ] Flatten gal took : 4 ms
Domain [Cli(2), Z(4), Z(4)] of place MovetoZ breaks symmetries in sort Z
Transition timeout forces synchronizations/join behavior on parameter c of sort Cli
[2023-03-19 13:00:14] [INFO ] Unfolded HLPN to a Petri net with 80 places and 150 transitions 482 arcs in 10 ms.
[2023-03-19 13:00:14] [INFO ] Unfolded 14 HLPN properties in 1 ms.
[2023-03-19 13:00:14] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 13:00:14] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 13:00:14] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 13:00:14] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 13:00:14] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 13:00:14] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 13:00:14] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 13:00:14] [INFO ] Reduced 6 identical enabling conditions.
Ensure Unique test removed 32 transitions
Reduce redundant transitions removed 32 transitions.
Support contains 80 out of 80 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Applied a total of 0 rules in 5 ms. Remains 80 /80 variables (removed 0) and now considering 118/118 (removed 0) transitions.
// Phase 1: matrix 118 rows 80 cols
[2023-03-19 13:00:14] [INFO ] Computed 7 place invariants in 5 ms
[2023-03-19 13:00:14] [INFO ] Implicit Places using invariants in 66 ms returned []
[2023-03-19 13:00:14] [INFO ] Invariant cache hit.
[2023-03-19 13:00:14] [INFO ] Implicit Places using invariants and state equation in 95 ms returned []
Implicit Place search using SMT with State Equation took 165 ms to find 0 implicit places.
[2023-03-19 13:00:14] [INFO ] Invariant cache hit.
[2023-03-19 13:00:14] [INFO ] Dead Transitions using invariants and state equation in 107 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 278 ms. Remains : 80/80 places, 118/118 transitions.
Support contains 80 out of 80 places after structural reductions.
[2023-03-19 13:00:14] [INFO ] Flatten gal took : 19 ms
[2023-03-19 13:00:14] [INFO ] Flatten gal took : 23 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 118 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 80 ms. (steps per millisecond=125 ) properties (out of 32) seen :31
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 75 ms. (steps per millisecond=133 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-19 13:00:15] [INFO ] Invariant cache hit.
[2023-03-19 13:00:15] [INFO ] [Real]Absence check using 7 positive place invariants in 3 ms returned sat
[2023-03-19 13:00:15] [INFO ] After 73ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 14 simplifications.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 11 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 25 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 118 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 4 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Drop transitions removed 32 transitions
Trivial Post-agglo rules discarded 32 transitions
Performed 32 trivial Post agglomeration. Transition count delta: 32
Iterating post reduction 0 with 32 rules applied. Total rules applied 32 place count 80 transition count 86
Reduce places removed 32 places and 0 transitions.
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 1 with 40 rules applied. Total rules applied 72 place count 48 transition count 78
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 75 place count 45 transition count 54
Iterating global reduction 2 with 3 rules applied. Total rules applied 78 place count 45 transition count 54
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 84 place count 39 transition count 48
Iterating global reduction 2 with 6 rules applied. Total rules applied 90 place count 39 transition count 48
Applied a total of 90 rules in 11 ms. Remains 39 /80 variables (removed 41) and now considering 48/118 (removed 70) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 39/80 places, 48/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 3 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 2 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 48 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 3 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 4 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Applied a total of 0 rules in 0 ms. Remains 80 /80 variables (removed 0) and now considering 118/118 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 80/80 places, 118/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 118 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 2 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 1 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Applied a total of 0 rules in 1 ms. Remains 80 /80 variables (removed 0) and now considering 118/118 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 80/80 places, 118/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 118 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 4 place count 78 transition count 116
Applied a total of 4 rules in 6 ms. Remains 78 /80 variables (removed 2) and now considering 116/118 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 78/80 places, 116/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 3 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 2 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Drop transitions removed 32 transitions
Trivial Post-agglo rules discarded 32 transitions
Performed 32 trivial Post agglomeration. Transition count delta: 32
Iterating post reduction 0 with 32 rules applied. Total rules applied 32 place count 80 transition count 86
Reduce places removed 32 places and 0 transitions.
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 1 with 40 rules applied. Total rules applied 72 place count 48 transition count 78
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 8 Pre rules applied. Total rules applied 72 place count 48 transition count 70
Deduced a syphon composed of 8 places in 1 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 88 place count 40 transition count 70
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 91 place count 37 transition count 46
Iterating global reduction 2 with 3 rules applied. Total rules applied 94 place count 37 transition count 46
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 100 place count 31 transition count 40
Iterating global reduction 2 with 6 rules applied. Total rules applied 106 place count 31 transition count 40
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 112 place count 25 transition count 28
Iterating global reduction 2 with 6 rules applied. Total rules applied 118 place count 25 transition count 28
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 124 place count 19 transition count 22
Iterating global reduction 2 with 6 rules applied. Total rules applied 130 place count 19 transition count 22
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 136 place count 19 transition count 16
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 136 place count 19 transition count 14
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 140 place count 17 transition count 14
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Ensure Unique test removed 1 places
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 5 rules applied. Total rules applied 145 place count 14 transition count 12
Applied a total of 145 rules in 8 ms. Remains 14 /80 variables (removed 66) and now considering 12/118 (removed 106) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 14/80 places, 12/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 0 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 0 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 12 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=1 )
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Performed 32 Post agglomeration using F-continuation condition.Transition count delta: 32
Iterating post reduction 0 with 32 rules applied. Total rules applied 32 place count 80 transition count 86
Reduce places removed 32 places and 0 transitions.
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 1 with 40 rules applied. Total rules applied 72 place count 48 transition count 78
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 8 Pre rules applied. Total rules applied 72 place count 48 transition count 70
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 88 place count 40 transition count 70
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 92 place count 38 transition count 68
Applied a total of 92 rules in 6 ms. Remains 38 /80 variables (removed 42) and now considering 68/118 (removed 50) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 38/80 places, 68/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 2 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 2 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 68 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 1 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:00:15] [INFO ] Input system was already deterministic with 94 transitions.
[2023-03-19 13:00:15] [INFO ] Flatten gal took : 11 ms
[2023-03-19 13:00:16] [INFO ] Flatten gal took : 12 ms
[2023-03-19 13:00:16] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 11 ms.
[2023-03-19 13:00:16] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 80 places, 118 transitions and 354 arcs took 0 ms.
Total runtime 2931 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-COL-Z4T4N02
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N02-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679230819979
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 9 (type EXCL) for 0 UtilityControlRoom-COL-Z4T4N02-CTLFireability-00
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-00
lola: result : true
lola: markings : 16
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 7 (type EXCL) for 0 UtilityControlRoom-COL-Z4T4N02-CTLFireability-00
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 7 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-00
lola: result : true
lola: markings : 68
lola: fired transitions : 86
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 3 (type EXCL) for 0 UtilityControlRoom-COL-Z4T4N02-CTLFireability-00
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 3 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-00
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 12 (type EXCL) for 11 UtilityControlRoom-COL-Z4T4N02-CTLFireability-01
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 12 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-01
lola: result : false
lola: markings : 18640
lola: fired transitions : 116285
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 UtilityControlRoom-COL-Z4T4N02-CTLFireability-15
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-15
lola: result : false
lola: markings : 3
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 UtilityControlRoom-COL-Z4T4N02-CTLFireability-12
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-12
lola: result : false
lola: markings : 46800
lola: fired transitions : 159883
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 UtilityControlRoom-COL-Z4T4N02-CTLFireability-11
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-11
lola: result : false
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 UtilityControlRoom-COL-Z4T4N02-CTLFireability-07
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-07
lola: result : false
lola: markings : 57040
lola: fired transitions : 713433
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 UtilityControlRoom-COL-Z4T4N02-CTLFireability-06
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-06
lola: result : true
lola: markings : 37
lola: fired transitions : 43
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 23 UtilityControlRoom-COL-Z4T4N02-CTLFireability-05
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-05
lola: result : true
lola: markings : 57040
lola: fired transitions : 220330
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 20 UtilityControlRoom-COL-Z4T4N02-CTLFireability-04
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-04
lola: result : false
lola: markings : 57040
lola: fired transitions : 620326
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 17 UtilityControlRoom-COL-Z4T4N02-CTLFireability-03
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-03
lola: result : false
lola: markings : 39405
lola: fired transitions : 159956
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 15 (type EXCL) for 14 UtilityControlRoom-COL-Z4T4N02-CTLFireability-02
lola: time limit : 1199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-02
lola: result : false
lola: markings : 158
lola: fired transitions : 447
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 UtilityControlRoom-COL-Z4T4N02-CTLFireability-14
lola: time limit : 1799 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-14
lola: result : false
lola: markings : 14
lola: fired transitions : 40
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 UtilityControlRoom-COL-Z4T4N02-CTLFireability-09
lola: time limit : 3598 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for UtilityControlRoom-COL-Z4T4N02-CTLFireability-09
lola: result : false
lola: markings : 434
lola: fired transitions : 1062
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N02-CTLFireability-00: CONJ true CONJ
UtilityControlRoom-COL-Z4T4N02-CTLFireability-01: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-03: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-06: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-09: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-14: AFAG false CTL model checker
UtilityControlRoom-COL-Z4T4N02-CTLFireability-15: CTL false CTL model checker
Time elapsed: 2 secs. Pages in use: 1
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z4T4N02"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-COL-Z4T4N02, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703901050"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z4T4N02.tgz
mv UtilityControlRoom-COL-Z4T4N02 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;