Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703801002.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-COL-Z2T4N06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703801002
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 476K
-rw-r--r-- 1 mcc users 8.1K Feb 26 14:44 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 26 14:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.6K Feb 26 14:43 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K Feb 26 14:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 14:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 114K Feb 26 14:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Feb 26 14:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 26 14:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z2T4N06-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679228501740

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-COL-Z2T4N06
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 12:21:43] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 12:21:43] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 12:21:43] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-19 12:21:43] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-19 12:21:43] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 418 ms
[2023-03-19 12:21:43] [INFO ] Imported 13 HL places and 12 HL transitions for a total of 106 PT places and 162.0 transition bindings in 12 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
[2023-03-19 12:21:43] [INFO ] Built PT skeleton of HLPN with 13 places and 12 transitions 37 arcs in 4 ms.
[2023-03-19 12:21:43] [INFO ] Skeletonized 16 HLPN properties in 3 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 7 properties that can be checked using skeleton over-approximation.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 1146 steps, including 0 resets, run visited all 16 properties in 31 ms. (steps per millisecond=36 )
[2023-03-19 12:21:43] [INFO ] Flatten gal took : 14 ms
[2023-03-19 12:21:44] [INFO ] Flatten gal took : 3 ms
Transition timeout forces synchronizations/join behavior on parameter c of sort Cli
Domain [Cli(6), Z(2), Z(2)] of place MovetoZ breaks symmetries in sort Z
[2023-03-19 12:21:44] [INFO ] Unfolded HLPN to a Petri net with 106 places and 162 transitions 510 arcs in 11 ms.
[2023-03-19 12:21:44] [INFO ] Unfolded 16 HLPN properties in 1 ms.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 12:21:44] [INFO ] Reduced 6 identical enabling conditions.
Ensure Unique test removed 24 transitions
Reduce redundant transitions removed 24 transitions.
Support contains 106 out of 106 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 5 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
// Phase 1: matrix 138 rows 106 cols
[2023-03-19 12:21:44] [INFO ] Computed 15 place invariants in 14 ms
[2023-03-19 12:21:44] [INFO ] Implicit Places using invariants in 202 ms returned []
[2023-03-19 12:21:44] [INFO ] Invariant cache hit.
[2023-03-19 12:21:44] [INFO ] Implicit Places using invariants and state equation in 99 ms returned []
Implicit Place search using SMT with State Equation took 378 ms to find 0 implicit places.
[2023-03-19 12:21:44] [INFO ] Invariant cache hit.
[2023-03-19 12:21:44] [INFO ] Dead Transitions using invariants and state equation in 143 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 528 ms. Remains : 106/106 places, 138/138 transitions.
Support contains 106 out of 106 places after structural reductions.
[2023-03-19 12:21:44] [INFO ] Flatten gal took : 51 ms
[2023-03-19 12:21:44] [INFO ] Flatten gal took : 27 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 138 transitions.
Finished random walk after 434 steps, including 0 resets, run visited all 37 properties in 16 ms. (steps per millisecond=27 )
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 14 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 19 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 138 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 2 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 106/106 places, 138/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 7 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 9 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 4 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 6 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 6 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 7 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 4 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 6 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 6 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 1 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 106/106 places, 138/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 7 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 7 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 2 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 6 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 3 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 6 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 1 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 106/106 places, 138/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 6 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 3 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 1 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 106/106 places, 138/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 4 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 2 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 6 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 2 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 1 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 106/106 places, 138/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 4 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 2 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 4 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 4 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Performed 24 Post agglomeration using F-continuation condition.Transition count delta: 24
Iterating post reduction 0 with 24 rules applied. Total rules applied 24 place count 106 transition count 114
Reduce places removed 24 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 1 with 36 rules applied. Total rules applied 60 place count 82 transition count 102
Applied a total of 60 rules in 10 ms. Remains 82 /106 variables (removed 24) and now considering 102/138 (removed 36) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 82/106 places, 102/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 3 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 3 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 102 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Performed 12 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 12 Pre rules applied. Total rules applied 0 place count 106 transition count 126
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 0 with 24 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 6 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 5 ms
[2023-03-19 12:21:45] [INFO ] Input system was already deterministic with 126 transitions.
[2023-03-19 12:21:45] [INFO ] Flatten gal took : 17 ms
[2023-03-19 12:21:46] [INFO ] Flatten gal took : 16 ms
[2023-03-19 12:21:46] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 19 ms.
[2023-03-19 12:21:46] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 106 places, 138 transitions and 414 arcs took 1 ms.
Total runtime 2881 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-COL-Z2T4N06
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T4N06-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679228783849

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
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lola: Rule S: 0 transitions removed,0 places removed
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 19 (type EXCL) for 18 UtilityControlRoom-COL-Z2T4N06-CTLFireability-02
lola: time limit : 89 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:664
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 19 (type EXCL) for UtilityControlRoom-COL-Z2T4N06-CTLFireability-02
lola: result : true
lola: markings : 81695
lola: fired transitions : 268963
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 72 (type EXCL) for 63 UtilityControlRoom-COL-Z2T4N06-CTLFireability-13
lola: time limit : 156 sec
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lola: FINISHED task # 72 (type EXCL) for UtilityControlRoom-COL-Z2T4N06-CTLFireability-13
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 58 (type EXCL) for 53 UtilityControlRoom-COL-Z2T4N06-CTLFireability-11
lola: time limit : 171 sec
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lola: FINISHED task # 58 (type EXCL) for UtilityControlRoom-COL-Z2T4N06-CTLFireability-11
lola: result : false
lola: markings : 12079
lola: fired transitions : 21066
lola: time used : 0.000000
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lola: LAUNCH task # 51 (type EXCL) for 50 UtilityControlRoom-COL-Z2T4N06-CTLFireability-10
lola: time limit : 189 sec
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-11: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-01: DISJ 0 4 0 0 4 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-09: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-12: SP ECTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-13: DISJ 0 1 0 0 4 0 0 1
UtilityControlRoom-COL-Z2T4N06-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 5/189 4/32 UtilityControlRoom-COL-Z2T4N06-CTLFireability-10 921347 m, 184269 m/sec, 2902596 t fired, .

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-11: CONJ false CTL model checker

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-01: DISJ 0 4 0 0 4 0 0 0
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-09: EG 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-13: DISJ 0 1 0 0 4 0 0 1
UtilityControlRoom-COL-Z2T4N06-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 10/189 8/32 UtilityControlRoom-COL-Z2T4N06-CTLFireability-10 1712914 m, 158313 m/sec, 6049912 t fired, .

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-11: CONJ false CTL model checker

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-09: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-12: SP ECTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-13: DISJ 0 1 0 0 4 0 0 1
UtilityControlRoom-COL-Z2T4N06-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 15/189 11/32 UtilityControlRoom-COL-Z2T4N06-CTLFireability-10 2445387 m, 146494 m/sec, 9262243 t fired, .

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-11: CONJ false CTL model checker

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-09: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-12: SP ECTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-13: DISJ 0 1 0 0 4 0 0 1
UtilityControlRoom-COL-Z2T4N06-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 20/189 14/32 UtilityControlRoom-COL-Z2T4N06-CTLFireability-10 3135144 m, 137951 m/sec, 12476355 t fired, .

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-11: CONJ false CTL model checker

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-01: DISJ 0 4 0 0 4 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-COL-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-09: EG true state space / EG
UtilityControlRoom-COL-Z2T4N06-CTLFireability-11: CONJ false CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-12: SP ECTL true LTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-13: DISJ true state space / EG
UtilityControlRoom-COL-Z2T4N06-CTLFireability-14: EGEF true CTL model checker

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-COL-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-09: EG true state space / EG
UtilityControlRoom-COL-Z2T4N06-CTLFireability-11: CONJ false CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-12: SP ECTL true LTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-13: DISJ true state space / EG
UtilityControlRoom-COL-Z2T4N06-CTLFireability-14: EGEF true CTL model checker

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UtilityControlRoom-COL-Z2T4N06-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-09: EG true state space / EG
UtilityControlRoom-COL-Z2T4N06-CTLFireability-11: CONJ false CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-12: SP ECTL true LTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-13: DISJ true state space / EG
UtilityControlRoom-COL-Z2T4N06-CTLFireability-14: EGEF true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-09: EG true state space / EG
UtilityControlRoom-COL-Z2T4N06-CTLFireability-11: CONJ false CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-12: SP ECTL true LTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-13: DISJ true state space / EG
UtilityControlRoom-COL-Z2T4N06-CTLFireability-14: EGEF true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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UtilityControlRoom-COL-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T4N06-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T4N06-CTLFireability-00: CTL false CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-01: DISJ unknown DISJ
UtilityControlRoom-COL-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-COL-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-06: CTL unknown AGGR
UtilityControlRoom-COL-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-09: EG true state space / EG
UtilityControlRoom-COL-Z2T4N06-CTLFireability-10: CTL unknown AGGR
UtilityControlRoom-COL-Z2T4N06-CTLFireability-11: CONJ false CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-12: SP ECTL true LTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-13: DISJ true state space / EG
UtilityControlRoom-COL-Z2T4N06-CTLFireability-14: EGEF true CTL model checker
UtilityControlRoom-COL-Z2T4N06-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z2T4N06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-COL-Z2T4N06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703801002"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z2T4N06.tgz
mv UtilityControlRoom-COL-Z2T4N06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;