fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r487-tall-167912703800962
Last Updated
May 14, 2023

About the Execution of LoLa+red for UtilityControlRoom-COL-Z2T3N06

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3289.663 299092.00 297218.00 828.80 ?F?FTTFTFTTTF?FT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703800962.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-COL-Z2T3N06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703800962
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 500K
-rw-r--r-- 1 mcc users 7.3K Feb 26 14:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 26 14:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 26 14:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 26 14:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 26 14:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 143K Feb 26 14:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 14:52 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Feb 26 14:52 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z2T3N06-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679226809975

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-COL-Z2T3N06
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:53:31] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 11:53:31] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:53:31] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-19 11:53:31] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-19 11:53:32] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 609 ms
[2023-03-19 11:53:32] [INFO ] Imported 13 HL places and 12 HL transitions for a total of 106 PT places and 162.0 transition bindings in 12 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 13 ms.
[2023-03-19 11:53:32] [INFO ] Built PT skeleton of HLPN with 13 places and 12 transitions 37 arcs in 4 ms.
[2023-03-19 11:53:32] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 7 properties that can be checked using skeleton over-approximation.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 34 steps, including 0 resets, run visited all 12 properties in 11 ms. (steps per millisecond=3 )
[2023-03-19 11:53:32] [INFO ] Flatten gal took : 13 ms
[2023-03-19 11:53:32] [INFO ] Flatten gal took : 3 ms
Transition timeout forces synchronizations/join behavior on parameter c of sort Cli
Domain [Cli(6), Z(2), Z(2)] of place MovetoZ breaks symmetries in sort Z
[2023-03-19 11:53:32] [INFO ] Unfolded HLPN to a Petri net with 106 places and 162 transitions 510 arcs in 12 ms.
[2023-03-19 11:53:32] [INFO ] Unfolded 16 HLPN properties in 1 ms.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 11:53:32] [INFO ] Reduced 6 identical enabling conditions.
Ensure Unique test removed 24 transitions
Reduce redundant transitions removed 24 transitions.
Support contains 106 out of 106 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 6 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
// Phase 1: matrix 138 rows 106 cols
[2023-03-19 11:53:32] [INFO ] Computed 15 place invariants in 15 ms
[2023-03-19 11:53:32] [INFO ] Implicit Places using invariants in 156 ms returned []
[2023-03-19 11:53:32] [INFO ] Invariant cache hit.
[2023-03-19 11:53:32] [INFO ] Implicit Places using invariants and state equation in 99 ms returned []
Implicit Place search using SMT with State Equation took 276 ms to find 0 implicit places.
[2023-03-19 11:53:32] [INFO ] Invariant cache hit.
[2023-03-19 11:53:32] [INFO ] Dead Transitions using invariants and state equation in 96 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 382 ms. Remains : 106/106 places, 138/138 transitions.
Support contains 106 out of 106 places after structural reductions.
[2023-03-19 11:53:32] [INFO ] Flatten gal took : 22 ms
[2023-03-19 11:53:32] [INFO ] Flatten gal took : 31 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 138 transitions.
Finished random walk after 151 steps, including 0 resets, run visited all 33 properties in 12 ms. (steps per millisecond=12 )
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 17 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 20 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 138 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 2 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 106/106 places, 138/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 11 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 9 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 5 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 6 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 6 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Drop transitions removed 12 transitions
Redundant transition composition rules discarded 12 transitions
Iterating global reduction 0 with 12 rules applied. Total rules applied 36 place count 94 transition count 114
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 37 place count 93 transition count 102
Iterating global reduction 0 with 1 rules applied. Total rules applied 38 place count 93 transition count 102
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 44 place count 87 transition count 96
Iterating global reduction 0 with 6 rules applied. Total rules applied 50 place count 87 transition count 96
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 56 place count 81 transition count 84
Iterating global reduction 0 with 6 rules applied. Total rules applied 62 place count 81 transition count 84
Applied a total of 62 rules in 31 ms. Remains 81 /106 variables (removed 25) and now considering 84/138 (removed 54) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 81/106 places, 84/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 3 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 3 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 3 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 6 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 6 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 6 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 6 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 7 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Performed 24 Post agglomeration using F-continuation condition.Transition count delta: 24
Iterating post reduction 0 with 24 rules applied. Total rules applied 24 place count 106 transition count 114
Reduce places removed 24 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 1 with 36 rules applied. Total rules applied 60 place count 82 transition count 102
Applied a total of 60 rules in 12 ms. Remains 82 /106 variables (removed 24) and now considering 102/138 (removed 36) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 82/106 places, 102/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 4 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 13 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 102 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Performed 24 Post agglomeration using F-continuation condition.Transition count delta: 24
Iterating post reduction 0 with 24 rules applied. Total rules applied 24 place count 106 transition count 114
Reduce places removed 24 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 1 with 36 rules applied. Total rules applied 60 place count 82 transition count 102
Performed 12 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 12 Pre rules applied. Total rules applied 60 place count 82 transition count 90
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 2 with 24 rules applied. Total rules applied 84 place count 70 transition count 90
Applied a total of 84 rules in 21 ms. Remains 70 /106 variables (removed 36) and now considering 90/138 (removed 48) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 21 ms. Remains : 70/106 places, 90/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 4 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 10 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 90 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 2 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 5 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 6 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 3 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 106/106 places, 138/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 6 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 22 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 10 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 6 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 7 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 1 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 106/106 places, 138/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 5 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 5 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 2 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 6 ms
[2023-03-19 11:53:33] [INFO ] Flatten gal took : 19 ms
[2023-03-19 11:53:33] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Drop transitions removed 24 transitions
Trivial Post-agglo rules discarded 24 transitions
Performed 24 trivial Post agglomeration. Transition count delta: 24
Iterating post reduction 0 with 24 rules applied. Total rules applied 24 place count 106 transition count 114
Reduce places removed 24 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 1 with 36 rules applied. Total rules applied 60 place count 82 transition count 102
Performed 12 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 12 Pre rules applied. Total rules applied 60 place count 82 transition count 90
Deduced a syphon composed of 12 places in 1 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 2 with 24 rules applied. Total rules applied 84 place count 70 transition count 90
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 85 place count 69 transition count 78
Iterating global reduction 2 with 1 rules applied. Total rules applied 86 place count 69 transition count 78
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 92 place count 63 transition count 72
Iterating global reduction 2 with 6 rules applied. Total rules applied 98 place count 63 transition count 72
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 104 place count 57 transition count 60
Iterating global reduction 2 with 6 rules applied. Total rules applied 110 place count 57 transition count 60
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 116 place count 51 transition count 54
Iterating global reduction 2 with 6 rules applied. Total rules applied 122 place count 51 transition count 54
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 128 place count 51 transition count 48
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 6 Pre rules applied. Total rules applied 128 place count 51 transition count 42
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 3 with 12 rules applied. Total rules applied 140 place count 45 transition count 42
Applied a total of 140 rules in 33 ms. Remains 45 /106 variables (removed 61) and now considering 42/138 (removed 96) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 33 ms. Remains : 45/106 places, 42/138 transitions.
[2023-03-19 11:53:34] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:53:34] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:53:34] [INFO ] Input system was already deterministic with 42 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 11 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 11:53:34] [INFO ] Flatten gal took : 5 ms
[2023-03-19 11:53:34] [INFO ] Flatten gal took : 4 ms
[2023-03-19 11:53:34] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 2 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 11:53:34] [INFO ] Flatten gal took : 5 ms
[2023-03-19 11:53:34] [INFO ] Flatten gal took : 4 ms
[2023-03-19 11:53:34] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 1 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 94/106 places, 126/138 transitions.
[2023-03-19 11:53:34] [INFO ] Flatten gal took : 4 ms
[2023-03-19 11:53:34] [INFO ] Flatten gal took : 5 ms
[2023-03-19 11:53:34] [INFO ] Input system was already deterministic with 126 transitions.
[2023-03-19 11:53:34] [INFO ] Flatten gal took : 27 ms
[2023-03-19 11:53:34] [INFO ] Flatten gal took : 15 ms
[2023-03-19 11:53:34] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 16 ms.
[2023-03-19 11:53:34] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 106 places, 138 transitions and 414 arcs took 1 ms.
Total runtime 3033 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-COL-Z2T3N06
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N06-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679227109067

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 20 (type EXCL) for 19 UtilityControlRoom-COL-Z2T3N06-CTLFireability-05
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/211 3/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-05 683236 m, 136647 m/sec, 4710840 t fired, .

Time elapsed: 6 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/211 6/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-05 1314890 m, 126330 m/sec, 9389139 t fired, .

Time elapsed: 11 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/211 8/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-05 1899592 m, 116940 m/sec, 13967079 t fired, .

Time elapsed: 16 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 20/211 11/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-05 2520137 m, 124109 m/sec, 18634931 t fired, .

Time elapsed: 21 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/211 13/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-05 3095150 m, 115002 m/sec, 23148387 t fired, .

Time elapsed: 26 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 30/211 15/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-05 3663137 m, 113597 m/sec, 27669470 t fired, .

Time elapsed: 31 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 35/211 18/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-05 4203011 m, 107974 m/sec, 32180602 t fired, .

Time elapsed: 36 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 20 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-05
lola: result : true
lola: markings : 4672816
lola: fired transitions : 35934004
lola: time used : 39.000000
lola: memory pages used : 19
lola: LAUNCH task # 50 (type EXCL) for 49 UtilityControlRoom-COL-Z2T3N06-CTLFireability-15
lola: time limit : 222 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-15
lola: result : true
lola: markings : 142
lola: fired transitions : 156
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 UtilityControlRoom-COL-Z2T3N06-CTLFireability-14
lola: time limit : 237 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-14
lola: result : false
lola: markings : 6561
lola: fired transitions : 21857
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13
lola: time limit : 254 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 1/254 1/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 168370 m, 33674 m/sec, 715978 t fired, .

Time elapsed: 41 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 6/254 4/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 857562 m, 137838 m/sec, 4574014 t fired, .

Time elapsed: 46 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 11/254 7/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 1466865 m, 121860 m/sec, 8335541 t fired, .

Time elapsed: 51 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 16/254 9/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 2035559 m, 113738 m/sec, 12020983 t fired, .

Time elapsed: 56 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 21/254 11/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 2580930 m, 109074 m/sec, 15656659 t fired, .

Time elapsed: 61 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 26/254 13/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 3106884 m, 105190 m/sec, 19252155 t fired, .

Time elapsed: 66 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 31/254 16/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 3615931 m, 101809 m/sec, 22807150 t fired, .

Time elapsed: 71 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 36/254 18/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 4110584 m, 98930 m/sec, 26325177 t fired, .

Time elapsed: 76 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 41/254 20/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 4594839 m, 96851 m/sec, 29820747 t fired, .

Time elapsed: 81 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 46/254 21/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 5066670 m, 94366 m/sec, 33279250 t fired, .

Time elapsed: 86 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 51/254 23/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 5530824 m, 92830 m/sec, 36720222 t fired, .

Time elapsed: 91 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 56/254 25/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 5986758 m, 91186 m/sec, 40137844 t fired, .

Time elapsed: 96 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 61/254 27/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 6435173 m, 89683 m/sec, 43545366 t fired, .

Time elapsed: 101 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 66/254 29/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 6876024 m, 88170 m/sec, 46935967 t fired, .

Time elapsed: 106 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 71/254 31/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 7311803 m, 87155 m/sec, 50315741 t fired, .

Time elapsed: 111 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 76/254 32/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 7741668 m, 85973 m/sec, 53685056 t fired, .

Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 44 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 38 (type EXCL) for 37 UtilityControlRoom-COL-Z2T3N06-CTLFireability-11
lola: time limit : 267 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-11
lola: result : true
lola: markings : 83
lola: fired transitions : 400
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 UtilityControlRoom-COL-Z2T3N06-CTLFireability-10
lola: time limit : 289 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-10
lola: result : true
lola: markings : 6561
lola: fired transitions : 8748
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 UtilityControlRoom-COL-Z2T3N06-CTLFireability-09
lola: time limit : 316 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/316 6/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-09 1403632 m, 280726 m/sec, 5105412 t fired, .

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/316 11/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-09 2587674 m, 236808 m/sec, 9904618 t fired, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 32 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-09
lola: result : true
lola: markings : 2956777
lola: fired transitions : 11306872
lola: time used : 11.000000
lola: memory pages used : 12
lola: LAUNCH task # 26 (type EXCL) for 25 UtilityControlRoom-COL-Z2T3N06-CTLFireability-07
lola: time limit : 346 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-07
lola: result : true
lola: markings : 86
lola: fired transitions : 385
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 8 (type EXCL) for 3 UtilityControlRoom-COL-Z2T3N06-CTLFireability-01
lola: time limit : 385 sec
lola: memory limit: 32 pages
lola: FINISHED task # 8 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-01
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-COL-Z2T3N06-CTLFireability-00
lola: time limit : 433 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 4/433 4/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-00 849222 m, 169844 m/sec, 3525657 t fired, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 9/433 8/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-00 1831434 m, 196442 m/sec, 8343316 t fired, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 14/433 12/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-00 2698223 m, 173357 m/sec, 13024142 t fired, .

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 19/433 15/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-00 3614541 m, 183263 m/sec, 17692103 t fired, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 24/433 19/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-00 4405115 m, 158114 m/sec, 22386183 t fired, .

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 29/433 21/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-00 5088132 m, 136603 m/sec, 26940111 t fired, .

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 34/433 25/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-00 6011653 m, 184704 m/sec, 31618209 t fired, .

Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 39/433 28/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-00 6876459 m, 172961 m/sec, 36255991 t fired, .

Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 44/433 32/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-00 7668902 m, 158488 m/sec, 40884296 t fired, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 52 (type EXCL) for 13 UtilityControlRoom-COL-Z2T3N06-CTLFireability-03
lola: time limit : 488 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 5/488 5/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-03 1212110 m, 242422 m/sec, 4433288 t fired, .

Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 10/488 8/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-03 2018631 m, 161304 m/sec, 8784401 t fired, .

Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 15/488 10/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-03 2645415 m, 125356 m/sec, 13287950 t fired, .

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 20/488 11/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-03 2859290 m, 42775 m/sec, 17988618 t fired, .

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 25/488 11/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-03 2859582 m, 58 m/sec, 22532456 t fired, .

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 52 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-03
lola: result : true
lola: markings : 2859591
lola: fired transitions : 25073254
lola: time used : 28.000000
lola: memory pages used : 11
lola: LAUNCH task # 6 (type EXCL) for 3 UtilityControlRoom-COL-Z2T3N06-CTLFireability-01
lola: time limit : 565 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 0 1 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 EFEG EXCL 2/565 2/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-01 511146 m, 102229 m/sec, 1790585 t fired, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 0 1 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 EFEG EXCL 7/565 5/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-01 1098672 m, 117505 m/sec, 5132551 t fired, .

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ 0 0 1 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 EFEG EXCL 12/565 7/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-01 1686201 m, 117505 m/sec, 8735749 t fired, .

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 6 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-01
lola: result : false
lola: markings : 1830337
lola: fired transitions : 10127791
lola: time used : 14.000000
lola: memory pages used : 7
lola: LAUNCH task # 41 (type EXCL) for 40 UtilityControlRoom-COL-Z2T3N06-CTLFireability-12
lola: time limit : 675 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-12
lola: result : false
lola: markings : 12
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 UtilityControlRoom-COL-Z2T3N06-CTLFireability-06
lola: time limit : 844 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-06
lola: result : false
lola: markings : 33
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02
lola: time limit : 1125 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 3/1125 4/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 718353 m, 143670 m/sec, 2520424 t fired, .

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 8/1125 7/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 1630238 m, 182377 m/sec, 6301882 t fired, .

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 13/1125 11/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 2422525 m, 158457 m/sec, 9961463 t fired, .

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 18/1125 14/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 3136929 m, 142880 m/sec, 13537032 t fired, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 23/1125 16/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 3801683 m, 132950 m/sec, 17058518 t fired, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 28/1125 19/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 4428367 m, 125336 m/sec, 20552476 t fired, .

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 33/1125 21/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 5024357 m, 119198 m/sec, 24015813 t fired, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 38/1125 24/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 5595135 m, 114155 m/sec, 27451851 t fired, .

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 43/1125 26/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 6143880 m, 109749 m/sec, 30858836 t fired, .

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 48/1125 28/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 6670196 m, 105263 m/sec, 34247256 t fired, .

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 53/1125 30/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 7177622 m, 101485 m/sec, 37615875 t fired, .

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 58/1125 32/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 7671281 m, 98731 m/sec, 40966295 t fired, .

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 11 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 17 (type EXCL) for 16 UtilityControlRoom-COL-Z2T3N06-CTLFireability-04
lola: time limit : 1657 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/1657 5/32 UtilityControlRoom-COL-Z2T3N06-CTLFireability-04 1071119 m, 214223 m/sec, 4405869 t fired, .

Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 17 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-04
lola: result : true
lola: markings : 1497325
lola: fired transitions : 6289543
lola: time used : 7.000000
lola: memory pages used : 7
lola: LAUNCH task # 29 (type EXCL) for 28 UtilityControlRoom-COL-Z2T3N06-CTLFireability-08
lola: time limit : 3307 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for UtilityControlRoom-COL-Z2T3N06-CTLFireability-08
lola: result : false
lola: markings : 81215
lola: fired transitions : 268073
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z2T3N06-CTLFireability-00: CTL unknown AGGR
UtilityControlRoom-COL-Z2T3N06-CTLFireability-01: DISJ false DISJ
UtilityControlRoom-COL-Z2T3N06-CTLFireability-02: CTL unknown AGGR
UtilityControlRoom-COL-Z2T3N06-CTLFireability-03: EFAG false tscc_search
UtilityControlRoom-COL-Z2T3N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-13: CTL unknown AGGR
UtilityControlRoom-COL-Z2T3N06-CTLFireability-14: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N06-CTLFireability-15: CTL true CTL model checker


Time elapsed: 293 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z2T3N06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-COL-Z2T3N06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703800962"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z2T3N06.tgz
mv UtilityControlRoom-COL-Z2T3N06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;