Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703700938.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC10000vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703700938
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 524K
-rw-r--r-- 1 mcc users 7.3K Feb 25 17:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 25 17:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 25 17:26 CTLFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 25 17:26 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 25 17:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 169K Feb 25 17:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.4K Feb 25 17:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 79K Feb 25 17:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679225870085

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC10000vN
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:37:51] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 11:37:51] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:37:51] [INFO ] Load time of PNML (sax parser for PT used): 17 ms
[2023-03-19 11:37:51] [INFO ] Transformed 8 places.
[2023-03-19 11:37:51] [INFO ] Transformed 6 transitions.
[2023-03-19 11:37:51] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 72 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
Initial state reduction rules removed 1 formulas.
FORMULA TwoPhaseLocking-PT-nC10000vN-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 8 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:37:51] [INFO ] Computed 3 place invariants in 6 ms
[2023-03-19 11:37:51] [INFO ] Implicit Places using invariants in 124 ms returned []
[2023-03-19 11:37:51] [INFO ] Invariant cache hit.
[2023-03-19 11:37:51] [INFO ] Implicit Places using invariants and state equation in 33 ms returned []
Implicit Place search using SMT with State Equation took 179 ms to find 0 implicit places.
[2023-03-19 11:37:51] [INFO ] Invariant cache hit.
[2023-03-19 11:37:51] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 213 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 15 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 3 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10003 steps, including 1 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 34) seen :11
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 23) seen :21
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-19 11:37:52] [INFO ] Invariant cache hit.
[2023-03-19 11:37:52] [INFO ] [Real]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 11:37:52] [INFO ] After 44ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-19 11:37:52] [INFO ] [Nat]Absence check using 3 positive place invariants in 3 ms returned sat
[2023-03-19 11:37:52] [INFO ] After 10ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-19 11:37:52] [INFO ] After 24ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 8 ms.
[2023-03-19 11:37:52] [INFO ] After 66ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Finished Parikh walk after 5 steps, including 0 resets, run visited all 2 properties in 1 ms. (steps per millisecond=5 )
Parikh walk visited 2 properties in 2 ms.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 3 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 2 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:37:52] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:37:52] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 11:37:52] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 0 ms.
Total runtime 1065 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC10000vN
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

FORMULA TwoPhaseLocking-PT-nC10000vN-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679226048882

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC10000vN-CTLFireability-00
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: LAUNCH task # 61 (type FNDP) for 39 TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
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lola: FINISHED task # 64 (type SRCH) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
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lola: tried executions : 1
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: planning for (null) stopped (result already fixed).
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: try reading problem file /home/mcc/execution/376/CTLFireability-62.sara.

lola: FINISHED task # 62 (type EQUN) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
lola: result : true
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TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
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TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ 0 1 0 0 11 0 0 1
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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1 CTL EXCL 5/240 32/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-00 7113600 m, 1422720 m/sec, 7126928 t fired, .

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TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ 0 1 0 0 11 0 0 1
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TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ 0 1 0 0 11 0 0 1
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

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59 CTL EXCL 5/256 31/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-15 6821056 m, 1364211 m/sec, 9079745 t fired, .

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TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ 0 1 0 0 11 0 0 1
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TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ 0 0 1 0 11 0 0 1
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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42 CTL EXCL 5/275 10/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-14 2283519 m, 456703 m/sec, 7230321 t fired, .

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TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ 0 0 1 0 11 0 0 1
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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42 CTL EXCL 10/275 18/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-14 4355415 m, 414379 m/sec, 13904358 t fired, .

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TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ 0 0 1 0 11 0 0 1
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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42 CTL EXCL 15/275 27/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-14 6358857 m, 400688 m/sec, 20358131 t fired, .

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TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ 0 0 0 0 11 0 1 1
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/1722 26/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-11 6457487 m, 594301 m/sec, 15570849 t fired, .

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TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ 0 0 0 0 11 0 1 1
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ 0 0 0 0 11 0 1 1
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: CONJ unknown CONJ
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC10000vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC10000vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703700938"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC10000vN.tgz
mv TwoPhaseLocking-PT-nC10000vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;