Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703700922.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC05000vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703700922
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 464K
-rw-r--r-- 1 mcc users 8.1K Feb 25 17:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 25 17:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 17:52 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 25 17:52 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 17:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 109K Feb 25 17:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 93K Feb 25 17:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679225401911

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC05000vN
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:30:03] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 11:30:03] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:30:03] [INFO ] Load time of PNML (sax parser for PT used): 16 ms
[2023-03-19 11:30:03] [INFO ] Transformed 8 places.
[2023-03-19 11:30:03] [INFO ] Transformed 6 transitions.
[2023-03-19 11:30:03] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 70 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 8 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:30:03] [INFO ] Computed 3 place invariants in 5 ms
[2023-03-19 11:30:03] [INFO ] Implicit Places using invariants in 127 ms returned []
[2023-03-19 11:30:03] [INFO ] Invariant cache hit.
[2023-03-19 11:30:03] [INFO ] Implicit Places using invariants and state equation in 29 ms returned []
Implicit Place search using SMT with State Equation took 179 ms to find 0 implicit places.
[2023-03-19 11:30:03] [INFO ] Invariant cache hit.
[2023-03-19 11:30:03] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 214 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:30:03] [INFO ] Flatten gal took : 11 ms
[2023-03-19 11:30:03] [INFO ] Flatten gal took : 3 ms
[2023-03-19 11:30:03] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10006 steps, including 2 resets, run finished after 137 ms. (steps per millisecond=73 ) properties (out of 19) seen :6
Finished Best-First random walk after 73 steps, including 0 resets, run visited all 13 properties in 4 ms. (steps per millisecond=18 )
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 7 transition count 4
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 5 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 8 transition count 5
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 2 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 4 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:30:04] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 11:30:04] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 0 ms.
Total runtime 957 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC05000vN
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/377
CTLFireability

FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679225555539

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/377/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/377/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/377/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 31 (type EXCL) for 30 TwoPhaseLocking-PT-nC05000vN-CTLFireability-10
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 49 (type FNDP) for 3 TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
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lola: LAUNCH task # 50 (type EQUN) for 3 TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
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lola: LAUNCH task # 52 (type SRCH) for 3 TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
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lola: rewrite Frontend/Parser/formula_rewrite.k:815
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
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lola: FINISHED task # 52 (type SRCH) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
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lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 49 (type FNDP) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
lola: result : true
lola: fired transitions : 2499
lola: tried executions : 1
lola: time used : 0.000000
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lola: CANCELED task # 50 (type EQUN) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-01 (obsolete)
lola: FINISHED task # 50 (type EQUN) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/240 24/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-10 5777697 m, 1155539 m/sec, 7698692 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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lola: result : false
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/276 7/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-14 1640915 m, 328183 m/sec, 6598860 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/276 13/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-14 3056912 m, 283199 m/sec, 12528359 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/276 18/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-14 4411167 m, 270851 m/sec, 18229332 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/276 24/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-14 5724258 m, 262618 m/sec, 23787451 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/276 29/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-14 7014402 m, 258028 m/sec, 29254849 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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lola: time limit : 296 sec
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lola: FINISHED task # 40 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-13
lola: result : true
lola: markings : 12503
lola: fired transitions : 15003
lola: time used : 0.000000
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lola: LAUNCH task # 37 (type EXCL) for 36 TwoPhaseLocking-PT-nC05000vN-CTLFireability-12
lola: time limit : 323 sec
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lola: FINISHED task # 37 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-12
lola: result : false
lola: markings : 2504
lola: fired transitions : 2510
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lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC05000vN-CTLFireability-07
lola: time limit : 356 sec
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/356 17/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-07 4114443 m, 822888 m/sec, 8163624 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/394 27/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-05 6357992 m, 1271598 m/sec, 8472108 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC05000vN-CTLFireability-04
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lola: FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-04
lola: result : true
lola: markings : 12503
lola: fired transitions : 15003
lola: time used : 0.000000
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lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC05000vN-CTLFireability-03
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/505 17/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-03 3699061 m, 739812 m/sec, 9246403 t fired, .

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lola: result : true
lola: markings : 6255001
lola: fired transitions : 15636252
lola: time used : 8.000000
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lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC05000vN-CTLFireability-02
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 2/588 3/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-02 504493 m, 100898 m/sec, 3379015 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 7/588 8/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-02 1751759 m, 249453 m/sec, 12746683 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 12/588 12/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-02 2899058 m, 229459 m/sec, 21533236 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 17/588 17/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-02 4004403 m, 221069 m/sec, 30080716 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 22/588 21/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-02 5080693 m, 215258 m/sec, 38442722 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 27/588 25/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-02 6115781 m, 207017 m/sec, 46524020 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 32/588 29/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-02 7119739 m, 200791 m/sec, 54368708 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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lola: result : true
lola: markings : 55030
lola: fired transitions : 90040
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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28 CTL EXCL 5/1165 8/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-09 1992951 m, 398590 m/sec, 7796404 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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28 CTL EXCL 10/1165 16/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-09 3878760 m, 377161 m/sec, 15187080 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/1165 23/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-09 5712326 m, 366713 m/sec, 22371774 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/1165 30/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-09 7443020 m, 346138 m/sec, 29289155 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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19 CTL EXCL 5/1735 20/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-06 4903978 m, 980795 m/sec, 9719990 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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34 CTL EXCL 5/3460 29/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-11 6532964 m, 1306592 m/sec, 6542690 t fired, .

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC05000vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC05000vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703700922"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC05000vN.tgz
mv TwoPhaseLocking-PT-nC05000vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;