Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703700890.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC01000vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703700890
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 396K
-rw-r--r-- 1 mcc users 6.8K Feb 25 17:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K Feb 25 17:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 17:40 CTLFireability.txt
-rw-r--r-- 1 mcc users 37K Feb 25 17:40 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:23 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:23 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.8K Feb 25 17:42 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 79K Feb 25 17:42 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K Feb 25 17:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 25 17:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:23 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679224770191

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC01000vN
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:19:31] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 11:19:31] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:19:31] [INFO ] Load time of PNML (sax parser for PT used): 15 ms
[2023-03-19 11:19:31] [INFO ] Transformed 8 places.
[2023-03-19 11:19:31] [INFO ] Transformed 6 transitions.
[2023-03-19 11:19:31] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 68 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 7 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:19:31] [INFO ] Computed 3 place invariants in 5 ms
[2023-03-19 11:19:31] [INFO ] Implicit Places using invariants in 317 ms returned []
[2023-03-19 11:19:32] [INFO ] Invariant cache hit.
[2023-03-19 11:19:32] [INFO ] Implicit Places using invariants and state equation in 44 ms returned []
Implicit Place search using SMT with State Equation took 383 ms to find 0 implicit places.
[2023-03-19 11:19:32] [INFO ] Invariant cache hit.
[2023-03-19 11:19:32] [INFO ] Dead Transitions using invariants and state equation in 34 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 427 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 11 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 2013 steps, including 0 resets, run visited all 15 properties in 14 ms. (steps per millisecond=143 )
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 8 transition count 5
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 3 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 2 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 1 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 0 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:19:32] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:19:32] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 11:19:32] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 0 ms.
Total runtime 881 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC01000vN
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679224938580

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 56 (type EXCL) for 10 TwoPhaseLocking-PT-nC01000vN-CTLFireability-02
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 59 (type FNDP) for 3 TwoPhaseLocking-PT-nC01000vN-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type EQUN) for 3 TwoPhaseLocking-PT-nC01000vN-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type SRCH) for 3 TwoPhaseLocking-PT-nC01000vN-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 62 (type SRCH) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 59 (type FNDP) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-01
lola: result : true
lola: fired transitions : 499
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 60 (type EQUN) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-01 (obsolete)
sara: try reading problem file /home/mcc/execution/373/CTLFireability-60.sara.

lola: FINISHED task # 60 (type EQUN) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-01
lola: result : true
lola: FINISHED task # 56 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-02
lola: result : false
lola: markings : 377251
lola: fired transitions : 627249
lola: time used : 0.000000
lola: memory pages used : 2
lola: LAUNCH task # 54 (type EXCL) for 53 TwoPhaseLocking-PT-nC01000vN-CTLFireability-15
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-15
lola: result : true
lola: markings : 916587
lola: fired transitions : 5835969
lola: time used : 4.000000
lola: memory pages used : 4
lola: LAUNCH task # 48 (type EXCL) for 47 TwoPhaseLocking-PT-nC01000vN-CTLFireability-13
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-13
lola: result : false
lola: markings : 501
lola: fired transitions : 1002
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11
lola: time limit : 276 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 1/276 2/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 439162 m, 87832 m/sec, 1061708 t fired, .

Time elapsed: 5 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 6/276 7/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 1592388 m, 230645 m/sec, 8654155 t fired, .

Time elapsed: 10 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 11/276 10/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 2409803 m, 163483 m/sec, 15159384 t fired, .

Time elapsed: 15 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 16/276 13/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 3195242 m, 157087 m/sec, 21451014 t fired, .

Time elapsed: 20 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 21/276 17/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 3982869 m, 157525 m/sec, 27734199 t fired, .

Time elapsed: 25 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 26/276 20/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 4770719 m, 157570 m/sec, 34008053 t fired, .

Time elapsed: 30 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 31/276 23/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 5535314 m, 152919 m/sec, 40157489 t fired, .

Time elapsed: 35 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 36/276 26/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 6329396 m, 158816 m/sec, 46396830 t fired, .

Time elapsed: 40 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 41/276 29/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 7085232 m, 151167 m/sec, 52417140 t fired, .

Time elapsed: 45 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 46/276 32/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 7835311 m, 150015 m/sec, 58395069 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 42 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 39 (type EXCL) for 38 TwoPhaseLocking-PT-nC01000vN-CTLFireability-10
lola: time limit : 295 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-10
lola: result : false
lola: markings : 751989
lola: fired transitions : 1376252
lola: time used : 1.000000
lola: memory pages used : 4
lola: LAUNCH task # 23 (type EXCL) for 22 TwoPhaseLocking-PT-nC01000vN-CTLFireability-06
lola: time limit : 322 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-06
lola: result : false
lola: markings : 626749
lola: fired transitions : 1253002
lola: time used : 0.000000
lola: memory pages used : 3
lola: LAUNCH task # 20 (type EXCL) for 19 TwoPhaseLocking-PT-nC01000vN-CTLFireability-05
lola: time limit : 354 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-05
lola: result : true
lola: markings : 3000
lola: fired transitions : 3510
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 TwoPhaseLocking-PT-nC01000vN-CTLFireability-03
lola: time limit : 393 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 4/393 14/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-03 3381363 m, 676272 m/sec, 5852205 t fired, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 9/393 31/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-03 7381660 m, 800059 m/sec, 13025404 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 14 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC01000vN-CTLFireability-00
lola: time limit : 441 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/441 6/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-00 1416439 m, 283287 m/sec, 6696544 t fired, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/441 11/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-00 2579351 m, 232582 m/sec, 12677918 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/441 15/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-00 3701370 m, 224403 m/sec, 18460729 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/441 20/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-00 4785362 m, 216798 m/sec, 24158399 t fired, .

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/441 24/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-00 5856926 m, 214312 m/sec, 29778742 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/441 28/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-00 6940659 m, 216746 m/sec, 35498116 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 57 (type EXCL) for 25 TwoPhaseLocking-PT-nC01000vN-CTLFireability-07
lola: time limit : 499 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 AGEF EXCL 5/499 16/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-07 4320219 m, 864043 m/sec, 10627973 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 AGEF EXCL 10/499 29/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-07 7808586 m, 697673 m/sec, 19396502 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 57 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 51 (type EXCL) for 50 TwoPhaseLocking-PT-nC01000vN-CTLFireability-14
lola: time limit : 580 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-14
lola: result : false
lola: markings : 501
lola: fired transitions : 500
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 TwoPhaseLocking-PT-nC01000vN-CTLFireability-09
lola: time limit : 696 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-09
lola: result : false
lola: markings : 4495
lola: fired transitions : 8501
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 28 TwoPhaseLocking-PT-nC01000vN-CTLFireability-08
lola: time limit : 870 sec
lola: memory limit: 32 pages
lola: CANCELED task # 33 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 28 TwoPhaseLocking-PT-nC01000vN-CTLFireability-08
lola: time limit : 1158 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 0 1 0 2 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/1158 23/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-08 5445681 m, 1089136 m/sec, 5504353 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 0 0 0 2 0 2 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 17 (type EXCL) for 16 TwoPhaseLocking-PT-nC01000vN-CTLFireability-04
lola: time limit : 1732 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 0 0 0 2 0 2 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/1732 12/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-04 2674092 m, 534818 m/sec, 8353562 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 0 0 0 2 0 2 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/1732 20/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-04 4679561 m, 401093 m/sec, 15375255 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 0 0 0 2 0 2 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/1732 28/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-04 6684308 m, 400949 m/sec, 22396248 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 17 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 0 0 0 2 0 2 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 45 (type EXCL) for 44 TwoPhaseLocking-PT-nC01000vN-CTLFireability-12
lola: time limit : 3445 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 0 0 0 2 0 2 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 5/3445 19/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-12 4491575 m, 898315 m/sec, 7845573 t fired, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 45 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ 0 0 0 0 2 0 2 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CONJ false findpath
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: F true state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: EFAG unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: DISJ unknown DISJ
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL true CTL model checker


Time elapsed: 165 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC01000vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC01000vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703700890"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC01000vN.tgz
mv TwoPhaseLocking-PT-nC01000vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;