Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703700882.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC01000vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703700882
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 420K
-rw-r--r-- 1 mcc users 7.6K Feb 25 17:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 17:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Feb 25 17:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K Feb 25 17:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:23 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:23 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 131K Feb 25 17:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 25 17:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 25 17:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:23 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679224703078

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC01000vD
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:18:24] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 11:18:24] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:18:24] [INFO ] Load time of PNML (sax parser for PT used): 17 ms
[2023-03-19 11:18:24] [INFO ] Transformed 8 places.
[2023-03-19 11:18:24] [INFO ] Transformed 6 transitions.
[2023-03-19 11:18:24] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 71 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 7 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:18:24] [INFO ] Computed 3 place invariants in 7 ms
[2023-03-19 11:18:24] [INFO ] Implicit Places using invariants in 122 ms returned []
[2023-03-19 11:18:24] [INFO ] Invariant cache hit.
[2023-03-19 11:18:24] [INFO ] Implicit Places using invariants and state equation in 29 ms returned []
Implicit Place search using SMT with State Equation took 175 ms to find 0 implicit places.
[2023-03-19 11:18:24] [INFO ] Invariant cache hit.
[2023-03-19 11:18:24] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 215 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 12 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 3 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10023 steps, including 3 resets, run finished after 22 ms. (steps per millisecond=455 ) properties (out of 22) seen :17
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 120 ms. (steps per millisecond=83 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 4) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-19 11:18:25] [INFO ] Invariant cache hit.
[2023-03-19 11:18:25] [INFO ] After 21ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 2 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 3 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:18:25] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 11:18:25] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 1 ms.
Total runtime 1224 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC01000vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679224812159

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 23 (type EXCL) for 22 TwoPhaseLocking-PT-nC01000vD-CTLFireability-06
lola: time limit : 116 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/171 14/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-06 3393721 m, 678744 m/sec, 7147293 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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23 CTL EXCL 10/171 27/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-06 6486020 m, 618459 m/sec, 13914307 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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53 CTL EXCL 5/224 8/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-12 1722927 m, 344585 m/sec, 6527745 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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53 CTL EXCL 10/224 14/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-12 3355981 m, 326610 m/sec, 12785671 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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53 CTL EXCL 15/224 21/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-12 5003226 m, 329449 m/sec, 19102182 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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53 CTL EXCL 20/224 28/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-12 6624068 m, 324168 m/sec, 25314032 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ 0 2 0 0 6 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/444 20/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 4698575 m, 939715 m/sec, 9311847 t fired, .

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lola: CANCELED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ 0 2 0 0 6 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC01000vD-CTLFireability-02
lola: time limit : 507 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-02
lola: result : false
lola: markings : 377245
lola: fired transitions : 378740
lola: time used : 0.000000
lola: memory pages used : 2
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC01000vD-CTLFireability-01
lola: time limit : 591 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ 0 2 0 0 6 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/591 8/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-01 1727565 m, 345513 m/sec, 6519907 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ 0 2 0 0 6 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/591 14/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-01 3395161 m, 333519 m/sec, 12902907 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ 0 2 0 0 6 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/591 21/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-01 4963306 m, 313629 m/sec, 18908561 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ 0 2 0 0 6 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/591 27/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-01 6554887 m, 318316 m/sec, 24999327 t fired, .

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lola: CANCELED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ 0 2 0 0 6 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC01000vD-CTLFireability-00
lola: time limit : 704 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-00
lola: result : true
lola: markings : 4997
lola: fired transitions : 10999
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 71 (type EXCL) for 28 TwoPhaseLocking-PT-nC01000vD-CTLFireability-08
lola: time limit : 881 sec
lola: memory limit: 32 pages
lola: FINISHED task # 71 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-08
lola: result : false
lola: markings : 2001
lola: fired transitions : 2001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 58 TwoPhaseLocking-PT-nC01000vD-CTLFireability-14
lola: time limit : 1174 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-14
lola: result : false
lola: markings : 3505
lola: fired transitions : 9023
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 28 TwoPhaseLocking-PT-nC01000vD-CTLFireability-08
lola: time limit : 1762 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-08
lola: result : true
lola: markings : 1501
lola: fired transitions : 5505
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 TwoPhaseLocking-PT-nC01000vD-CTLFireability-10
lola: time limit : 3524 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ true CONJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 5/3524 8/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-10 1875433 m, 375086 m/sec, 7901109 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ true CONJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 10/3524 15/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-10 3519534 m, 328820 m/sec, 14947600 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ true CONJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 15/3524 21/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-10 5057551 m, 307603 m/sec, 21569363 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ true CONJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 20/3524 26/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-10 6468218 m, 282133 m/sec, 27654134 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ true CONJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 25/3524 32/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-10 7864405 m, 279237 m/sec, 33691836 t fired, .

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lola: CANCELED task # 47 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ true CONJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CONJ true CONJ
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: AXAF false state space /EXEG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: DISJ true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC01000vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC01000vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703700882"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC01000vD.tgz
mv TwoPhaseLocking-PT-nC01000vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;