Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703600866.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC00500vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703600866
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 544K
-rw-r--r-- 1 mcc users 7.7K Feb 25 17:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 25 17:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 17:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 17:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:23 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:23 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 25 17:43 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 173K Feb 25 17:43 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 17:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 103K Feb 25 17:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:23 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679224449034

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC00500vD
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:14:10] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 11:14:10] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:14:10] [INFO ] Load time of PNML (sax parser for PT used): 16 ms
[2023-03-19 11:14:10] [INFO ] Transformed 8 places.
[2023-03-19 11:14:10] [INFO ] Transformed 6 transitions.
[2023-03-19 11:14:10] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 72 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 7 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:14:10] [INFO ] Computed 3 place invariants in 5 ms
[2023-03-19 11:14:10] [INFO ] Implicit Places using invariants in 121 ms returned []
[2023-03-19 11:14:10] [INFO ] Invariant cache hit.
[2023-03-19 11:14:10] [INFO ] Implicit Places using invariants and state equation in 30 ms returned []
Implicit Place search using SMT with State Equation took 176 ms to find 0 implicit places.
[2023-03-19 11:14:10] [INFO ] Invariant cache hit.
[2023-03-19 11:14:10] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 211 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 13 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 4 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10046 steps, including 6 resets, run finished after 28 ms. (steps per millisecond=358 ) properties (out of 26) seen :22
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 4) seen :2
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-19 11:14:11] [INFO ] Invariant cache hit.
[2023-03-19 11:14:11] [INFO ] After 26ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 7 transition count 4
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 5 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 3 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 1 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:11] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 11:14:11] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 0 ms.
Total runtime 1129 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC00500vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679224617951

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC00500vD-CTLFireability-01
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/200 7/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-01 1693970 m, 338794 m/sec, 6279928 t fired, .

Time elapsed: 5 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/200 14/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-01 3279963 m, 317198 m/sec, 12218942 t fired, .

Time elapsed: 10 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/200 20/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-01 4827902 m, 309587 m/sec, 18004405 t fired, .

Time elapsed: 15 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/200 27/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-01 6354610 m, 305341 m/sec, 23721881 t fired, .

Time elapsed: 20 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 54 (type EXCL) for 53 TwoPhaseLocking-PT-nC00500vD-CTLFireability-15
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-15
lola: result : true
lola: markings : 2016
lola: fired transitions : 3552
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 42 TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
lola: time limit : 223 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
lola: result : true
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 42 TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
lola: time limit : 238 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
lola: result : true
lola: markings : 256
lola: fired transitions : 255
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 42 TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
lola: result : true
lola: markings : 1006
lola: fired transitions : 2009
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13
lola: time limit : 275 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/275 8/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 1756723 m, 351344 m/sec, 6678130 t fired, .

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/275 14/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 3414699 m, 331595 m/sec, 13054657 t fired, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/275 21/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 5050560 m, 327172 m/sec, 19361950 t fired, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/275 28/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 6705137 m, 330915 m/sec, 25740185 t fired, .

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 40 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 30 TwoPhaseLocking-PT-nC00500vD-CTLFireability-10
lola: time limit : 295 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/295 8/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-10 1785415 m, 357083 m/sec, 6788147 t fired, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/295 15/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-10 3430111 m, 328939 m/sec, 13114164 t fired, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/295 21/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-10 5031657 m, 320309 m/sec, 19289231 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/295 28/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-10 6656802 m, 325029 m/sec, 25553827 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 27 TwoPhaseLocking-PT-nC00500vD-CTLFireability-09
lola: time limit : 320 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/320 16/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-09 3771048 m, 754209 m/sec, 8732292 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/320 29/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-09 6980983 m, 641987 m/sec, 16386976 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 TwoPhaseLocking-PT-nC00500vD-CTLFireability-08
lola: time limit : 351 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/351 20/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-08 4818999 m, 963799 m/sec, 7291530 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC00500vD-CTLFireability-07
lola: time limit : 388 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-07
lola: result : true
lola: markings : 1755
lola: fired transitions : 3507
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC00500vD-CTLFireability-06
lola: time limit : 437 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-06
lola: result : true
lola: markings : 95125
lola: fired transitions : 127999
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC00500vD-CTLFireability-04
lola: time limit : 500 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-04
lola: result : false
lola: markings : 1501
lola: fired transitions : 4501
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02
lola: time limit : 583 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/583 6/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 1294724 m, 258944 m/sec, 4199755 t fired, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/583 11/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 2490318 m, 239118 m/sec, 8105235 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/583 15/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 3643287 m, 230593 m/sec, 11893162 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/583 20/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 4770545 m, 225451 m/sec, 15599407 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/583 24/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 5878076 m, 221506 m/sec, 19249450 t fired, .

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/583 29/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 6977247 m, 219834 m/sec, 22881311 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC00500vD-CTLFireability-00
lola: time limit : 693 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-00
lola: result : true
lola: markings : 502
lola: fired transitions : 1003
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 33 TwoPhaseLocking-PT-nC00500vD-CTLFireability-11
lola: time limit : 866 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 AGEF EXCL 5/866 15/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-11 4044626 m, 808925 m/sec, 8743535 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 AGEF EXCL 10/866 26/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-11 7096238 m, 610322 m/sec, 15959347 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 57 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 56 (type EXCL) for 36 TwoPhaseLocking-PT-nC00500vD-CTLFireability-12
lola: time limit : 1150 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-12
lola: result : true
lola: markings : 751
lola: fired transitions : 750
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 58 (type EXCL) for 9 TwoPhaseLocking-PT-nC00500vD-CTLFireability-03
lola: time limit : 1725 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-03
lola: result : false
lola: markings : 501
lola: fired transitions : 500
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC00500vD-CTLFireability-05
lola: time limit : 3450 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F true state space / EG
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF false state space /EFEG
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/3450 17/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-05 3956786 m, 791357 m/sec, 8275435 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F true state space / EG
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF false state space /EFEG
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/3450 31/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-05 7517108 m, 712064 m/sec, 15855902 t fired, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F true state space / EG
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF false state space /EFEG
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: F true state space / EG
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EFAG unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: AGAF false state space /EFEG
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ true CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker


Time elapsed: 165 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00500vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC00500vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703600866"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00500vD.tgz
mv TwoPhaseLocking-PT-nC00500vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;