Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703600865.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC00500vD, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703600865
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 544K
-rw-r--r-- 1 mcc users 7.7K Feb 25 17:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 25 17:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 17:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 17:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:23 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:23 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 25 17:43 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 173K Feb 25 17:43 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 17:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 103K Feb 25 17:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:23 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-00
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-04
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-05
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-06
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-07
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-09
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-10
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-13
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15

=== Now, execution of the tool begins

BK_START 1679224441513

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC00500vD
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:14:03] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 11:14:03] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:14:03] [INFO ] Load time of PNML (sax parser for PT used): 19 ms
[2023-03-19 11:14:03] [INFO ] Transformed 8 places.
[2023-03-19 11:14:03] [INFO ] Transformed 6 transitions.
[2023-03-19 11:14:03] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 82 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 13 ms.
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 9 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:14:03] [INFO ] Computed 3 place invariants in 8 ms
[2023-03-19 11:14:03] [INFO ] Implicit Places using invariants in 147 ms returned []
[2023-03-19 11:14:03] [INFO ] Invariant cache hit.
[2023-03-19 11:14:03] [INFO ] Implicit Places using invariants and state equation in 32 ms returned []
Implicit Place search using SMT with State Equation took 209 ms to find 0 implicit places.
[2023-03-19 11:14:03] [INFO ] Invariant cache hit.
[2023-03-19 11:14:03] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 246 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:14:03] [INFO ] Flatten gal took : 12 ms
[2023-03-19 11:14:03] [INFO ] Flatten gal took : 3 ms
[2023-03-19 11:14:03] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10039 steps, including 3 resets, run finished after 52 ms. (steps per millisecond=193 ) properties (out of 75) seen :49
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 26) seen :0
Running SMT prover for 26 properties.
[2023-03-19 11:14:04] [INFO ] Invariant cache hit.
[2023-03-19 11:14:04] [INFO ] [Real]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 11:14:04] [INFO ] After 73ms SMT Verify possible using all constraints in real domain returned unsat :24 sat :0 real:2
[2023-03-19 11:14:04] [INFO ] [Nat]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 11:14:04] [INFO ] After 38ms SMT Verify possible using all constraints in natural domain returned unsat :26 sat :0
Fused 26 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 26 atomic propositions for a total of 16 simplifications.
FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 11:14:04] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 2 ms
FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 7 transition count 4
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 6 place count 5 transition count 3
Applied a total of 6 rules in 5 ms. Remains 5 /8 variables (removed 3) and now considering 3/6 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 5/8 places, 3/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 3 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 1 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 1 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 1 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 4 transitions.
Finished random walk after 503 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=503 )
FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 1 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 5 transitions.
Finished random walk after 251 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=251 )
FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:14:04] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:14:04] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 1 ms.
[2023-03-19 11:14:04] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 0 ms.
Total runtime 1326 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC00500vD
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 13290136 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16104268 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH INITIAL
lola: LAUNCH task # 44 (type CNST) for 31 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 44 (type CNST) for TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12
lola: result : false
lola: LAUNCH task # 17 (type EXCL) for 16 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-04
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: LAUNCH task # 53 (type FNDP) for 31 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 17 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLCardinality-04
lola: result : true
lola: markings : 1755
lola: fired transitions : 9734
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11
lola: result : true
lola: markings : 985
lola: fired transitions : 1573
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 23 (type EXCL) for 22 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 53 (type FNDP) for TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12
lola: result : true
lola: fired transitions : 748529
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 23 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08
lola: result : true
lola: markings : 435777
lola: fired transitions : 775010
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 50 (type EXCL) for 49 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15
lola: time limit : 327 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-00: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12: DISJ 0 2 0 0 4 0 0 1
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 4/327 17/32 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15 3903831 m, 780766 m/sec, 9713995 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-00: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12: DISJ 0 2 0 0 4 0 0 1
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 9/327 31/32 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15 7273885 m, 674010 m/sec, 18770323 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11: CTL true CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12: DISJ 0 2 0 0 4 0 0 1
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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lola: time limit : 358 sec
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lola: FINISHED task # 47 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14
lola: result : false
lola: markings : 1147897
lola: fired transitions : 1567142
lola: time used : 1.000000
lola: memory pages used : 5
lola: LAUNCH task # 42 (type EXCL) for 31 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12
lola: time limit : 398 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02
lola: time limit : 512 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12: DISJ true DISJ
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-00: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 4/512 5/32 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02 1239451 m, 247890 m/sec, 5795059 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12: DISJ true DISJ
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-00: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 9/512 11/32 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02 2504563 m, 253022 m/sec, 11870986 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12: DISJ true DISJ
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-00: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 14/512 15/32 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02 3601625 m, 219412 m/sec, 17173718 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12: DISJ true DISJ
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-00: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 19/512 19/32 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02 4687759 m, 217226 m/sec, 22443208 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12: DISJ true DISJ
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-00: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 24/512 24/32 TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02 5766411 m, 215730 m/sec, 27698491 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-12: DISJ true DISJ
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLCardinality-00: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLCardinality-03: EFAG 0 1 0 0 1 0 0 0
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