Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703600842.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC00100vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703600842
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 464K
-rw-r--r-- 1 mcc users 7.6K Feb 25 17:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 25 17:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 25 17:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 25 17:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:23 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:23 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Feb 25 17:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 25 17:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:23 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679224070083

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC00100vN
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:07:51] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 11:07:51] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:07:51] [INFO ] Load time of PNML (sax parser for PT used): 21 ms
[2023-03-19 11:07:51] [INFO ] Transformed 8 places.
[2023-03-19 11:07:51] [INFO ] Transformed 6 transitions.
[2023-03-19 11:07:51] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 272 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 13 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:07:51] [INFO ] Computed 3 place invariants in 6 ms
[2023-03-19 11:07:52] [INFO ] Implicit Places using invariants in 138 ms returned []
[2023-03-19 11:07:52] [INFO ] Invariant cache hit.
[2023-03-19 11:07:52] [INFO ] Implicit Places using invariants and state equation in 50 ms returned []
Implicit Place search using SMT with State Equation took 214 ms to find 0 implicit places.
[2023-03-19 11:07:52] [INFO ] Invariant cache hit.
[2023-03-19 11:07:52] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 256 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 14 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 3 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10007 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 25) seen :24
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=769 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-19 11:07:52] [INFO ] Invariant cache hit.
[2023-03-19 11:07:52] [INFO ] After 31ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 2 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 7 transition count 4
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 2 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 2 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 1 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:07:52] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:07:52] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 11:07:52] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 0 ms.
Total runtime 1063 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC00100vN
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679224318942

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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TwoPhaseLocking-PT-nC00100vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00100vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 5/200 11/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-10 2521443 m, 504288 m/sec, 8093747 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 10/200 17/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-10 4027363 m, 301184 m/sec, 14987439 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 15/200 22/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-10 5444505 m, 283428 m/sec, 21741777 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 20/200 28/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-10 6721732 m, 255445 m/sec, 28370309 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 5/210 8/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-12 1990313 m, 398062 m/sec, 9695557 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 10/210 13/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-12 3073087 m, 216554 m/sec, 17830132 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 15/210 17/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-12 4140078 m, 213398 m/sec, 25602263 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 20/210 21/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-12 5182838 m, 208552 m/sec, 33091848 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 15/233 19/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-07 4571319 m, 272553 m/sec, 24584112 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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30 CTL EXCL 20/233 24/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-07 5873209 m, 260378 m/sec, 31717268 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 25/233 29/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-07 7134206 m, 252199 m/sec, 38625913 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 5/267 15/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-05 3578876 m, 715775 m/sec, 6483349 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 10/267 23/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-05 5558266 m, 395878 m/sec, 12173820 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 15/267 28/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-05 6923635 m, 273073 m/sec, 17636330 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 20/267 32/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-05 7904512 m, 196175 m/sec, 23074157 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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21 CTL EXCL 4/862 15/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-04 3499265 m, 699853 m/sec, 6120890 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vN-CTLFireability-08: EFEG false state space /EFEG
TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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21 CTL EXCL 9/862 23/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-04 5622534 m, 424653 m/sec, 11901175 t fired, .

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21 CTL EXCL 14/862 29/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-04 7077627 m, 291018 m/sec, 17465589 t fired, .

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54 CTL EXCL 5/1715 6/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-15 1358509 m, 271701 m/sec, 8194891 t fired, .

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54 CTL EXCL 10/1715 11/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-15 2550081 m, 238314 m/sec, 15562471 t fired, .

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54 CTL EXCL 15/1715 15/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-15 3698843 m, 229752 m/sec, 22700135 t fired, .

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54 CTL EXCL 20/1715 20/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-15 4792247 m, 218680 m/sec, 29541858 t fired, .

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54 CTL EXCL 25/1715 24/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-15 5859128 m, 213376 m/sec, 36269632 t fired, .

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54 CTL EXCL 30/1715 28/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-15 6909198 m, 210014 m/sec, 42945068 t fired, .

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54 CTL EXCL 35/1715 32/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-15 7939992 m, 206158 m/sec, 49547652 t fired, .

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42 CTL EXCL 5/3390 7/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-11 1640129 m, 328025 m/sec, 9678889 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/3390 13/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-11 3014128 m, 274799 m/sec, 18260427 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 15/3390 18/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-11 4273300 m, 251834 m/sec, 26193967 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vN-CTLFireability-08: EFEG false state space /EFEG
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TwoPhaseLocking-PT-nC00100vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 20/3390 23/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-11 5481855 m, 241711 m/sec, 33852811 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-08: EFEG false state space /EFEG
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TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 25/3390 27/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-11 6666532 m, 236935 m/sec, 41407626 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 30/3390 32/32 TwoPhaseLocking-PT-nC00100vN-CTLFireability-11 7849363 m, 236566 m/sec, 48986346 t fired, .

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TwoPhaseLocking-PT-nC00100vN-CTLFireability-08: EFEG false state space /EFEG
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vN-CTLFireability-00: DISJ false DISJ
TwoPhaseLocking-PT-nC00100vN-CTLFireability-01: CONJ true CONJ
TwoPhaseLocking-PT-nC00100vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vN-CTLFireability-04: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vN-CTLFireability-05: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vN-CTLFireability-07: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vN-CTLFireability-08: EFEG false state space /EFEG
TwoPhaseLocking-PT-nC00100vN-CTLFireability-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vN-CTLFireability-10: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vN-CTLFireability-11: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vN-CTLFireability-12: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vN-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vN-CTLFireability-14: CTL false CTL model checker
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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00100vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC00100vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703600842"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00100vN.tgz
mv TwoPhaseLocking-PT-nC00100vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;