Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703600834.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC00100vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703600834
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 456K
-rw-r--r-- 1 mcc users 7.2K Feb 25 17:31 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 25 17:31 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 17:30 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 25 17:30 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:23 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:23 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 131K Feb 25 17:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 25 17:31 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 25 17:31 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:23 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679223954364

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC00100vD
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:05:56] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 11:05:56] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:05:56] [INFO ] Load time of PNML (sax parser for PT used): 17 ms
[2023-03-19 11:05:56] [INFO ] Transformed 8 places.
[2023-03-19 11:05:56] [INFO ] Transformed 6 transitions.
[2023-03-19 11:05:56] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 73 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
Initial state reduction rules removed 1 formulas.
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 8 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:05:56] [INFO ] Computed 3 place invariants in 4 ms
[2023-03-19 11:05:56] [INFO ] Implicit Places using invariants in 129 ms returned []
[2023-03-19 11:05:56] [INFO ] Invariant cache hit.
[2023-03-19 11:05:56] [INFO ] Implicit Places using invariants and state equation in 40 ms returned []
Implicit Place search using SMT with State Equation took 196 ms to find 0 implicit places.
[2023-03-19 11:05:56] [INFO ] Invariant cache hit.
[2023-03-19 11:05:56] [INFO ] Dead Transitions using invariants and state equation in 40 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 246 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 12 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 4 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10000 steps, including 22 resets, run finished after 71 ms. (steps per millisecond=140 ) properties (out of 25) seen :23
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10000 steps, including 11 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-19 11:05:56] [INFO ] Invariant cache hit.
[2023-03-19 11:05:56] [INFO ] [Real]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 11:05:56] [INFO ] After 29ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 2 atomic propositions for a total of 15 simplifications.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 3 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 3 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 8 transition count 5
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 2 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:05:56] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 11:05:56] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 0 ms.
Total runtime 939 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC00100vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/371
CTLFireability

FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679224183408

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/371/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/371/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/371/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 66 (type FNDP) for 27 TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type EQUN) for 27 TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type SRCH) for 27 TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 69 (type SRCH) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 66 (type FNDP) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: result : true
lola: fired transitions : 49
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 67 (type EQUN) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 71 (type FNDP) for 3 TwoPhaseLocking-PT-nC00100vD-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
sara: try reading problem file /home/mcc/execution/371/CTLFireability-67.sara.
lola: FINISHED task # 71 (type FNDP) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-01
lola: result : true
lola: fired transitions : 35138
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0

lola: FINISHED task # 67 (type EQUN) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/239 6/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 1376740 m, 275348 m/sec, 6995558 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/239 11/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 2619583 m, 248568 m/sec, 13461443 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/239 16/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 3808833 m, 237850 m/sec, 19701493 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/239 20/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 4958877 m, 230008 m/sec, 25767145 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/239 25/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 6084317 m, 225088 m/sec, 31732427 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 30/239 29/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 7192335 m, 221603 m/sec, 37623019 t fired, .

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lola: CANCELED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 36 secs. Pages in use: 32
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lola: LAUNCH task # 57 (type EXCL) for 54 TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
lola: time limit : 254 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
lola: result : true
lola: markings : 51
lola: fired transitions : 102
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 51 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13
lola: time limit : 274 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 5/274 4/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 907245 m, 181449 m/sec, 6713350 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 10/274 7/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 1662874 m, 151125 m/sec, 12831509 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 15/274 10/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 2369872 m, 141399 m/sec, 18754681 t fired, .

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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52 CTL EXCL 20/274 13/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 3037048 m, 133435 m/sec, 24541859 t fired, .

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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52 CTL EXCL 25/274 15/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 3684589 m, 129508 m/sec, 30258921 t fired, .

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52 CTL EXCL 30/274 18/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 4309538 m, 124989 m/sec, 35903279 t fired, .

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52 CTL EXCL 35/274 20/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 4916360 m, 121364 m/sec, 41481492 t fired, .

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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52 CTL EXCL 40/274 23/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 5508102 m, 118348 m/sec, 47025234 t fired, .

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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52 CTL EXCL 45/274 25/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 6088344 m, 116048 m/sec, 52541613 t fired, .

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52 CTL EXCL 50/274 27/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 6650342 m, 112399 m/sec, 58020579 t fired, .

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
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52 CTL EXCL 55/274 29/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 7200069 m, 109945 m/sec, 63490760 t fired, .

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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52 CTL EXCL 60/274 32/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 7737326 m, 107451 m/sec, 68921484 t fired, .

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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49 CTL EXCL 10/291 15/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-12 3591014 m, 296397 m/sec, 13759592 t fired, .

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker

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25 CTL EXCL 25/346 28/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-08 6888745 m, 245828 m/sec, 28948889 t fired, .

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TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/429 28/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-06 6781716 m, 202646 m/sec, 24836636 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/429 31/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-06 7583886 m, 160434 m/sec, 30756924 t fired, .

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lola: CANCELED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 191 secs. Pages in use: 32
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lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC00100vD-CTLFireability-03
lola: time limit : 487 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-03
lola: result : false
lola: markings : 200
lola: fired transitions : 204
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC00100vD-CTLFireability-02
lola: time limit : 568 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-02
lola: result : true
lola: markings : 151
lola: fired transitions : 150
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 63 (type EXCL) for 54 TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
lola: time limit : 681 sec
lola: memory limit: 32 pages
lola: FINISHED task # 63 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
lola: result : false
lola: markings : 151
lola: fired transitions : 153
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 TwoPhaseLocking-PT-nC00100vD-CTLFireability-11
lola: time limit : 852 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-11
lola: result : true
lola: markings : 202
lola: fired transitions : 606
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 54 TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
lola: time limit : 1136 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC00100vD-CTLFireability-04
lola: time limit : 1704 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-04
lola: result : false
lola: markings : 247
lola: fired transitions : 298
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00
lola: time limit : 3409 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/3409 6/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 1398388 m, 279677 m/sec, 6000928 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/3409 11/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 2623541 m, 245030 m/sec, 11429820 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/3409 16/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 3788301 m, 232952 m/sec, 16682524 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/3409 20/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 4942416 m, 230823 m/sec, 21881036 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/3409 25/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 6055775 m, 222671 m/sec, 27032141 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/3409 29/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 7083364 m, 205517 m/sec, 32125294 t fired, .

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lola: CANCELED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: EF DL true findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ


Time elapsed: 226 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00100vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC00100vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703600834"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00100vD.tgz
mv TwoPhaseLocking-PT-nC00100vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;