About the Execution of LoLa+red for Szymanski-PT-b04
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 8586.876 | 3600000.00 | 12368452.00 | 3939.20 | ?F?FF?????FTT??F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703100458.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Szymanski-PT-b04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703100458
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.2M
-rw-r--r-- 1 mcc users 8.4K Feb 26 16:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K Feb 26 16:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 16:52 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 26 16:52 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 17:19 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:19 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:19 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K Feb 25 17:19 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Feb 26 16:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 205K Feb 26 16:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 16:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 95K Feb 26 16:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:19 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:19 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 3.7M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Szymanski-PT-b04-CTLFireability-00
FORMULA_NAME Szymanski-PT-b04-CTLFireability-01
FORMULA_NAME Szymanski-PT-b04-CTLFireability-02
FORMULA_NAME Szymanski-PT-b04-CTLFireability-03
FORMULA_NAME Szymanski-PT-b04-CTLFireability-04
FORMULA_NAME Szymanski-PT-b04-CTLFireability-05
FORMULA_NAME Szymanski-PT-b04-CTLFireability-06
FORMULA_NAME Szymanski-PT-b04-CTLFireability-07
FORMULA_NAME Szymanski-PT-b04-CTLFireability-08
FORMULA_NAME Szymanski-PT-b04-CTLFireability-09
FORMULA_NAME Szymanski-PT-b04-CTLFireability-10
FORMULA_NAME Szymanski-PT-b04-CTLFireability-11
FORMULA_NAME Szymanski-PT-b04-CTLFireability-12
FORMULA_NAME Szymanski-PT-b04-CTLFireability-13
FORMULA_NAME Szymanski-PT-b04-CTLFireability-14
FORMULA_NAME Szymanski-PT-b04-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679190183507
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Szymanski-PT-b04
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 01:43:05] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 01:43:05] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 01:43:05] [INFO ] Load time of PNML (sax parser for PT used): 295 ms
[2023-03-19 01:43:05] [INFO ] Transformed 568 places.
[2023-03-19 01:43:05] [INFO ] Transformed 8320 transitions.
[2023-03-19 01:43:05] [INFO ] Parsed PT model containing 568 places and 8320 transitions and 33408 arcs in 398 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
Deduced a syphon composed of 260 places in 18 ms
Reduce places removed 260 places and 256 transitions.
Support contains 123 out of 308 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 308/308 places, 8064/8064 transitions.
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 306 transition count 8064
Applied a total of 2 rules in 129 ms. Remains 306 /308 variables (removed 2) and now considering 8064/8064 (removed 0) transitions.
[2023-03-19 01:43:05] [INFO ] Flow matrix only has 2733 transitions (discarded 5331 similar events)
// Phase 1: matrix 2733 rows 306 cols
[2023-03-19 01:43:05] [INFO ] Computed 1 place invariants in 56 ms
[2023-03-19 01:43:06] [INFO ] Implicit Places using invariants in 443 ms returned []
[2023-03-19 01:43:06] [INFO ] Flow matrix only has 2733 transitions (discarded 5331 similar events)
[2023-03-19 01:43:06] [INFO ] Invariant cache hit.
[2023-03-19 01:43:06] [INFO ] State equation strengthened by 147 read => feed constraints.
[2023-03-19 01:43:08] [INFO ] Implicit Places using invariants and state equation in 2151 ms returned []
Implicit Place search using SMT with State Equation took 2629 ms to find 0 implicit places.
[2023-03-19 01:43:08] [INFO ] Flow matrix only has 2733 transitions (discarded 5331 similar events)
[2023-03-19 01:43:08] [INFO ] Invariant cache hit.
[2023-03-19 01:43:10] [INFO ] Dead Transitions using invariants and state equation in 2088 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 306/308 places, 8064/8064 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4851 ms. Remains : 306/308 places, 8064/8064 transitions.
Support contains 123 out of 306 places after structural reductions.
[2023-03-19 01:43:11] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-19 01:43:11] [INFO ] Flatten gal took : 403 ms
FORMULA Szymanski-PT-b04-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 01:43:11] [INFO ] Flatten gal took : 233 ms
[2023-03-19 01:43:11] [INFO ] Input system was already deterministic with 8064 transitions.
Support contains 115 out of 306 places (down from 123) after GAL structural reductions.
Incomplete random walk after 10003 steps, including 2 resets, run finished after 270 ms. (steps per millisecond=37 ) properties (out of 75) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 72) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 70) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 67) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 66) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 65) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 63) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 63) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 62) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 59) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 58) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 57) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 56) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 55) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 53) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 53) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 52) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 51) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 51) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 51) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 51) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 51) seen :0
Running SMT prover for 51 properties.
[2023-03-19 01:43:12] [INFO ] Flow matrix only has 2733 transitions (discarded 5331 similar events)
[2023-03-19 01:43:12] [INFO ] Invariant cache hit.
[2023-03-19 01:43:13] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 4 ms returned sat
[2023-03-19 01:43:13] [INFO ] After 546ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:51
[2023-03-19 01:43:14] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 3 ms returned sat
[2023-03-19 01:43:38] [INFO ] After 24469ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :48
[2023-03-19 01:43:38] [INFO ] State equation strengthened by 147 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-19 01:43:38] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-19 01:43:38] [INFO ] After 25036ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:51
Fused 51 Parikh solutions to 18 different solutions.
Parikh walk visited 0 properties in 505 ms.
Support contains 86 out of 306 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Drop transitions removed 39 transitions
Reduce isomorphic transitions removed 39 transitions.
Iterating post reduction 0 with 39 rules applied. Total rules applied 39 place count 306 transition count 8025
Applied a total of 39 rules in 402 ms. Remains 306 /306 variables (removed 0) and now considering 8025/8064 (removed 39) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 403 ms. Remains : 306/306 places, 8025/8064 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 191 ms. (steps per millisecond=52 ) properties (out of 50) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 49) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 48) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 46) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 45) seen :0
Running SMT prover for 45 properties.
[2023-03-19 01:43:40] [INFO ] Flow matrix only has 2694 transitions (discarded 5331 similar events)
// Phase 1: matrix 2694 rows 306 cols
[2023-03-19 01:43:40] [INFO ] Computed 1 place invariants in 24 ms
[2023-03-19 01:43:40] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-19 01:43:40] [INFO ] After 391ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:45
[2023-03-19 01:43:41] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 3 ms returned sat
[2023-03-19 01:44:05] [INFO ] After 24550ms SMT Verify possible using state equation in natural domain returned unsat :4 sat :40
[2023-03-19 01:44:05] [INFO ] State equation strengthened by 147 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-19 01:44:05] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-19 01:44:05] [INFO ] After 25031ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:45
Fused 45 Parikh solutions to 27 different solutions.
Parikh walk visited 0 properties in 486 ms.
Support contains 63 out of 306 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 306/306 places, 8025/8025 transitions.
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 6 place count 306 transition count 8019
Applied a total of 6 rules in 234 ms. Remains 306 /306 variables (removed 0) and now considering 8019/8025 (removed 6) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 234 ms. Remains : 306/306 places, 8019/8025 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 220 ms. (steps per millisecond=45 ) properties (out of 41) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 39) seen :0
Interrupted probabilistic random walk after 118958 steps, run timeout after 3001 ms. (steps per millisecond=39 ) properties seen :{4=1, 11=1, 17=1, 34=1, 38=1}
Probabilistic random walk after 118958 steps, saw 46222 distinct states, run finished after 3002 ms. (steps per millisecond=39 ) properties seen :5
Running SMT prover for 34 properties.
[2023-03-19 01:44:10] [INFO ] Flow matrix only has 2688 transitions (discarded 5331 similar events)
// Phase 1: matrix 2688 rows 306 cols
[2023-03-19 01:44:10] [INFO ] Computed 1 place invariants in 23 ms
[2023-03-19 01:44:10] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 4 ms returned sat
[2023-03-19 01:44:17] [INFO ] After 6998ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:34
[2023-03-19 01:44:17] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-19 01:44:41] [INFO ] After 23452ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :33
[2023-03-19 01:44:41] [INFO ] State equation strengthened by 147 read => feed constraints.
[2023-03-19 01:44:42] [INFO ] After 1173ms SMT Verify possible using 147 Read/Feed constraints in natural domain returned unsat :1 sat :32
[2023-03-19 01:44:42] [INFO ] After 1173ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :32
Attempting to minimize the solution found.
Minimization took 1 ms.
[2023-03-19 01:44:42] [INFO ] After 25011ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :32
Fused 34 Parikh solutions to 33 different solutions.
Parikh walk visited 0 properties in 426 ms.
Support contains 49 out of 306 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 306/306 places, 8019/8019 transitions.
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 306 transition count 8015
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 5 place count 305 transition count 7887
Iterating global reduction 1 with 1 rules applied. Total rules applied 6 place count 305 transition count 7887
Applied a total of 6 rules in 361 ms. Remains 305 /306 variables (removed 1) and now considering 7887/8019 (removed 132) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 362 ms. Remains : 305/306 places, 7887/8019 transitions.
Incomplete random walk after 10002 steps, including 2 resets, run finished after 120 ms. (steps per millisecond=83 ) properties (out of 33) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 32) seen :0
Interrupted probabilistic random walk after 113862 steps, run timeout after 3001 ms. (steps per millisecond=37 ) properties seen :{4=1, 8=1}
Probabilistic random walk after 113862 steps, saw 47096 distinct states, run finished after 3001 ms. (steps per millisecond=37 ) properties seen :2
Running SMT prover for 30 properties.
[2023-03-19 01:44:46] [INFO ] Flow matrix only has 2683 transitions (discarded 5204 similar events)
// Phase 1: matrix 2683 rows 305 cols
[2023-03-19 01:44:46] [INFO ] Computed 1 place invariants in 19 ms
[2023-03-19 01:44:46] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 3 ms returned sat
[2023-03-19 01:44:58] [INFO ] After 11883ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:30
[2023-03-19 01:44:58] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 3 ms returned sat
[2023-03-19 01:45:23] [INFO ] After 24710ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :28
[2023-03-19 01:45:23] [INFO ] State equation strengthened by 147 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-19 01:45:23] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-19 01:45:23] [INFO ] After 25030ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:30
Fused 30 Parikh solutions to 23 different solutions.
Parikh walk visited 0 properties in 271 ms.
Support contains 45 out of 305 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 305/305 places, 7887/7887 transitions.
Applied a total of 0 rules in 183 ms. Remains 305 /305 variables (removed 0) and now considering 7887/7887 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 183 ms. Remains : 305/305 places, 7887/7887 transitions.
Successfully simplified 6 atomic propositions for a total of 15 simplifications.
FORMULA Szymanski-PT-b04-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 01:45:24] [INFO ] Flatten gal took : 174 ms
[2023-03-19 01:45:24] [INFO ] Flatten gal took : 193 ms
[2023-03-19 01:45:24] [INFO ] Input system was already deterministic with 8064 transitions.
Computed a total of 12 stabilizing places and 2432 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 305 transition count 7936
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 7936
Applied a total of 2 rules in 621 ms. Remains 305 /306 variables (removed 1) and now considering 7936/8064 (removed 128) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 628 ms. Remains : 305/306 places, 7936/8064 transitions.
[2023-03-19 01:45:25] [INFO ] Flatten gal took : 165 ms
[2023-03-19 01:45:25] [INFO ] Flatten gal took : 188 ms
[2023-03-19 01:45:25] [INFO ] Input system was already deterministic with 7936 transitions.
Incomplete random walk after 10002 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 4 resets, run finished after 11 ms. (steps per millisecond=909 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 189376 steps, run timeout after 3001 ms. (steps per millisecond=63 ) properties seen :{}
Probabilistic random walk after 189376 steps, saw 69428 distinct states, run finished after 3003 ms. (steps per millisecond=63 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 01:45:29] [INFO ] Flow matrix only has 2732 transitions (discarded 5204 similar events)
// Phase 1: matrix 2732 rows 305 cols
[2023-03-19 01:45:29] [INFO ] Computed 1 place invariants in 28 ms
[2023-03-19 01:45:29] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-19 01:45:30] [INFO ] After 1780ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 01:45:30] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-19 01:45:32] [INFO ] After 1564ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 01:45:32] [INFO ] State equation strengthened by 147 read => feed constraints.
[2023-03-19 01:45:35] [INFO ] After 3165ms SMT Verify possible using 147 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 01:45:35] [INFO ] After 3329ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 168 ms.
[2023-03-19 01:45:35] [INFO ] After 5142ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 481 ms.
Support contains 2 out of 305 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 305/305 places, 7936/7936 transitions.
Drop transitions removed 127 transitions
Reduce isomorphic transitions removed 127 transitions.
Iterating post reduction 0 with 127 rules applied. Total rules applied 127 place count 305 transition count 7809
Applied a total of 127 rules in 226 ms. Remains 305 /305 variables (removed 0) and now considering 7809/7936 (removed 127) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 227 ms. Remains : 305/305 places, 7809/7936 transitions.
Incomplete random walk after 1000000 steps, including 2 resets, run finished after 2264 ms. (steps per millisecond=441 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000001 steps, including 2 resets, run finished after 998 ms. (steps per millisecond=1002 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 641374 steps, run timeout after 9001 ms. (steps per millisecond=71 ) properties seen :{}
Probabilistic random walk after 641374 steps, saw 195412 distinct states, run finished after 9001 ms. (steps per millisecond=71 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 01:45:48] [INFO ] Flow matrix only has 2605 transitions (discarded 5204 similar events)
// Phase 1: matrix 2605 rows 305 cols
[2023-03-19 01:45:48] [INFO ] Computed 2 place invariants in 19 ms
[2023-03-19 01:45:49] [INFO ] [Real]Absence check using 0 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 01:45:50] [INFO ] After 1504ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 01:45:50] [INFO ] [Nat]Absence check using 0 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 01:45:51] [INFO ] After 1033ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 01:45:51] [INFO ] State equation strengthened by 147 read => feed constraints.
[2023-03-19 01:45:56] [INFO ] After 4951ms SMT Verify possible using 147 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 01:45:57] [INFO ] Deduced a trap composed of 72 places in 387 ms of which 1 ms to minimize.
[2023-03-19 01:45:58] [INFO ] Deduced a trap composed of 134 places in 335 ms of which 1 ms to minimize.
[2023-03-19 01:45:58] [INFO ] Deduced a trap composed of 101 places in 357 ms of which 0 ms to minimize.
[2023-03-19 01:45:58] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 1689 ms
[2023-03-19 01:45:58] [INFO ] After 7041ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 74 ms.
[2023-03-19 01:45:58] [INFO ] After 8212ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 3 ms.
Support contains 2 out of 305 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 305/305 places, 7809/7809 transitions.
Applied a total of 0 rules in 204 ms. Remains 305 /305 variables (removed 0) and now considering 7809/7809 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 205 ms. Remains : 305/305 places, 7809/7809 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 305/305 places, 7809/7809 transitions.
Applied a total of 0 rules in 179 ms. Remains 305 /305 variables (removed 0) and now considering 7809/7809 (removed 0) transitions.
[2023-03-19 01:45:59] [INFO ] Flow matrix only has 2605 transitions (discarded 5204 similar events)
[2023-03-19 01:45:59] [INFO ] Invariant cache hit.
[2023-03-19 01:45:59] [INFO ] Implicit Places using invariants in 447 ms returned []
[2023-03-19 01:45:59] [INFO ] Flow matrix only has 2605 transitions (discarded 5204 similar events)
[2023-03-19 01:45:59] [INFO ] Invariant cache hit.
[2023-03-19 01:45:59] [INFO ] State equation strengthened by 147 read => feed constraints.
[2023-03-19 01:46:07] [INFO ] Implicit Places using invariants and state equation in 7747 ms returned []
Implicit Place search using SMT with State Equation took 8197 ms to find 0 implicit places.
[2023-03-19 01:46:08] [INFO ] Redundant transitions in 905 ms returned []
[2023-03-19 01:46:08] [INFO ] Flow matrix only has 2605 transitions (discarded 5204 similar events)
[2023-03-19 01:46:08] [INFO ] Invariant cache hit.
[2023-03-19 01:46:10] [INFO ] Dead Transitions using invariants and state equation in 2043 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 11337 ms. Remains : 305/305 places, 7809/7809 transitions.
Incomplete random walk after 100003 steps, including 2 resets, run finished after 468 ms. (steps per millisecond=213 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-19 01:46:10] [INFO ] Flow matrix only has 2605 transitions (discarded 5204 similar events)
[2023-03-19 01:46:10] [INFO ] Invariant cache hit.
[2023-03-19 01:46:10] [INFO ] [Real]Absence check using 0 positive and 2 generalized place invariants in 4 ms returned sat
[2023-03-19 01:46:12] [INFO ] After 1297ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 01:46:12] [INFO ] State equation strengthened by 147 read => feed constraints.
[2023-03-19 01:46:12] [INFO ] After 390ms SMT Verify possible using 147 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-19 01:46:12] [INFO ] After 771ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 01:46:12] [INFO ] After 2194ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 01:46:12] [INFO ] [Nat]Absence check using 0 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 01:46:14] [INFO ] After 1172ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 01:46:21] [INFO ] After 6989ms SMT Verify possible using 147 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 01:46:21] [INFO ] Deduced a trap composed of 72 places in 261 ms of which 0 ms to minimize.
[2023-03-19 01:46:21] [INFO ] Deduced a trap composed of 134 places in 258 ms of which 1 ms to minimize.
[2023-03-19 01:46:22] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 1073 ms
[2023-03-19 01:46:22] [INFO ] After 8137ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 146 ms.
[2023-03-19 01:46:22] [INFO ] After 9503ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Incomplete random walk after 1000000 steps, including 2 resets, run finished after 1914 ms. (steps per millisecond=522 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000001 steps, including 2 resets, run finished after 991 ms. (steps per millisecond=1009 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 413428 steps, run timeout after 6001 ms. (steps per millisecond=68 ) properties seen :{}
Probabilistic random walk after 413428 steps, saw 127050 distinct states, run finished after 6001 ms. (steps per millisecond=68 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 01:46:31] [INFO ] Flow matrix only has 2605 transitions (discarded 5204 similar events)
[2023-03-19 01:46:31] [INFO ] Invariant cache hit.
[2023-03-19 01:46:31] [INFO ] [Real]Absence check using 0 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 01:46:32] [INFO ] After 1473ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 01:46:32] [INFO ] [Nat]Absence check using 0 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 01:46:33] [INFO ] After 1032ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 01:46:33] [INFO ] State equation strengthened by 147 read => feed constraints.
[2023-03-19 01:46:38] [INFO ] After 4941ms SMT Verify possible using 147 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 01:46:39] [INFO ] Deduced a trap composed of 72 places in 330 ms of which 5 ms to minimize.
[2023-03-19 01:46:40] [INFO ] Deduced a trap composed of 134 places in 350 ms of which 1 ms to minimize.
[2023-03-19 01:46:40] [INFO ] Deduced a trap composed of 101 places in 362 ms of which 0 ms to minimize.
[2023-03-19 01:46:40] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 1668 ms
[2023-03-19 01:46:40] [INFO ] After 7013ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 78 ms.
[2023-03-19 01:46:41] [INFO ] After 8188ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 3 ms.
Support contains 2 out of 305 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 305/305 places, 7809/7809 transitions.
Applied a total of 0 rules in 205 ms. Remains 305 /305 variables (removed 0) and now considering 7809/7809 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 206 ms. Remains : 305/305 places, 7809/7809 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 305/305 places, 7809/7809 transitions.
Applied a total of 0 rules in 198 ms. Remains 305 /305 variables (removed 0) and now considering 7809/7809 (removed 0) transitions.
[2023-03-19 01:46:41] [INFO ] Flow matrix only has 2605 transitions (discarded 5204 similar events)
[2023-03-19 01:46:41] [INFO ] Invariant cache hit.
[2023-03-19 01:46:41] [INFO ] Implicit Places using invariants in 460 ms returned []
[2023-03-19 01:46:41] [INFO ] Flow matrix only has 2605 transitions (discarded 5204 similar events)
[2023-03-19 01:46:41] [INFO ] Invariant cache hit.
[2023-03-19 01:46:42] [INFO ] State equation strengthened by 147 read => feed constraints.
[2023-03-19 01:46:49] [INFO ] Implicit Places using invariants and state equation in 7216 ms returned []
Implicit Place search using SMT with State Equation took 7692 ms to find 0 implicit places.
[2023-03-19 01:46:49] [INFO ] Redundant transitions in 646 ms returned []
[2023-03-19 01:46:49] [INFO ] Flow matrix only has 2605 transitions (discarded 5204 similar events)
[2023-03-19 01:46:49] [INFO ] Invariant cache hit.
[2023-03-19 01:46:51] [INFO ] Dead Transitions using invariants and state equation in 1839 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10388 ms. Remains : 305/305 places, 7809/7809 transitions.
Incomplete random walk after 100000 steps, including 2 resets, run finished after 226 ms. (steps per millisecond=442 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-19 01:46:51] [INFO ] Flow matrix only has 2605 transitions (discarded 5204 similar events)
[2023-03-19 01:46:51] [INFO ] Invariant cache hit.
[2023-03-19 01:46:51] [INFO ] [Real]Absence check using 0 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 01:46:53] [INFO ] After 1105ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 01:46:53] [INFO ] State equation strengthened by 147 read => feed constraints.
[2023-03-19 01:46:53] [INFO ] After 401ms SMT Verify possible using 147 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-19 01:46:53] [INFO ] After 802ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 01:46:53] [INFO ] After 1975ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 01:46:53] [INFO ] [Nat]Absence check using 0 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 01:46:55] [INFO ] After 1165ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 01:47:02] [INFO ] After 7190ms SMT Verify possible using 147 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 01:47:02] [INFO ] Deduced a trap composed of 72 places in 265 ms of which 0 ms to minimize.
[2023-03-19 01:47:02] [INFO ] Deduced a trap composed of 134 places in 241 ms of which 0 ms to minimize.
[2023-03-19 01:47:03] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 1069 ms
[2023-03-19 01:47:03] [INFO ] After 8330ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 147 ms.
[2023-03-19 01:47:03] [INFO ] After 9690ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Incomplete random walk after 10000 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 1) seen :0
Finished Best-First random walk after 202 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=101 )
Finished random walk after 176 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=88 )
Graph (trivial) has 5064 edges and 305 vertex of which 28 / 305 are part of one of the 5 SCC in 5 ms
Free SCC test removed 23 places
Drop transitions removed 3104 transitions
Ensure Unique test removed 2327 transitions
Reduce isomorphic transitions removed 5431 transitions.
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 4 Pre rules applied. Total rules applied 1 place count 282 transition count 2374
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 9 place count 278 transition count 2374
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 13 place count 276 transition count 2372
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 14 place count 276 transition count 2371
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 14 place count 276 transition count 2370
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 16 place count 275 transition count 2370
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 17 place count 275 transition count 2370
Applied a total of 17 rules in 226 ms. Remains 275 /305 variables (removed 30) and now considering 2370/7809 (removed 5439) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 2370 rows 275 cols
[2023-03-19 01:47:03] [INFO ] Computed 2 place invariants in 20 ms
[2023-03-19 01:47:03] [INFO ] [Real]Absence check using 0 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 01:47:04] [INFO ] After 584ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 01:47:04] [INFO ] [Nat]Absence check using 0 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 01:47:05] [INFO ] After 599ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 01:47:05] [INFO ] State equation strengthened by 224 read => feed constraints.
[2023-03-19 01:47:05] [INFO ] After 148ms SMT Verify possible using 224 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 01:47:06] [INFO ] After 1038ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 175 ms.
[2023-03-19 01:47:06] [INFO ] After 1883ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in LTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Applied a total of 0 rules in 44 ms. Remains 306 /306 variables (removed 0) and now considering 8064/8064 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 44 ms. Remains : 306/306 places, 8064/8064 transitions.
[2023-03-19 01:47:06] [INFO ] Flatten gal took : 159 ms
[2023-03-19 01:47:06] [INFO ] Flatten gal took : 181 ms
[2023-03-19 01:47:07] [INFO ] Input system was already deterministic with 8064 transitions.
Starting structural reductions in LTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 305 transition count 7936
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 7936
Applied a total of 2 rules in 44 ms. Remains 305 /306 variables (removed 1) and now considering 7936/8064 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 45 ms. Remains : 305/306 places, 7936/8064 transitions.
[2023-03-19 01:47:07] [INFO ] Flatten gal took : 155 ms
[2023-03-19 01:47:07] [INFO ] Flatten gal took : 196 ms
[2023-03-19 01:47:07] [INFO ] Input system was already deterministic with 7936 transitions.
Starting structural reductions in LTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Applied a total of 0 rules in 23 ms. Remains 306 /306 variables (removed 0) and now considering 8064/8064 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 306/306 places, 8064/8064 transitions.
[2023-03-19 01:47:07] [INFO ] Flatten gal took : 154 ms
[2023-03-19 01:47:08] [INFO ] Flatten gal took : 176 ms
[2023-03-19 01:47:08] [INFO ] Input system was already deterministic with 8064 transitions.
Starting structural reductions in LTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 305 transition count 7936
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 7936
Applied a total of 2 rules in 41 ms. Remains 305 /306 variables (removed 1) and now considering 7936/8064 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 41 ms. Remains : 305/306 places, 7936/8064 transitions.
[2023-03-19 01:47:08] [INFO ] Flatten gal took : 149 ms
[2023-03-19 01:47:08] [INFO ] Flatten gal took : 170 ms
[2023-03-19 01:47:09] [INFO ] Input system was already deterministic with 7936 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Applied a total of 0 rules in 178 ms. Remains 306 /306 variables (removed 0) and now considering 8064/8064 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 179 ms. Remains : 306/306 places, 8064/8064 transitions.
[2023-03-19 01:47:09] [INFO ] Flatten gal took : 152 ms
[2023-03-19 01:47:09] [INFO ] Flatten gal took : 174 ms
[2023-03-19 01:47:10] [INFO ] Input system was already deterministic with 8064 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 305 transition count 7936
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 7936
Applied a total of 2 rules in 210 ms. Remains 305 /306 variables (removed 1) and now considering 7936/8064 (removed 128) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 212 ms. Remains : 305/306 places, 7936/8064 transitions.
[2023-03-19 01:47:10] [INFO ] Flatten gal took : 150 ms
[2023-03-19 01:47:10] [INFO ] Flatten gal took : 173 ms
[2023-03-19 01:47:10] [INFO ] Input system was already deterministic with 7936 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 305 transition count 7936
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 7936
Applied a total of 2 rules in 201 ms. Remains 305 /306 variables (removed 1) and now considering 7936/8064 (removed 128) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 201 ms. Remains : 305/306 places, 7936/8064 transitions.
[2023-03-19 01:47:11] [INFO ] Flatten gal took : 150 ms
[2023-03-19 01:47:11] [INFO ] Flatten gal took : 171 ms
[2023-03-19 01:47:11] [INFO ] Input system was already deterministic with 7936 transitions.
Starting structural reductions in LTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 305 transition count 7936
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 7936
Applied a total of 2 rules in 42 ms. Remains 305 /306 variables (removed 1) and now considering 7936/8064 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 43 ms. Remains : 305/306 places, 7936/8064 transitions.
[2023-03-19 01:47:11] [INFO ] Flatten gal took : 163 ms
[2023-03-19 01:47:12] [INFO ] Flatten gal took : 176 ms
[2023-03-19 01:47:12] [INFO ] Input system was already deterministic with 7936 transitions.
Starting structural reductions in LTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 305 transition count 7936
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 7936
Applied a total of 2 rules in 44 ms. Remains 305 /306 variables (removed 1) and now considering 7936/8064 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 44 ms. Remains : 305/306 places, 7936/8064 transitions.
[2023-03-19 01:47:12] [INFO ] Flatten gal took : 149 ms
[2023-03-19 01:47:12] [INFO ] Flatten gal took : 173 ms
[2023-03-19 01:47:13] [INFO ] Input system was already deterministic with 7936 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 305 transition count 7936
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 7936
Applied a total of 2 rules in 201 ms. Remains 305 /306 variables (removed 1) and now considering 7936/8064 (removed 128) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 201 ms. Remains : 305/306 places, 7936/8064 transitions.
[2023-03-19 01:47:13] [INFO ] Flatten gal took : 153 ms
[2023-03-19 01:47:13] [INFO ] Flatten gal took : 176 ms
[2023-03-19 01:47:14] [INFO ] Input system was already deterministic with 7936 transitions.
Starting structural reductions in LTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 305 transition count 7936
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 7936
Applied a total of 2 rules in 40 ms. Remains 305 /306 variables (removed 1) and now considering 7936/8064 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 40 ms. Remains : 305/306 places, 7936/8064 transitions.
[2023-03-19 01:47:14] [INFO ] Flatten gal took : 152 ms
[2023-03-19 01:47:14] [INFO ] Flatten gal took : 173 ms
[2023-03-19 01:47:14] [INFO ] Input system was already deterministic with 7936 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 305 transition count 7936
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 7936
Applied a total of 2 rules in 221 ms. Remains 305 /306 variables (removed 1) and now considering 7936/8064 (removed 128) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 221 ms. Remains : 305/306 places, 7936/8064 transitions.
[2023-03-19 01:47:15] [INFO ] Flatten gal took : 155 ms
[2023-03-19 01:47:15] [INFO ] Flatten gal took : 175 ms
[2023-03-19 01:47:15] [INFO ] Input system was already deterministic with 7936 transitions.
Starting structural reductions in LTL mode, iteration 0 : 306/306 places, 8064/8064 transitions.
Applied a total of 0 rules in 22 ms. Remains 306 /306 variables (removed 0) and now considering 8064/8064 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 306/306 places, 8064/8064 transitions.
[2023-03-19 01:47:15] [INFO ] Flatten gal took : 151 ms
[2023-03-19 01:47:15] [INFO ] Flatten gal took : 178 ms
[2023-03-19 01:47:16] [INFO ] Input system was already deterministic with 8064 transitions.
[2023-03-19 01:47:16] [INFO ] Flatten gal took : 178 ms
[2023-03-19 01:47:16] [INFO ] Flatten gal took : 184 ms
[2023-03-19 01:47:16] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 01:47:16] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 306 places, 8064 transitions and 32128 arcs took 32 ms.
Total runtime 251562 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Szymanski-PT-b04
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA Szymanski-PT-b04-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b04-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b04-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b04-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b04-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 7550296 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16091280 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 0 0 0 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 0 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 8 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 13 (type EXCL) for 12 Szymanski-PT-b04-CTLFireability-04
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 13 (type EXCL) for Szymanski-PT-b04-CTLFireability-04
lola: result : false
lola: markings : 33
lola: fired transitions : 99
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 Szymanski-PT-b04-CTLFireability-02
lola: time limit : 256 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 1 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 0/256 1/32 Szymanski-PT-b04-CTLFireability-02 11568 m, 2313 m/sec, 30903 t fired, .
Time elapsed: 13 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 14
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 48 (type FNDP) for 0 Szymanski-PT-b04-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 0 Szymanski-PT-b04-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 0 Szymanski-PT-b04-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
sara: try reading problem file /home/mcc/execution/374/CTLFireability-49.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:663
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 51 (type SRCH) for Szymanski-PT-b04-CTLFireability-00
lola: result : unknown
lola: markings : 717
lola: fired transitions : 1258
lola: time used : 1.000000
lola: memory pages used : 1
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/256 2/32 Szymanski-PT-b04-CTLFireability-02 177000 m, 33086 m/sec, 870993 t fired, .
48 EF FNDP 4/3586 0/5 Szymanski-PT-b04-CTLFireability-00 4397 t fired, 17 attempts, .
49 EF STEQ 4/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 18 secs. Pages in use: 2
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/256 3/32 Szymanski-PT-b04-CTLFireability-02 391823 m, 42964 m/sec, 1753087 t fired, .
48 EF FNDP 9/3586 0/5 Szymanski-PT-b04-CTLFireability-00 9830 t fired, 35 attempts, .
49 EF STEQ 9/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 23 secs. Pages in use: 3
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/256 4/32 Szymanski-PT-b04-CTLFireability-02 623243 m, 46284 m/sec, 2598280 t fired, .
48 EF FNDP 14/3586 0/5 Szymanski-PT-b04-CTLFireability-00 15268 t fired, 55 attempts, .
49 EF STEQ 14/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 28 secs. Pages in use: 4
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/256 6/32 Szymanski-PT-b04-CTLFireability-02 851851 m, 45721 m/sec, 3427932 t fired, .
48 EF FNDP 19/3586 0/5 Szymanski-PT-b04-CTLFireability-00 20710 t fired, 76 attempts, .
49 EF STEQ 19/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 33 secs. Pages in use: 6
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/256 7/32 Szymanski-PT-b04-CTLFireability-02 1021792 m, 33988 m/sec, 4326484 t fired, .
48 EF FNDP 24/3586 0/5 Szymanski-PT-b04-CTLFireability-00 26160 t fired, 97 attempts, .
49 EF STEQ 24/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 38 secs. Pages in use: 7
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/256 8/32 Szymanski-PT-b04-CTLFireability-02 1238218 m, 43285 m/sec, 5174375 t fired, .
48 EF FNDP 29/3586 0/5 Szymanski-PT-b04-CTLFireability-00 31635 t fired, 119 attempts, .
49 EF STEQ 29/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 43 secs. Pages in use: 8
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/256 9/32 Szymanski-PT-b04-CTLFireability-02 1404097 m, 33175 m/sec, 6075360 t fired, .
48 EF FNDP 34/3586 0/5 Szymanski-PT-b04-CTLFireability-00 37124 t fired, 140 attempts, .
49 EF STEQ 34/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 48 secs. Pages in use: 9
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/256 10/32 Szymanski-PT-b04-CTLFireability-02 1622105 m, 43601 m/sec, 6895820 t fired, .
48 EF FNDP 39/3586 0/5 Szymanski-PT-b04-CTLFireability-00 42598 t fired, 163 attempts, .
49 EF STEQ 39/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 53 secs. Pages in use: 10
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/256 11/32 Szymanski-PT-b04-CTLFireability-02 1811192 m, 37817 m/sec, 7751089 t fired, .
48 EF FNDP 44/3586 0/5 Szymanski-PT-b04-CTLFireability-00 48047 t fired, 183 attempts, .
49 EF STEQ 44/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 58 secs. Pages in use: 11
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/256 12/32 Szymanski-PT-b04-CTLFireability-02 1992914 m, 36344 m/sec, 8621059 t fired, .
48 EF FNDP 49/3586 0/5 Szymanski-PT-b04-CTLFireability-00 53505 t fired, 201 attempts, .
49 EF STEQ 49/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 63 secs. Pages in use: 12
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 55/256 13/32 Szymanski-PT-b04-CTLFireability-02 2201651 m, 41747 m/sec, 9444418 t fired, .
48 EF FNDP 54/3586 0/5 Szymanski-PT-b04-CTLFireability-00 58964 t fired, 221 attempts, .
49 EF STEQ 54/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 68 secs. Pages in use: 13
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 60/256 15/32 Szymanski-PT-b04-CTLFireability-02 2392172 m, 38104 m/sec, 10284179 t fired, .
48 EF FNDP 59/3586 0/5 Szymanski-PT-b04-CTLFireability-00 64467 t fired, 240 attempts, .
49 EF STEQ 59/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 73 secs. Pages in use: 15
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 65/256 16/32 Szymanski-PT-b04-CTLFireability-02 2589752 m, 39516 m/sec, 11125080 t fired, .
48 EF FNDP 64/3586 0/5 Szymanski-PT-b04-CTLFireability-00 69962 t fired, 262 attempts, .
49 EF STEQ 64/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 78 secs. Pages in use: 16
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 70/256 17/32 Szymanski-PT-b04-CTLFireability-02 2808562 m, 43762 m/sec, 11917258 t fired, .
48 EF FNDP 69/3586 0/5 Szymanski-PT-b04-CTLFireability-00 75451 t fired, 281 attempts, .
49 EF STEQ 69/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 83 secs. Pages in use: 17
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 75/256 18/32 Szymanski-PT-b04-CTLFireability-02 3021918 m, 42671 m/sec, 12708652 t fired, .
48 EF FNDP 74/3586 0/5 Szymanski-PT-b04-CTLFireability-00 80943 t fired, 303 attempts, .
49 EF STEQ 74/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 88 secs. Pages in use: 18
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 80/256 19/32 Szymanski-PT-b04-CTLFireability-02 3206512 m, 36918 m/sec, 13538412 t fired, .
48 EF FNDP 79/3586 0/5 Szymanski-PT-b04-CTLFireability-00 86445 t fired, 324 attempts, .
49 EF STEQ 79/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 93 secs. Pages in use: 19
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 85/256 20/32 Szymanski-PT-b04-CTLFireability-02 3401230 m, 38943 m/sec, 14360591 t fired, .
48 EF FNDP 84/3586 0/5 Szymanski-PT-b04-CTLFireability-00 91926 t fired, 345 attempts, .
49 EF STEQ 84/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 98 secs. Pages in use: 20
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 90/256 22/32 Szymanski-PT-b04-CTLFireability-02 3610823 m, 41918 m/sec, 15136972 t fired, .
48 EF FNDP 89/3586 0/5 Szymanski-PT-b04-CTLFireability-00 97437 t fired, 366 attempts, .
49 EF STEQ 89/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 103 secs. Pages in use: 22
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 95/256 23/32 Szymanski-PT-b04-CTLFireability-02 3821323 m, 42100 m/sec, 15915167 t fired, .
48 EF FNDP 94/3586 0/5 Szymanski-PT-b04-CTLFireability-00 102964 t fired, 385 attempts, .
49 EF STEQ 94/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 108 secs. Pages in use: 23
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 100/256 24/32 Szymanski-PT-b04-CTLFireability-02 4012884 m, 38312 m/sec, 16722056 t fired, .
48 EF FNDP 99/3586 0/5 Szymanski-PT-b04-CTLFireability-00 108459 t fired, 408 attempts, .
49 EF STEQ 99/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 113 secs. Pages in use: 24
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 105/256 25/32 Szymanski-PT-b04-CTLFireability-02 4131979 m, 23819 m/sec, 17648822 t fired, .
48 EF FNDP 104/3586 0/5 Szymanski-PT-b04-CTLFireability-00 113945 t fired, 426 attempts, .
49 EF STEQ 104/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 118 secs. Pages in use: 25
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 110/256 26/32 Szymanski-PT-b04-CTLFireability-02 4329966 m, 39597 m/sec, 18432791 t fired, .
48 EF FNDP 109/3586 0/5 Szymanski-PT-b04-CTLFireability-00 119433 t fired, 444 attempts, .
49 EF STEQ 109/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 123 secs. Pages in use: 26
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 115/256 27/32 Szymanski-PT-b04-CTLFireability-02 4527329 m, 39472 m/sec, 19209333 t fired, .
48 EF FNDP 114/3586 0/5 Szymanski-PT-b04-CTLFireability-00 124927 t fired, 466 attempts, .
49 EF STEQ 114/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 128 secs. Pages in use: 27
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 120/256 28/32 Szymanski-PT-b04-CTLFireability-02 4668828 m, 28299 m/sec, 20087830 t fired, .
48 EF FNDP 119/3586 0/5 Szymanski-PT-b04-CTLFireability-00 130408 t fired, 486 attempts, .
49 EF STEQ 119/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 133 secs. Pages in use: 28
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 125/256 28/32 Szymanski-PT-b04-CTLFireability-02 4796813 m, 25597 m/sec, 20994733 t fired, .
48 EF FNDP 124/3586 0/5 Szymanski-PT-b04-CTLFireability-00 135930 t fired, 505 attempts, .
49 EF STEQ 124/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 138 secs. Pages in use: 28
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 130/256 29/32 Szymanski-PT-b04-CTLFireability-02 4964516 m, 33540 m/sec, 21835700 t fired, .
48 EF FNDP 129/3586 0/5 Szymanski-PT-b04-CTLFireability-00 141389 t fired, 527 attempts, .
49 EF STEQ 129/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 143 secs. Pages in use: 29
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 135/256 30/32 Szymanski-PT-b04-CTLFireability-02 5159231 m, 38943 m/sec, 22615753 t fired, .
48 EF FNDP 134/3586 0/5 Szymanski-PT-b04-CTLFireability-00 146899 t fired, 544 attempts, .
49 EF STEQ 134/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 148 secs. Pages in use: 30
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 140/256 31/32 Szymanski-PT-b04-CTLFireability-02 5346123 m, 37378 m/sec, 23398596 t fired, .
48 EF FNDP 139/3586 0/5 Szymanski-PT-b04-CTLFireability-00 152345 t fired, 564 attempts, .
49 EF STEQ 139/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 153 secs. Pages in use: 31
# running tasks: 3 of 4 Visible: 14
lola: CANCELED task # 7 (type EXCL) for Szymanski-PT-b04-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 144/3586 0/5 Szymanski-PT-b04-CTLFireability-00 157822 t fired, 587 attempts, .
49 EF STEQ 144/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 158 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: LAUNCH task # 44 (type EXCL) for 43 Szymanski-PT-b04-CTLFireability-15
lola: time limit : 264 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for Szymanski-PT-b04-CTLFireability-15
lola: result : false
lola: markings : 33
lola: fired transitions : 267
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 Szymanski-PT-b04-CTLFireability-13
lola: time limit : 286 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/286 2/32 Szymanski-PT-b04-CTLFireability-13 253851 m, 50770 m/sec, 791246 t fired, .
48 EF FNDP 149/3586 0/5 Szymanski-PT-b04-CTLFireability-00 163290 t fired, 607 attempts, .
49 EF STEQ 149/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 163 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 10/286 4/32 Szymanski-PT-b04-CTLFireability-13 506600 m, 50549 m/sec, 1553162 t fired, .
48 EF FNDP 154/3586 0/5 Szymanski-PT-b04-CTLFireability-00 168808 t fired, 624 attempts, .
49 EF STEQ 154/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 168 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 15/286 5/32 Szymanski-PT-b04-CTLFireability-13 746178 m, 47915 m/sec, 2307421 t fired, .
48 EF FNDP 159/3586 0/5 Szymanski-PT-b04-CTLFireability-00 174312 t fired, 643 attempts, .
49 EF STEQ 159/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 173 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 20/286 6/32 Szymanski-PT-b04-CTLFireability-13 982507 m, 47265 m/sec, 3022657 t fired, .
48 EF FNDP 164/3586 0/5 Szymanski-PT-b04-CTLFireability-00 179846 t fired, 667 attempts, .
49 EF STEQ 164/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 178 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 25/286 8/32 Szymanski-PT-b04-CTLFireability-13 1230651 m, 49628 m/sec, 3664901 t fired, .
48 EF FNDP 169/3586 0/5 Szymanski-PT-b04-CTLFireability-00 185364 t fired, 686 attempts, .
49 EF STEQ 169/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 183 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 30/286 9/32 Szymanski-PT-b04-CTLFireability-13 1481706 m, 50211 m/sec, 4311683 t fired, .
48 EF FNDP 174/3586 0/5 Szymanski-PT-b04-CTLFireability-00 190911 t fired, 703 attempts, .
49 EF STEQ 174/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 188 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 35/286 11/32 Szymanski-PT-b04-CTLFireability-13 1713574 m, 46373 m/sec, 5047637 t fired, .
48 EF FNDP 179/3586 0/5 Szymanski-PT-b04-CTLFireability-00 196394 t fired, 725 attempts, .
49 EF STEQ 179/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 193 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 40/286 12/32 Szymanski-PT-b04-CTLFireability-13 1951820 m, 47649 m/sec, 5785407 t fired, .
48 EF FNDP 184/3586 0/5 Szymanski-PT-b04-CTLFireability-00 201869 t fired, 745 attempts, .
49 EF STEQ 184/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 198 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 45/286 13/32 Szymanski-PT-b04-CTLFireability-13 2186532 m, 46942 m/sec, 6518186 t fired, .
48 EF FNDP 189/3586 0/5 Szymanski-PT-b04-CTLFireability-00 207335 t fired, 767 attempts, .
49 EF STEQ 189/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 203 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 50/286 15/32 Szymanski-PT-b04-CTLFireability-13 2443443 m, 51382 m/sec, 7135522 t fired, .
48 EF FNDP 194/3586 0/5 Szymanski-PT-b04-CTLFireability-00 212838 t fired, 787 attempts, .
49 EF STEQ 194/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 208 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 55/286 16/32 Szymanski-PT-b04-CTLFireability-13 2700098 m, 51331 m/sec, 7736915 t fired, .
48 EF FNDP 199/3586 0/5 Szymanski-PT-b04-CTLFireability-00 218372 t fired, 809 attempts, .
49 EF STEQ 199/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 213 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 60/286 18/32 Szymanski-PT-b04-CTLFireability-13 2923649 m, 44710 m/sec, 8486481 t fired, .
48 EF FNDP 204/3586 0/5 Szymanski-PT-b04-CTLFireability-00 223874 t fired, 829 attempts, .
49 EF STEQ 204/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 218 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 65/286 19/32 Szymanski-PT-b04-CTLFireability-13 3164581 m, 48186 m/sec, 9151136 t fired, .
48 EF FNDP 209/3586 0/5 Szymanski-PT-b04-CTLFireability-00 229363 t fired, 846 attempts, .
49 EF STEQ 209/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 223 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 70/286 20/32 Szymanski-PT-b04-CTLFireability-13 3400502 m, 47184 m/sec, 9754844 t fired, .
48 EF FNDP 214/3586 0/5 Szymanski-PT-b04-CTLFireability-00 234826 t fired, 866 attempts, .
49 EF STEQ 214/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 228 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 75/286 22/32 Szymanski-PT-b04-CTLFireability-13 3649846 m, 49868 m/sec, 10431499 t fired, .
48 EF FNDP 219/3586 0/5 Szymanski-PT-b04-CTLFireability-00 240320 t fired, 888 attempts, .
49 EF STEQ 219/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 233 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 80/286 23/32 Szymanski-PT-b04-CTLFireability-13 3887317 m, 47494 m/sec, 11082060 t fired, .
48 EF FNDP 224/3586 0/5 Szymanski-PT-b04-CTLFireability-00 245801 t fired, 908 attempts, .
49 EF STEQ 224/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 238 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 85/286 25/32 Szymanski-PT-b04-CTLFireability-13 4137299 m, 49996 m/sec, 11687364 t fired, .
48 EF FNDP 229/3586 0/5 Szymanski-PT-b04-CTLFireability-00 251299 t fired, 925 attempts, .
49 EF STEQ 229/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 243 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 90/286 26/32 Szymanski-PT-b04-CTLFireability-13 4381504 m, 48841 m/sec, 12334434 t fired, .
48 EF FNDP 234/3586 0/5 Szymanski-PT-b04-CTLFireability-00 256802 t fired, 947 attempts, .
49 EF STEQ 234/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 248 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 95/286 27/32 Szymanski-PT-b04-CTLFireability-13 4634984 m, 50696 m/sec, 12926045 t fired, .
48 EF FNDP 239/3586 0/5 Szymanski-PT-b04-CTLFireability-00 262319 t fired, 966 attempts, .
49 EF STEQ 239/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 253 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 100/286 29/32 Szymanski-PT-b04-CTLFireability-13 4873151 m, 47633 m/sec, 13578818 t fired, .
48 EF FNDP 244/3586 0/5 Szymanski-PT-b04-CTLFireability-00 267797 t fired, 985 attempts, .
49 EF STEQ 244/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 258 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 105/286 30/32 Szymanski-PT-b04-CTLFireability-13 5123150 m, 49999 m/sec, 14181317 t fired, .
48 EF FNDP 249/3586 0/5 Szymanski-PT-b04-CTLFireability-00 273302 t fired, 1007 attempts, .
49 EF STEQ 249/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 263 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 110/286 31/32 Szymanski-PT-b04-CTLFireability-13 5355516 m, 46473 m/sec, 14846608 t fired, .
48 EF FNDP 254/3586 0/5 Szymanski-PT-b04-CTLFireability-00 278795 t fired, 1029 attempts, .
49 EF STEQ 254/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 268 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: CANCELED task # 38 (type EXCL) for Szymanski-PT-b04-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 259/3586 0/5 Szymanski-PT-b04-CTLFireability-00 284316 t fired, 1051 attempts, .
49 EF STEQ 259/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 273 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: LAUNCH task # 32 (type EXCL) for 31 Szymanski-PT-b04-CTLFireability-09
lola: time limit : 302 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/302 1/32 Szymanski-PT-b04-CTLFireability-09 96461 m, 19292 m/sec, 627346 t fired, .
48 EF FNDP 264/3586 0/5 Szymanski-PT-b04-CTLFireability-00 289804 t fired, 1068 attempts, .
49 EF STEQ 264/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 278 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/302 2/32 Szymanski-PT-b04-CTLFireability-09 190830 m, 18873 m/sec, 1230124 t fired, .
48 EF FNDP 269/3586 0/5 Szymanski-PT-b04-CTLFireability-00 295282 t fired, 1089 attempts, .
49 EF STEQ 269/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 283 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 15/302 2/32 Szymanski-PT-b04-CTLFireability-09 284634 m, 18760 m/sec, 1779099 t fired, .
48 EF FNDP 274/3586 0/5 Szymanski-PT-b04-CTLFireability-00 300762 t fired, 1112 attempts, .
49 EF STEQ 274/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 288 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 20/302 3/32 Szymanski-PT-b04-CTLFireability-09 383605 m, 19794 m/sec, 2355012 t fired, .
48 EF FNDP 279/3586 0/5 Szymanski-PT-b04-CTLFireability-00 305458 t fired, 1131 attempts, .
49 EF STEQ 279/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 293 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 25/302 3/32 Szymanski-PT-b04-CTLFireability-09 476639 m, 18606 m/sec, 3014091 t fired, .
48 EF FNDP 284/3586 0/5 Szymanski-PT-b04-CTLFireability-00 310932 t fired, 1150 attempts, .
49 EF STEQ 284/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 298 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 30/302 4/32 Szymanski-PT-b04-CTLFireability-09 566256 m, 17923 m/sec, 3628620 t fired, .
48 EF FNDP 289/3586 0/5 Szymanski-PT-b04-CTLFireability-00 316434 t fired, 1168 attempts, .
49 EF STEQ 289/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 303 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 35/302 4/32 Szymanski-PT-b04-CTLFireability-09 660913 m, 18931 m/sec, 4235172 t fired, .
48 EF FNDP 294/3586 0/5 Szymanski-PT-b04-CTLFireability-00 321941 t fired, 1189 attempts, .
49 EF STEQ 294/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 308 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 40/302 5/32 Szymanski-PT-b04-CTLFireability-09 753075 m, 18432 m/sec, 4855598 t fired, .
48 EF FNDP 299/3586 0/5 Szymanski-PT-b04-CTLFireability-00 327473 t fired, 1208 attempts, .
49 EF STEQ 299/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 313 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 45/302 6/32 Szymanski-PT-b04-CTLFireability-09 842914 m, 17967 m/sec, 5476263 t fired, .
48 EF FNDP 304/3586 0/5 Szymanski-PT-b04-CTLFireability-00 333012 t fired, 1231 attempts, .
49 EF STEQ 304/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 318 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 50/302 6/32 Szymanski-PT-b04-CTLFireability-09 936512 m, 18719 m/sec, 6063453 t fired, .
48 EF FNDP 309/3586 0/5 Szymanski-PT-b04-CTLFireability-00 338523 t fired, 1250 attempts, .
49 EF STEQ 309/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 323 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 55/302 7/32 Szymanski-PT-b04-CTLFireability-09 1029984 m, 18694 m/sec, 6650694 t fired, .
48 EF FNDP 314/3586 0/5 Szymanski-PT-b04-CTLFireability-00 344071 t fired, 1272 attempts, .
49 EF STEQ 314/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 328 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 60/302 7/32 Szymanski-PT-b04-CTLFireability-09 1121486 m, 18300 m/sec, 7251834 t fired, .
48 EF FNDP 319/3586 0/5 Szymanski-PT-b04-CTLFireability-00 349631 t fired, 1290 attempts, .
49 EF STEQ 319/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 333 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 65/302 8/32 Szymanski-PT-b04-CTLFireability-09 1216829 m, 19068 m/sec, 7803385 t fired, .
48 EF FNDP 324/3586 0/5 Szymanski-PT-b04-CTLFireability-00 355176 t fired, 1313 attempts, .
49 EF STEQ 324/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 338 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 70/302 8/32 Szymanski-PT-b04-CTLFireability-09 1311977 m, 19029 m/sec, 8390552 t fired, .
48 EF FNDP 329/3586 0/5 Szymanski-PT-b04-CTLFireability-00 360720 t fired, 1334 attempts, .
49 EF STEQ 329/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 343 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 75/302 9/32 Szymanski-PT-b04-CTLFireability-09 1405282 m, 18661 m/sec, 8973091 t fired, .
48 EF FNDP 334/3586 0/5 Szymanski-PT-b04-CTLFireability-00 366225 t fired, 1357 attempts, .
49 EF STEQ 334/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 348 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 80/302 9/32 Szymanski-PT-b04-CTLFireability-09 1500897 m, 19123 m/sec, 9515657 t fired, .
48 EF FNDP 339/3586 0/5 Szymanski-PT-b04-CTLFireability-00 371750 t fired, 1374 attempts, .
49 EF STEQ 339/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 353 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 85/302 10/32 Szymanski-PT-b04-CTLFireability-09 1595474 m, 18915 m/sec, 10071569 t fired, .
48 EF FNDP 344/3586 0/5 Szymanski-PT-b04-CTLFireability-00 377292 t fired, 1391 attempts, .
49 EF STEQ 344/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 358 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 90/302 10/32 Szymanski-PT-b04-CTLFireability-09 1679861 m, 16877 m/sec, 10767478 t fired, .
48 EF FNDP 349/3586 0/5 Szymanski-PT-b04-CTLFireability-00 382788 t fired, 1411 attempts, .
49 EF STEQ 349/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 363 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 95/302 11/32 Szymanski-PT-b04-CTLFireability-09 1774335 m, 18894 m/sec, 11320239 t fired, .
48 EF FNDP 354/3586 0/5 Szymanski-PT-b04-CTLFireability-00 388282 t fired, 1432 attempts, .
49 EF STEQ 354/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 368 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 100/302 12/32 Szymanski-PT-b04-CTLFireability-09 1867971 m, 18727 m/sec, 11874801 t fired, .
48 EF FNDP 359/3586 0/5 Szymanski-PT-b04-CTLFireability-00 393796 t fired, 1452 attempts, .
49 EF STEQ 359/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 373 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 105/302 12/32 Szymanski-PT-b04-CTLFireability-09 1954409 m, 17287 m/sec, 12580218 t fired, .
48 EF FNDP 364/3586 0/5 Szymanski-PT-b04-CTLFireability-00 399341 t fired, 1470 attempts, .
49 EF STEQ 364/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 378 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 110/302 12/32 Szymanski-PT-b04-CTLFireability-09 2041706 m, 17459 m/sec, 13249115 t fired, .
48 EF FNDP 369/3586 0/5 Szymanski-PT-b04-CTLFireability-00 404899 t fired, 1487 attempts, .
49 EF STEQ 369/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 383 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 115/302 13/32 Szymanski-PT-b04-CTLFireability-09 2134654 m, 18589 m/sec, 13820090 t fired, .
48 EF FNDP 374/3586 0/5 Szymanski-PT-b04-CTLFireability-00 410424 t fired, 1509 attempts, .
49 EF STEQ 374/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 388 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 120/302 14/32 Szymanski-PT-b04-CTLFireability-09 2226810 m, 18431 m/sec, 14365964 t fired, .
48 EF FNDP 379/3586 0/5 Szymanski-PT-b04-CTLFireability-00 415975 t fired, 1530 attempts, .
49 EF STEQ 379/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 393 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 125/302 14/32 Szymanski-PT-b04-CTLFireability-09 2318223 m, 18282 m/sec, 14916933 t fired, .
48 EF FNDP 384/3586 0/5 Szymanski-PT-b04-CTLFireability-00 421533 t fired, 1547 attempts, .
49 EF STEQ 384/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 398 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 130/302 15/32 Szymanski-PT-b04-CTLFireability-09 2412665 m, 18888 m/sec, 15466965 t fired, .
48 EF FNDP 389/3586 0/5 Szymanski-PT-b04-CTLFireability-00 427094 t fired, 1570 attempts, .
49 EF STEQ 389/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 403 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 135/302 15/32 Szymanski-PT-b04-CTLFireability-09 2507229 m, 18912 m/sec, 16024032 t fired, .
48 EF FNDP 394/3586 0/5 Szymanski-PT-b04-CTLFireability-00 431667 t fired, 1588 attempts, .
49 EF STEQ 394/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 408 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 140/302 16/32 Szymanski-PT-b04-CTLFireability-09 2600724 m, 18699 m/sec, 16570947 t fired, .
48 EF FNDP 399/3586 0/5 Szymanski-PT-b04-CTLFireability-00 434629 t fired, 1596 attempts, .
49 EF STEQ 399/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 413 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 145/302 16/32 Szymanski-PT-b04-CTLFireability-09 2693473 m, 18549 m/sec, 17119994 t fired, .
48 EF FNDP 404/3586 0/5 Szymanski-PT-b04-CTLFireability-00 440173 t fired, 1614 attempts, .
49 EF STEQ 404/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 418 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 150/302 17/32 Szymanski-PT-b04-CTLFireability-09 2775222 m, 16349 m/sec, 17795110 t fired, .
48 EF FNDP 409/3586 0/5 Szymanski-PT-b04-CTLFireability-00 445723 t fired, 1635 attempts, .
49 EF STEQ 409/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 423 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 155/302 17/32 Szymanski-PT-b04-CTLFireability-09 2862589 m, 17473 m/sec, 18380839 t fired, .
48 EF FNDP 414/3586 0/5 Szymanski-PT-b04-CTLFireability-00 451270 t fired, 1658 attempts, .
49 EF STEQ 414/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 428 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 160/302 18/32 Szymanski-PT-b04-CTLFireability-09 2954914 m, 18465 m/sec, 18932057 t fired, .
48 EF FNDP 419/3586 0/5 Szymanski-PT-b04-CTLFireability-00 456810 t fired, 1679 attempts, .
49 EF STEQ 419/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 433 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 165/302 18/32 Szymanski-PT-b04-CTLFireability-09 3040243 m, 17065 m/sec, 19550028 t fired, .
48 EF FNDP 424/3586 0/5 Szymanski-PT-b04-CTLFireability-00 462357 t fired, 1700 attempts, .
49 EF STEQ 424/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 438 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 170/302 19/32 Szymanski-PT-b04-CTLFireability-09 3133826 m, 18716 m/sec, 20093630 t fired, .
48 EF FNDP 429/3586 0/5 Szymanski-PT-b04-CTLFireability-00 467857 t fired, 1721 attempts, .
49 EF STEQ 429/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 443 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 175/302 19/32 Szymanski-PT-b04-CTLFireability-09 3226179 m, 18470 m/sec, 20638869 t fired, .
48 EF FNDP 434/3586 0/5 Szymanski-PT-b04-CTLFireability-00 473382 t fired, 1739 attempts, .
49 EF STEQ 434/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 448 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 180/302 20/32 Szymanski-PT-b04-CTLFireability-09 3317327 m, 18229 m/sec, 21193664 t fired, .
48 EF FNDP 439/3586 0/5 Szymanski-PT-b04-CTLFireability-00 478946 t fired, 1761 attempts, .
49 EF STEQ 439/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 453 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 185/302 20/32 Szymanski-PT-b04-CTLFireability-09 3409853 m, 18505 m/sec, 21778962 t fired, .
48 EF FNDP 444/3586 0/5 Szymanski-PT-b04-CTLFireability-00 484502 t fired, 1775 attempts, .
49 EF STEQ 444/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 458 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 190/302 21/32 Szymanski-PT-b04-CTLFireability-09 3507742 m, 19577 m/sec, 22369651 t fired, .
48 EF FNDP 449/3586 0/5 Szymanski-PT-b04-CTLFireability-00 490059 t fired, 1797 attempts, .
49 EF STEQ 449/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 463 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 195/302 21/32 Szymanski-PT-b04-CTLFireability-09 3603399 m, 19131 m/sec, 22954412 t fired, .
48 EF FNDP 454/3586 0/5 Szymanski-PT-b04-CTLFireability-00 495630 t fired, 1815 attempts, .
49 EF STEQ 454/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 468 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 200/302 22/32 Szymanski-PT-b04-CTLFireability-09 3694735 m, 18267 m/sec, 23525834 t fired, .
48 EF FNDP 459/3586 0/5 Szymanski-PT-b04-CTLFireability-00 501228 t fired, 1832 attempts, .
49 EF STEQ 459/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 473 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 205/302 23/32 Szymanski-PT-b04-CTLFireability-09 3788376 m, 18728 m/sec, 24071217 t fired, .
48 EF FNDP 464/3586 0/5 Szymanski-PT-b04-CTLFireability-00 506784 t fired, 1850 attempts, .
49 EF STEQ 464/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 478 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 210/302 23/32 Szymanski-PT-b04-CTLFireability-09 3876667 m, 17658 m/sec, 24671465 t fired, .
48 EF FNDP 469/3586 0/5 Szymanski-PT-b04-CTLFireability-00 512371 t fired, 1870 attempts, .
49 EF STEQ 469/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 483 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 215/302 24/32 Szymanski-PT-b04-CTLFireability-09 3968722 m, 18411 m/sec, 25215432 t fired, .
48 EF FNDP 474/3586 0/5 Szymanski-PT-b04-CTLFireability-00 517940 t fired, 1889 attempts, .
49 EF STEQ 474/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 488 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 220/302 24/32 Szymanski-PT-b04-CTLFireability-09 4062686 m, 18792 m/sec, 25773463 t fired, .
48 EF FNDP 479/3586 0/5 Szymanski-PT-b04-CTLFireability-00 523507 t fired, 1909 attempts, .
49 EF STEQ 479/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 493 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 225/302 25/32 Szymanski-PT-b04-CTLFireability-09 4153016 m, 18066 m/sec, 26342515 t fired, .
48 EF FNDP 484/3586 0/5 Szymanski-PT-b04-CTLFireability-00 529064 t fired, 1930 attempts, .
49 EF STEQ 484/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 498 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 230/302 25/32 Szymanski-PT-b04-CTLFireability-09 4242861 m, 17969 m/sec, 26957409 t fired, .
48 EF FNDP 489/3586 0/5 Szymanski-PT-b04-CTLFireability-00 534637 t fired, 1950 attempts, .
49 EF STEQ 489/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 503 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 235/302 26/32 Szymanski-PT-b04-CTLFireability-09 4336061 m, 18640 m/sec, 27507056 t fired, .
48 EF FNDP 494/3586 0/5 Szymanski-PT-b04-CTLFireability-00 540233 t fired, 1969 attempts, .
49 EF STEQ 494/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 508 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 240/302 26/32 Szymanski-PT-b04-CTLFireability-09 4428862 m, 18560 m/sec, 28051203 t fired, .
48 EF FNDP 499/3586 0/5 Szymanski-PT-b04-CTLFireability-00 545779 t fired, 1992 attempts, .
49 EF STEQ 499/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 513 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 245/302 27/32 Szymanski-PT-b04-CTLFireability-09 4522102 m, 18648 m/sec, 28594653 t fired, .
48 EF FNDP 504/3586 0/5 Szymanski-PT-b04-CTLFireability-00 551318 t fired, 2011 attempts, .
49 EF STEQ 504/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 518 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 250/302 27/32 Szymanski-PT-b04-CTLFireability-09 4615731 m, 18725 m/sec, 29161154 t fired, .
48 EF FNDP 509/3586 0/5 Szymanski-PT-b04-CTLFireability-00 556894 t fired, 2029 attempts, .
49 EF STEQ 509/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 523 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 255/302 28/32 Szymanski-PT-b04-CTLFireability-09 4709450 m, 18743 m/sec, 29708535 t fired, .
48 EF FNDP 514/3586 0/5 Szymanski-PT-b04-CTLFireability-00 562448 t fired, 2045 attempts, .
49 EF STEQ 514/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 528 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 260/302 28/32 Szymanski-PT-b04-CTLFireability-09 4802673 m, 18644 m/sec, 30258366 t fired, .
48 EF FNDP 519/3586 0/5 Szymanski-PT-b04-CTLFireability-00 568023 t fired, 2063 attempts, .
49 EF STEQ 519/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 533 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 265/302 29/32 Szymanski-PT-b04-CTLFireability-09 4889405 m, 17346 m/sec, 30880265 t fired, .
48 EF FNDP 524/3586 0/5 Szymanski-PT-b04-CTLFireability-00 573625 t fired, 2081 attempts, .
49 EF STEQ 524/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 538 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 270/302 29/32 Szymanski-PT-b04-CTLFireability-09 4982260 m, 18571 m/sec, 31425364 t fired, .
48 EF FNDP 529/3586 0/5 Szymanski-PT-b04-CTLFireability-00 579203 t fired, 2101 attempts, .
49 EF STEQ 529/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 543 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 275/302 30/32 Szymanski-PT-b04-CTLFireability-09 5075446 m, 18637 m/sec, 31995211 t fired, .
48 EF FNDP 534/3586 0/5 Szymanski-PT-b04-CTLFireability-00 584776 t fired, 2122 attempts, .
49 EF STEQ 534/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 548 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 280/302 30/32 Szymanski-PT-b04-CTLFireability-09 5161406 m, 17192 m/sec, 32625264 t fired, .
48 EF FNDP 539/3586 0/5 Szymanski-PT-b04-CTLFireability-00 590341 t fired, 2143 attempts, .
49 EF STEQ 539/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 553 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 285/302 31/32 Szymanski-PT-b04-CTLFireability-09 5254335 m, 18585 m/sec, 33177742 t fired, .
48 EF FNDP 544/3586 0/5 Szymanski-PT-b04-CTLFireability-00 595906 t fired, 2161 attempts, .
49 EF STEQ 544/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 558 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 290/302 31/32 Szymanski-PT-b04-CTLFireability-09 5346828 m, 18498 m/sec, 33729987 t fired, .
48 EF FNDP 549/3586 0/5 Szymanski-PT-b04-CTLFireability-00 601460 t fired, 2181 attempts, .
49 EF STEQ 549/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 563 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 295/302 32/32 Szymanski-PT-b04-CTLFireability-09 5440971 m, 18828 m/sec, 34315250 t fired, .
48 EF FNDP 554/3586 0/5 Szymanski-PT-b04-CTLFireability-00 607050 t fired, 2200 attempts, .
49 EF STEQ 554/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 568 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 300/302 32/32 Szymanski-PT-b04-CTLFireability-09 5532740 m, 18353 m/sec, 34878313 t fired, .
48 EF FNDP 559/3586 0/5 Szymanski-PT-b04-CTLFireability-00 612619 t fired, 2222 attempts, .
49 EF STEQ 559/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 573 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: CANCELED task # 32 (type EXCL) for Szymanski-PT-b04-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 564/3586 0/5 Szymanski-PT-b04-CTLFireability-00 618184 t fired, 2242 attempts, .
49 EF STEQ 564/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 578 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: LAUNCH task # 29 (type EXCL) for 24 Szymanski-PT-b04-CTLFireability-08
lola: time limit : 302 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/302 2/32 Szymanski-PT-b04-CTLFireability-08 227170 m, 45434 m/sec, 955746 t fired, .
48 EF FNDP 569/3586 0/5 Szymanski-PT-b04-CTLFireability-00 623755 t fired, 2265 attempts, .
49 EF STEQ 569/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 583 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/302 3/32 Szymanski-PT-b04-CTLFireability-08 459282 m, 46422 m/sec, 1880326 t fired, .
48 EF FNDP 574/3586 0/5 Szymanski-PT-b04-CTLFireability-00 629373 t fired, 2286 attempts, .
49 EF STEQ 574/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 588 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/302 5/32 Szymanski-PT-b04-CTLFireability-08 682744 m, 44692 m/sec, 2779300 t fired, .
48 EF FNDP 580/3586 0/5 Szymanski-PT-b04-CTLFireability-00 634988 t fired, 2304 attempts, .
49 EF STEQ 580/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 594 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 21/302 6/32 Szymanski-PT-b04-CTLFireability-08 900628 m, 43576 m/sec, 3690546 t fired, .
48 EF FNDP 585/3586 0/5 Szymanski-PT-b04-CTLFireability-00 640574 t fired, 2323 attempts, .
49 EF STEQ 585/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 599 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 26/302 7/32 Szymanski-PT-b04-CTLFireability-08 1126907 m, 45255 m/sec, 4560316 t fired, .
48 EF FNDP 590/3586 0/5 Szymanski-PT-b04-CTLFireability-00 646150 t fired, 2339 attempts, .
49 EF STEQ 590/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 604 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 31/302 9/32 Szymanski-PT-b04-CTLFireability-08 1358210 m, 46260 m/sec, 5401744 t fired, .
48 EF FNDP 595/3586 0/5 Szymanski-PT-b04-CTLFireability-00 651732 t fired, 2359 attempts, .
49 EF STEQ 595/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 609 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 36/302 10/32 Szymanski-PT-b04-CTLFireability-08 1600781 m, 48514 m/sec, 6182118 t fired, .
48 EF FNDP 600/3586 0/5 Szymanski-PT-b04-CTLFireability-00 657331 t fired, 2378 attempts, .
49 EF STEQ 600/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 614 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 41/302 11/32 Szymanski-PT-b04-CTLFireability-08 1812989 m, 42441 m/sec, 7080984 t fired, .
48 EF FNDP 605/3586 0/5 Szymanski-PT-b04-CTLFireability-00 662911 t fired, 2398 attempts, .
49 EF STEQ 605/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 619 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 46/302 12/32 Szymanski-PT-b04-CTLFireability-08 2013002 m, 40002 m/sec, 8066144 t fired, .
48 EF FNDP 610/3586 0/5 Szymanski-PT-b04-CTLFireability-00 668497 t fired, 2418 attempts, .
49 EF STEQ 610/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 624 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 51/302 14/32 Szymanski-PT-b04-CTLFireability-08 2239107 m, 45221 m/sec, 8894636 t fired, .
48 EF FNDP 615/3586 0/5 Szymanski-PT-b04-CTLFireability-00 674075 t fired, 2437 attempts, .
49 EF STEQ 615/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 629 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 56/302 15/32 Szymanski-PT-b04-CTLFireability-08 2473856 m, 46949 m/sec, 9679235 t fired, .
48 EF FNDP 620/3586 0/5 Szymanski-PT-b04-CTLFireability-00 679651 t fired, 2457 attempts, .
49 EF STEQ 620/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 634 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 61/302 16/32 Szymanski-PT-b04-CTLFireability-08 2703429 m, 45914 m/sec, 10465428 t fired, .
48 EF FNDP 625/3586 0/5 Szymanski-PT-b04-CTLFireability-00 685231 t fired, 2471 attempts, .
49 EF STEQ 625/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 639 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 66/302 17/32 Szymanski-PT-b04-CTLFireability-08 2908837 m, 41081 m/sec, 11354717 t fired, .
48 EF FNDP 630/3586 0/5 Szymanski-PT-b04-CTLFireability-00 690805 t fired, 2490 attempts, .
49 EF STEQ 630/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 644 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 71/302 19/32 Szymanski-PT-b04-CTLFireability-08 3122174 m, 42667 m/sec, 12180662 t fired, .
48 EF FNDP 635/3586 0/5 Szymanski-PT-b04-CTLFireability-00 696369 t fired, 2506 attempts, .
49 EF STEQ 635/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 649 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 76/302 20/32 Szymanski-PT-b04-CTLFireability-08 3345170 m, 44599 m/sec, 12955991 t fired, .
48 EF FNDP 640/3586 0/5 Szymanski-PT-b04-CTLFireability-00 701923 t fired, 2527 attempts, .
49 EF STEQ 640/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 654 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 81/302 21/32 Szymanski-PT-b04-CTLFireability-08 3567455 m, 44457 m/sec, 13788748 t fired, .
48 EF FNDP 645/3586 0/5 Szymanski-PT-b04-CTLFireability-00 707485 t fired, 2543 attempts, .
49 EF STEQ 645/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 659 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 86/302 23/32 Szymanski-PT-b04-CTLFireability-08 3795604 m, 45629 m/sec, 14589377 t fired, .
48 EF FNDP 650/3586 0/5 Szymanski-PT-b04-CTLFireability-00 713024 t fired, 2565 attempts, .
49 EF STEQ 650/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 664 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 91/302 24/32 Szymanski-PT-b04-CTLFireability-08 4017145 m, 44308 m/sec, 15391988 t fired, .
48 EF FNDP 655/3586 0/5 Szymanski-PT-b04-CTLFireability-00 718567 t fired, 2583 attempts, .
49 EF STEQ 655/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 669 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 96/302 25/32 Szymanski-PT-b04-CTLFireability-08 4235319 m, 43634 m/sec, 16238087 t fired, .
48 EF FNDP 660/3586 0/5 Szymanski-PT-b04-CTLFireability-00 724138 t fired, 2603 attempts, .
49 EF STEQ 660/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 674 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 101/302 26/32 Szymanski-PT-b04-CTLFireability-08 4466444 m, 46225 m/sec, 16988781 t fired, .
48 EF FNDP 665/3586 0/5 Szymanski-PT-b04-CTLFireability-00 729671 t fired, 2626 attempts, .
49 EF STEQ 665/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 679 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 106/302 28/32 Szymanski-PT-b04-CTLFireability-08 4695377 m, 45786 m/sec, 17757530 t fired, .
48 EF FNDP 670/3586 0/5 Szymanski-PT-b04-CTLFireability-00 735239 t fired, 2644 attempts, .
49 EF STEQ 670/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 684 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 111/302 29/32 Szymanski-PT-b04-CTLFireability-08 4911039 m, 43132 m/sec, 18576465 t fired, .
48 EF FNDP 675/3586 0/5 Szymanski-PT-b04-CTLFireability-00 740799 t fired, 2662 attempts, .
49 EF STEQ 675/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 689 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 116/302 30/32 Szymanski-PT-b04-CTLFireability-08 5134971 m, 44786 m/sec, 19371643 t fired, .
48 EF FNDP 680/3586 0/5 Szymanski-PT-b04-CTLFireability-00 746357 t fired, 2680 attempts, .
49 EF STEQ 680/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 694 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 121/302 31/32 Szymanski-PT-b04-CTLFireability-08 5349787 m, 42963 m/sec, 20183573 t fired, .
48 EF FNDP 685/3586 0/5 Szymanski-PT-b04-CTLFireability-00 751838 t fired, 2700 attempts, .
49 EF STEQ 685/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 699 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: CANCELED task # 29 (type EXCL) for Szymanski-PT-b04-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 1 0 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 690/3586 0/5 Szymanski-PT-b04-CTLFireability-00 757358 t fired, 2718 attempts, .
49 EF STEQ 690/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 704 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: LAUNCH task # 27 (type EXCL) for 24 Szymanski-PT-b04-CTLFireability-08
lola: time limit : 321 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 5/321 2/32 Szymanski-PT-b04-CTLFireability-08 226768 m, 45353 m/sec, 953964 t fired, .
48 EF FNDP 695/3586 0/5 Szymanski-PT-b04-CTLFireability-00 762890 t fired, 2740 attempts, .
49 EF STEQ 695/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 709 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 10/321 3/32 Szymanski-PT-b04-CTLFireability-08 457818 m, 46210 m/sec, 1871711 t fired, .
48 EF FNDP 700/3586 0/5 Szymanski-PT-b04-CTLFireability-00 768375 t fired, 2759 attempts, .
49 EF STEQ 700/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 714 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 15/321 5/32 Szymanski-PT-b04-CTLFireability-08 680040 m, 44444 m/sec, 2771229 t fired, .
48 EF FNDP 705/3586 0/5 Szymanski-PT-b04-CTLFireability-00 773905 t fired, 2780 attempts, .
49 EF STEQ 705/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 719 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 20/321 6/32 Szymanski-PT-b04-CTLFireability-08 896899 m, 43371 m/sec, 3679436 t fired, .
48 EF FNDP 710/3586 0/5 Szymanski-PT-b04-CTLFireability-00 779430 t fired, 2801 attempts, .
49 EF STEQ 710/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 724 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 25/321 7/32 Szymanski-PT-b04-CTLFireability-08 1122354 m, 45091 m/sec, 4546687 t fired, .
48 EF FNDP 715/3586 0/5 Szymanski-PT-b04-CTLFireability-00 784909 t fired, 2820 attempts, .
49 EF STEQ 715/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 729 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 30/321 9/32 Szymanski-PT-b04-CTLFireability-08 1354491 m, 46427 m/sec, 5378135 t fired, .
48 EF FNDP 720/3586 0/5 Szymanski-PT-b04-CTLFireability-00 790436 t fired, 2840 attempts, .
49 EF STEQ 720/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 734 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 35/321 10/32 Szymanski-PT-b04-CTLFireability-08 1594863 m, 48074 m/sec, 6164248 t fired, .
48 EF FNDP 725/3586 0/5 Szymanski-PT-b04-CTLFireability-00 795927 t fired, 2861 attempts, .
49 EF STEQ 725/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 739 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 40/321 11/32 Szymanski-PT-b04-CTLFireability-08 1806054 m, 42238 m/sec, 7059664 t fired, .
48 EF FNDP 730/3586 0/5 Szymanski-PT-b04-CTLFireability-00 801397 t fired, 2882 attempts, .
49 EF STEQ 730/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 744 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 45/321 12/32 Szymanski-PT-b04-CTLFireability-08 2007532 m, 40295 m/sec, 8026097 t fired, .
48 EF FNDP 735/3586 0/5 Szymanski-PT-b04-CTLFireability-00 806865 t fired, 2902 attempts, .
49 EF STEQ 735/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 749 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 50/321 14/32 Szymanski-PT-b04-CTLFireability-08 2229985 m, 44490 m/sec, 8854634 t fired, .
48 EF FNDP 740/3586 0/5 Szymanski-PT-b04-CTLFireability-00 812318 t fired, 2918 attempts, .
49 EF STEQ 740/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 754 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 55/321 15/32 Szymanski-PT-b04-CTLFireability-08 2462889 m, 46580 m/sec, 9644063 t fired, .
48 EF FNDP 745/3586 0/5 Szymanski-PT-b04-CTLFireability-00 817766 t fired, 2938 attempts, .
49 EF STEQ 745/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 759 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 60/321 16/32 Szymanski-PT-b04-CTLFireability-08 2696470 m, 46716 m/sec, 10405352 t fired, .
48 EF FNDP 750/3586 0/5 Szymanski-PT-b04-CTLFireability-00 823176 t fired, 2958 attempts, .
49 EF STEQ 750/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 764 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 65/321 17/32 Szymanski-PT-b04-CTLFireability-08 2894653 m, 39636 m/sec, 11306476 t fired, .
48 EF FNDP 755/3586 0/5 Szymanski-PT-b04-CTLFireability-00 828608 t fired, 2978 attempts, .
49 EF STEQ 755/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 769 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 70/321 19/32 Szymanski-PT-b04-CTLFireability-08 3111274 m, 43324 m/sec, 12144737 t fired, .
48 EF FNDP 760/3586 0/5 Szymanski-PT-b04-CTLFireability-00 834055 t fired, 2998 attempts, .
49 EF STEQ 760/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 774 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 75/321 20/32 Szymanski-PT-b04-CTLFireability-08 3339176 m, 45580 m/sec, 12936143 t fired, .
48 EF FNDP 765/3586 0/5 Szymanski-PT-b04-CTLFireability-00 839474 t fired, 3019 attempts, .
49 EF STEQ 765/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 779 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 80/321 21/32 Szymanski-PT-b04-CTLFireability-08 3561723 m, 44509 m/sec, 13770956 t fired, .
48 EF FNDP 770/3586 0/5 Szymanski-PT-b04-CTLFireability-00 844914 t fired, 3037 attempts, .
49 EF STEQ 770/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 784 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 85/321 23/32 Szymanski-PT-b04-CTLFireability-08 3787894 m, 45234 m/sec, 14564819 t fired, .
48 EF FNDP 775/3586 0/5 Szymanski-PT-b04-CTLFireability-00 850393 t fired, 3053 attempts, .
49 EF STEQ 775/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 789 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 90/321 24/32 Szymanski-PT-b04-CTLFireability-08 4009785 m, 44378 m/sec, 15368960 t fired, .
48 EF FNDP 780/3586 0/5 Szymanski-PT-b04-CTLFireability-00 855817 t fired, 3073 attempts, .
49 EF STEQ 780/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 794 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 95/321 25/32 Szymanski-PT-b04-CTLFireability-08 4227748 m, 43592 m/sec, 16213793 t fired, .
48 EF FNDP 785/3586 0/5 Szymanski-PT-b04-CTLFireability-00 861257 t fired, 3095 attempts, .
49 EF STEQ 785/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 799 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 100/321 26/32 Szymanski-PT-b04-CTLFireability-08 4458883 m, 46227 m/sec, 16963823 t fired, .
48 EF FNDP 790/3586 0/5 Szymanski-PT-b04-CTLFireability-00 866689 t fired, 3117 attempts, .
49 EF STEQ 790/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 804 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 105/321 28/32 Szymanski-PT-b04-CTLFireability-08 4688158 m, 45855 m/sec, 17734005 t fired, .
48 EF FNDP 795/3586 0/5 Szymanski-PT-b04-CTLFireability-00 872139 t fired, 3138 attempts, .
49 EF STEQ 795/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 809 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 110/321 29/32 Szymanski-PT-b04-CTLFireability-08 4903459 m, 43060 m/sec, 18552022 t fired, .
48 EF FNDP 800/3586 0/5 Szymanski-PT-b04-CTLFireability-00 877663 t fired, 3157 attempts, .
49 EF STEQ 800/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 814 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 115/321 30/32 Szymanski-PT-b04-CTLFireability-08 5130118 m, 45331 m/sec, 19330612 t fired, .
48 EF FNDP 805/3586 0/5 Szymanski-PT-b04-CTLFireability-00 883127 t fired, 3176 attempts, .
49 EF STEQ 805/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 819 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 1 0 2 0 1 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 120/321 31/32 Szymanski-PT-b04-CTLFireability-08 5341720 m, 42320 m/sec, 20157424 t fired, .
48 EF FNDP 810/3586 0/5 Szymanski-PT-b04-CTLFireability-00 888652 t fired, 3198 attempts, .
49 EF STEQ 810/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 824 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: CANCELED task # 27 (type EXCL) for Szymanski-PT-b04-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 1 2 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 815/3586 0/5 Szymanski-PT-b04-CTLFireability-00 894205 t fired, 3214 attempts, .
49 EF STEQ 815/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 829 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: LAUNCH task # 10 (type EXCL) for 9 Szymanski-PT-b04-CTLFireability-03
lola: time limit : 346 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for Szymanski-PT-b04-CTLFireability-03
lola: result : false
lola: markings : 45307
lola: fired transitions : 125303
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 Szymanski-PT-b04-CTLFireability-01
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for Szymanski-PT-b04-CTLFireability-01
lola: result : false
lola: markings : 600
lola: fired transitions : 1893
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 0 Szymanski-PT-b04-CTLFireability-00
lola: time limit : 461 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 820/3586 0/5 Szymanski-PT-b04-CTLFireability-00 899752 t fired, 3232 attempts, .
49 EF STEQ 820/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 4/461 1/32 Szymanski-PT-b04-CTLFireability-00 4623 m, 924 m/sec, 11671 t fired, .
Time elapsed: 834 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 825/3586 0/5 Szymanski-PT-b04-CTLFireability-00 905331 t fired, 3253 attempts, .
49 EF STEQ 825/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 9/461 1/32 Szymanski-PT-b04-CTLFireability-00 10054 m, 1086 m/sec, 33186 t fired, .
Time elapsed: 839 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 830/3586 0/5 Szymanski-PT-b04-CTLFireability-00 910909 t fired, 3273 attempts, .
49 EF STEQ 830/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 14/461 1/32 Szymanski-PT-b04-CTLFireability-00 15525 m, 1094 m/sec, 56846 t fired, .
Time elapsed: 844 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 835/3586 0/5 Szymanski-PT-b04-CTLFireability-00 916488 t fired, 3292 attempts, .
49 EF STEQ 835/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 19/461 1/32 Szymanski-PT-b04-CTLFireability-00 21102 m, 1115 m/sec, 70711 t fired, .
Time elapsed: 849 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 840/3586 0/5 Szymanski-PT-b04-CTLFireability-00 922044 t fired, 3315 attempts, .
49 EF STEQ 840/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 24/461 1/32 Szymanski-PT-b04-CTLFireability-00 26553 m, 1090 m/sec, 84072 t fired, .
Time elapsed: 854 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 845/3586 0/5 Szymanski-PT-b04-CTLFireability-00 927615 t fired, 3334 attempts, .
49 EF STEQ 845/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 29/461 1/32 Szymanski-PT-b04-CTLFireability-00 32104 m, 1110 m/sec, 97055 t fired, .
Time elapsed: 859 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 850/3586 0/5 Szymanski-PT-b04-CTLFireability-00 933183 t fired, 3354 attempts, .
49 EF STEQ 850/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 34/461 1/32 Szymanski-PT-b04-CTLFireability-00 37649 m, 1109 m/sec, 109942 t fired, .
Time elapsed: 864 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 855/3586 0/5 Szymanski-PT-b04-CTLFireability-00 938763 t fired, 3370 attempts, .
49 EF STEQ 855/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 39/461 1/32 Szymanski-PT-b04-CTLFireability-00 43251 m, 1120 m/sec, 124163 t fired, .
Time elapsed: 869 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 860/3586 0/5 Szymanski-PT-b04-CTLFireability-00 944310 t fired, 3394 attempts, .
49 EF STEQ 860/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 44/461 1/32 Szymanski-PT-b04-CTLFireability-00 48690 m, 1087 m/sec, 138673 t fired, .
Time elapsed: 874 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 865/3586 0/5 Szymanski-PT-b04-CTLFireability-00 949893 t fired, 3419 attempts, .
49 EF STEQ 865/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 49/461 1/32 Szymanski-PT-b04-CTLFireability-00 54131 m, 1088 m/sec, 153906 t fired, .
Time elapsed: 879 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 870/3586 0/5 Szymanski-PT-b04-CTLFireability-00 955476 t fired, 3440 attempts, .
49 EF STEQ 870/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 54/461 1/32 Szymanski-PT-b04-CTLFireability-00 59752 m, 1124 m/sec, 172383 t fired, .
Time elapsed: 884 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 875/3586 0/5 Szymanski-PT-b04-CTLFireability-00 961026 t fired, 3462 attempts, .
49 EF STEQ 875/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 59/461 1/32 Szymanski-PT-b04-CTLFireability-00 65263 m, 1102 m/sec, 184920 t fired, .
Time elapsed: 889 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 880/3586 0/5 Szymanski-PT-b04-CTLFireability-00 966560 t fired, 3481 attempts, .
49 EF STEQ 880/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 64/461 1/32 Szymanski-PT-b04-CTLFireability-00 70962 m, 1139 m/sec, 204180 t fired, .
Time elapsed: 894 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 885/3586 0/5 Szymanski-PT-b04-CTLFireability-00 972154 t fired, 3500 attempts, .
49 EF STEQ 885/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 69/461 1/32 Szymanski-PT-b04-CTLFireability-00 76475 m, 1102 m/sec, 215734 t fired, .
Time elapsed: 899 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 890/3586 0/5 Szymanski-PT-b04-CTLFireability-00 977738 t fired, 3518 attempts, .
49 EF STEQ 890/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 74/461 1/32 Szymanski-PT-b04-CTLFireability-00 82088 m, 1122 m/sec, 232664 t fired, .
Time elapsed: 904 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 895/3586 0/5 Szymanski-PT-b04-CTLFireability-00 983344 t fired, 3535 attempts, .
49 EF STEQ 895/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 79/461 1/32 Szymanski-PT-b04-CTLFireability-00 87738 m, 1130 m/sec, 250070 t fired, .
Time elapsed: 909 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 900/3586 0/5 Szymanski-PT-b04-CTLFireability-00 988932 t fired, 3555 attempts, .
49 EF STEQ 900/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 84/461 1/32 Szymanski-PT-b04-CTLFireability-00 93387 m, 1129 m/sec, 264639 t fired, .
Time elapsed: 914 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 905/3586 0/5 Szymanski-PT-b04-CTLFireability-00 994477 t fired, 3576 attempts, .
49 EF STEQ 905/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 89/461 1/32 Szymanski-PT-b04-CTLFireability-00 99033 m, 1129 m/sec, 281434 t fired, .
Time elapsed: 919 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 910/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1000021 t fired, 3594 attempts, .
49 EF STEQ 910/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 94/461 1/32 Szymanski-PT-b04-CTLFireability-00 104740 m, 1141 m/sec, 300029 t fired, .
Time elapsed: 924 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 915/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1005607 t fired, 3610 attempts, .
49 EF STEQ 915/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 99/461 1/32 Szymanski-PT-b04-CTLFireability-00 110253 m, 1102 m/sec, 314861 t fired, .
Time elapsed: 929 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 920/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1011207 t fired, 3632 attempts, .
49 EF STEQ 920/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 104/461 1/32 Szymanski-PT-b04-CTLFireability-00 115655 m, 1080 m/sec, 326151 t fired, .
Time elapsed: 934 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 925/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1016788 t fired, 3655 attempts, .
49 EF STEQ 925/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 109/461 1/32 Szymanski-PT-b04-CTLFireability-00 121122 m, 1093 m/sec, 340976 t fired, .
Time elapsed: 939 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 930/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1022365 t fired, 3676 attempts, .
49 EF STEQ 930/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 114/461 1/32 Szymanski-PT-b04-CTLFireability-00 126579 m, 1091 m/sec, 355571 t fired, .
Time elapsed: 944 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 935/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1027890 t fired, 3695 attempts, .
49 EF STEQ 935/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 119/461 1/32 Szymanski-PT-b04-CTLFireability-00 132417 m, 1167 m/sec, 376147 t fired, .
Time elapsed: 949 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 940/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1033420 t fired, 3714 attempts, .
49 EF STEQ 940/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 124/461 1/32 Szymanski-PT-b04-CTLFireability-00 138148 m, 1146 m/sec, 391178 t fired, .
Time elapsed: 954 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 945/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1039008 t fired, 3731 attempts, .
49 EF STEQ 945/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 129/461 1/32 Szymanski-PT-b04-CTLFireability-00 143643 m, 1099 m/sec, 405571 t fired, .
Time elapsed: 959 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 950/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1044565 t fired, 3749 attempts, .
49 EF STEQ 950/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 134/461 1/32 Szymanski-PT-b04-CTLFireability-00 149540 m, 1179 m/sec, 432277 t fired, .
Time elapsed: 964 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 955/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1050194 t fired, 3766 attempts, .
49 EF STEQ 955/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 139/461 1/32 Szymanski-PT-b04-CTLFireability-00 155428 m, 1177 m/sec, 461663 t fired, .
Time elapsed: 969 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 960/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1055785 t fired, 3786 attempts, .
49 EF STEQ 960/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 144/461 1/32 Szymanski-PT-b04-CTLFireability-00 161213 m, 1157 m/sec, 494089 t fired, .
Time elapsed: 974 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 965/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1061359 t fired, 3805 attempts, .
49 EF STEQ 965/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 149/461 1/32 Szymanski-PT-b04-CTLFireability-00 167107 m, 1178 m/sec, 525215 t fired, .
Time elapsed: 979 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 970/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1066928 t fired, 3825 attempts, .
49 EF STEQ 970/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 154/461 1/32 Szymanski-PT-b04-CTLFireability-00 172942 m, 1167 m/sec, 556126 t fired, .
Time elapsed: 984 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 975/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1072505 t fired, 3843 attempts, .
49 EF STEQ 975/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 159/461 1/32 Szymanski-PT-b04-CTLFireability-00 178614 m, 1134 m/sec, 577003 t fired, .
Time elapsed: 989 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 980/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1078059 t fired, 3862 attempts, .
49 EF STEQ 980/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 164/461 1/32 Szymanski-PT-b04-CTLFireability-00 184172 m, 1111 m/sec, 592186 t fired, .
Time elapsed: 994 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 985/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1083617 t fired, 3882 attempts, .
49 EF STEQ 985/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 169/461 1/32 Szymanski-PT-b04-CTLFireability-00 189909 m, 1147 m/sec, 614788 t fired, .
Time elapsed: 999 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 990/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1089176 t fired, 3903 attempts, .
49 EF STEQ 990/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 174/461 1/32 Szymanski-PT-b04-CTLFireability-00 195382 m, 1094 m/sec, 626801 t fired, .
Time elapsed: 1004 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 995/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1094700 t fired, 3919 attempts, .
49 EF STEQ 995/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 179/461 1/32 Szymanski-PT-b04-CTLFireability-00 200962 m, 1116 m/sec, 639870 t fired, .
Time elapsed: 1009 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1000/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1100266 t fired, 3941 attempts, .
49 EF STEQ 1000/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 184/461 1/32 Szymanski-PT-b04-CTLFireability-00 206498 m, 1107 m/sec, 652683 t fired, .
Time elapsed: 1014 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1005/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1105801 t fired, 3957 attempts, .
49 EF STEQ 1005/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 189/461 2/32 Szymanski-PT-b04-CTLFireability-00 211979 m, 1096 m/sec, 667554 t fired, .
Time elapsed: 1019 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1010/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1111357 t fired, 3978 attempts, .
49 EF STEQ 1010/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 194/461 2/32 Szymanski-PT-b04-CTLFireability-00 217453 m, 1094 m/sec, 680775 t fired, .
Time elapsed: 1024 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1015/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1116946 t fired, 4001 attempts, .
49 EF STEQ 1015/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 199/461 2/32 Szymanski-PT-b04-CTLFireability-00 222967 m, 1102 m/sec, 692071 t fired, .
Time elapsed: 1029 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1020/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1122513 t fired, 4018 attempts, .
49 EF STEQ 1020/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 204/461 2/32 Szymanski-PT-b04-CTLFireability-00 228486 m, 1103 m/sec, 706125 t fired, .
Time elapsed: 1034 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1025/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1128094 t fired, 4039 attempts, .
49 EF STEQ 1025/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 209/461 2/32 Szymanski-PT-b04-CTLFireability-00 234007 m, 1104 m/sec, 719192 t fired, .
Time elapsed: 1039 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1030/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1133678 t fired, 4059 attempts, .
49 EF STEQ 1030/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 214/461 2/32 Szymanski-PT-b04-CTLFireability-00 239502 m, 1099 m/sec, 731314 t fired, .
Time elapsed: 1044 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1035/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1139242 t fired, 4077 attempts, .
49 EF STEQ 1035/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 219/461 2/32 Szymanski-PT-b04-CTLFireability-00 245050 m, 1109 m/sec, 743145 t fired, .
Time elapsed: 1049 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1040/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1144784 t fired, 4093 attempts, .
49 EF STEQ 1040/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 224/461 2/32 Szymanski-PT-b04-CTLFireability-00 250595 m, 1109 m/sec, 762784 t fired, .
Time elapsed: 1054 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1045/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1150336 t fired, 4114 attempts, .
49 EF STEQ 1045/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 229/461 2/32 Szymanski-PT-b04-CTLFireability-00 256133 m, 1107 m/sec, 783529 t fired, .
Time elapsed: 1059 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1050/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1155850 t fired, 4135 attempts, .
49 EF STEQ 1050/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 234/461 2/32 Szymanski-PT-b04-CTLFireability-00 261645 m, 1102 m/sec, 798871 t fired, .
Time elapsed: 1064 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1055/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1161423 t fired, 4154 attempts, .
49 EF STEQ 1055/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 239/461 2/32 Szymanski-PT-b04-CTLFireability-00 267566 m, 1184 m/sec, 818627 t fired, .
Time elapsed: 1069 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1060/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1166935 t fired, 4173 attempts, .
49 EF STEQ 1060/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 244/461 2/32 Szymanski-PT-b04-CTLFireability-00 273241 m, 1135 m/sec, 844654 t fired, .
Time elapsed: 1074 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1065/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1172454 t fired, 4193 attempts, .
49 EF STEQ 1065/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 249/461 2/32 Szymanski-PT-b04-CTLFireability-00 278795 m, 1110 m/sec, 857912 t fired, .
Time elapsed: 1079 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1070/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1178020 t fired, 4211 attempts, .
49 EF STEQ 1070/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 254/461 2/32 Szymanski-PT-b04-CTLFireability-00 284308 m, 1102 m/sec, 868246 t fired, .
Time elapsed: 1084 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1075/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1183597 t fired, 4229 attempts, .
49 EF STEQ 1075/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 259/461 2/32 Szymanski-PT-b04-CTLFireability-00 289811 m, 1100 m/sec, 883871 t fired, .
Time elapsed: 1089 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1080/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1189160 t fired, 4246 attempts, .
49 EF STEQ 1080/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 264/461 2/32 Szymanski-PT-b04-CTLFireability-00 295378 m, 1113 m/sec, 898492 t fired, .
Time elapsed: 1094 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1085/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1194733 t fired, 4268 attempts, .
49 EF STEQ 1085/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 269/461 2/32 Szymanski-PT-b04-CTLFireability-00 301442 m, 1212 m/sec, 928591 t fired, .
Time elapsed: 1099 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1090/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1200305 t fired, 4288 attempts, .
49 EF STEQ 1090/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 274/461 2/32 Szymanski-PT-b04-CTLFireability-00 307343 m, 1180 m/sec, 960245 t fired, .
Time elapsed: 1104 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1095/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1205875 t fired, 4309 attempts, .
49 EF STEQ 1095/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 279/461 2/32 Szymanski-PT-b04-CTLFireability-00 312888 m, 1109 m/sec, 976216 t fired, .
Time elapsed: 1109 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1100/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1211476 t fired, 4329 attempts, .
49 EF STEQ 1100/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 284/461 2/32 Szymanski-PT-b04-CTLFireability-00 318459 m, 1114 m/sec, 992242 t fired, .
Time elapsed: 1114 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1105/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1217058 t fired, 4349 attempts, .
49 EF STEQ 1105/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 289/461 2/32 Szymanski-PT-b04-CTLFireability-00 324017 m, 1111 m/sec, 1014966 t fired, .
Time elapsed: 1119 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1110/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1222622 t fired, 4369 attempts, .
49 EF STEQ 1110/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 294/461 2/32 Szymanski-PT-b04-CTLFireability-00 329695 m, 1135 m/sec, 1032058 t fired, .
Time elapsed: 1124 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1115/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1228182 t fired, 4392 attempts, .
49 EF STEQ 1115/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 299/461 2/32 Szymanski-PT-b04-CTLFireability-00 335299 m, 1120 m/sec, 1048997 t fired, .
Time elapsed: 1129 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1120/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1233753 t fired, 4413 attempts, .
49 EF STEQ 1120/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 304/461 2/32 Szymanski-PT-b04-CTLFireability-00 341242 m, 1188 m/sec, 1080557 t fired, .
Time elapsed: 1134 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1125/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1239345 t fired, 4434 attempts, .
49 EF STEQ 1125/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 309/461 2/32 Szymanski-PT-b04-CTLFireability-00 347211 m, 1193 m/sec, 1112692 t fired, .
Time elapsed: 1139 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1130/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1244940 t fired, 4453 attempts, .
49 EF STEQ 1130/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 314/461 2/32 Szymanski-PT-b04-CTLFireability-00 353374 m, 1232 m/sec, 1148676 t fired, .
Time elapsed: 1144 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1135/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1250507 t fired, 4475 attempts, .
49 EF STEQ 1135/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 319/461 2/32 Szymanski-PT-b04-CTLFireability-00 359606 m, 1246 m/sec, 1185474 t fired, .
Time elapsed: 1149 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1140/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1256076 t fired, 4495 attempts, .
49 EF STEQ 1140/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 324/461 2/32 Szymanski-PT-b04-CTLFireability-00 365711 m, 1221 m/sec, 1217430 t fired, .
Time elapsed: 1154 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1145/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1261637 t fired, 4516 attempts, .
49 EF STEQ 1145/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 329/461 2/32 Szymanski-PT-b04-CTLFireability-00 371814 m, 1220 m/sec, 1253685 t fired, .
Time elapsed: 1159 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1150/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1267136 t fired, 4538 attempts, .
49 EF STEQ 1150/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 334/461 2/32 Szymanski-PT-b04-CTLFireability-00 377614 m, 1160 m/sec, 1286900 t fired, .
Time elapsed: 1164 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1155/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1272591 t fired, 4554 attempts, .
49 EF STEQ 1155/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 339/461 2/32 Szymanski-PT-b04-CTLFireability-00 383147 m, 1106 m/sec, 1322499 t fired, .
Time elapsed: 1169 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1160/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1278007 t fired, 4570 attempts, .
49 EF STEQ 1160/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 344/461 2/32 Szymanski-PT-b04-CTLFireability-00 388970 m, 1164 m/sec, 1361852 t fired, .
Time elapsed: 1174 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1165/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1283500 t fired, 4588 attempts, .
49 EF STEQ 1165/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 349/461 2/32 Szymanski-PT-b04-CTLFireability-00 394624 m, 1130 m/sec, 1397085 t fired, .
Time elapsed: 1179 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1170/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1288946 t fired, 4605 attempts, .
49 EF STEQ 1170/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 354/461 2/32 Szymanski-PT-b04-CTLFireability-00 400408 m, 1156 m/sec, 1424375 t fired, .
Time elapsed: 1184 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1175/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1294374 t fired, 4626 attempts, .
49 EF STEQ 1175/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 359/461 2/32 Szymanski-PT-b04-CTLFireability-00 405978 m, 1114 m/sec, 1438568 t fired, .
Time elapsed: 1189 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1180/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1299836 t fired, 4646 attempts, .
49 EF STEQ 1180/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 364/461 2/32 Szymanski-PT-b04-CTLFireability-00 411486 m, 1101 m/sec, 1453811 t fired, .
Time elapsed: 1194 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1185/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1305291 t fired, 4668 attempts, .
49 EF STEQ 1185/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 369/461 2/32 Szymanski-PT-b04-CTLFireability-00 417015 m, 1105 m/sec, 1466155 t fired, .
Time elapsed: 1199 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1190/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1310700 t fired, 4687 attempts, .
49 EF STEQ 1190/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 374/461 3/32 Szymanski-PT-b04-CTLFireability-00 422783 m, 1153 m/sec, 1484403 t fired, .
Time elapsed: 1204 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1195/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1316137 t fired, 4705 attempts, .
49 EF STEQ 1195/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 379/461 3/32 Szymanski-PT-b04-CTLFireability-00 428365 m, 1116 m/sec, 1499119 t fired, .
Time elapsed: 1209 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1200/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1321583 t fired, 4724 attempts, .
49 EF STEQ 1200/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 384/461 3/32 Szymanski-PT-b04-CTLFireability-00 433924 m, 1111 m/sec, 1513637 t fired, .
Time elapsed: 1214 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1205/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1327151 t fired, 4739 attempts, .
49 EF STEQ 1205/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 389/461 3/32 Szymanski-PT-b04-CTLFireability-00 439449 m, 1105 m/sec, 1537745 t fired, .
Time elapsed: 1219 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1210/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1332641 t fired, 4757 attempts, .
49 EF STEQ 1210/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 394/461 3/32 Szymanski-PT-b04-CTLFireability-00 444991 m, 1108 m/sec, 1558135 t fired, .
Time elapsed: 1224 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1215/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1338126 t fired, 4775 attempts, .
49 EF STEQ 1215/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 399/461 3/32 Szymanski-PT-b04-CTLFireability-00 450543 m, 1110 m/sec, 1573452 t fired, .
Time elapsed: 1229 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1220/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1343746 t fired, 4793 attempts, .
49 EF STEQ 1220/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 404/461 3/32 Szymanski-PT-b04-CTLFireability-00 456203 m, 1132 m/sec, 1587061 t fired, .
Time elapsed: 1234 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1225/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1349359 t fired, 4816 attempts, .
49 EF STEQ 1225/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 409/461 3/32 Szymanski-PT-b04-CTLFireability-00 461715 m, 1102 m/sec, 1599621 t fired, .
Time elapsed: 1239 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1230/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1354948 t fired, 4837 attempts, .
49 EF STEQ 1230/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 414/461 3/32 Szymanski-PT-b04-CTLFireability-00 467244 m, 1105 m/sec, 1617378 t fired, .
Time elapsed: 1244 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1235/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1360546 t fired, 4854 attempts, .
49 EF STEQ 1235/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 419/461 3/32 Szymanski-PT-b04-CTLFireability-00 472682 m, 1087 m/sec, 1630848 t fired, .
Time elapsed: 1249 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1240/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1366110 t fired, 4875 attempts, .
49 EF STEQ 1240/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 424/461 3/32 Szymanski-PT-b04-CTLFireability-00 478181 m, 1099 m/sec, 1644443 t fired, .
Time elapsed: 1254 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1245/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1371733 t fired, 4890 attempts, .
49 EF STEQ 1245/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 429/461 3/32 Szymanski-PT-b04-CTLFireability-00 483709 m, 1105 m/sec, 1659814 t fired, .
Time elapsed: 1259 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1250/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1377311 t fired, 4911 attempts, .
49 EF STEQ 1250/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 434/461 3/32 Szymanski-PT-b04-CTLFireability-00 489520 m, 1162 m/sec, 1684307 t fired, .
Time elapsed: 1264 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1255/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1382862 t fired, 4935 attempts, .
49 EF STEQ 1255/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 439/461 3/32 Szymanski-PT-b04-CTLFireability-00 495367 m, 1169 m/sec, 1717827 t fired, .
Time elapsed: 1269 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1260/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1388255 t fired, 4958 attempts, .
49 EF STEQ 1260/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 444/461 3/32 Szymanski-PT-b04-CTLFireability-00 501022 m, 1131 m/sec, 1752463 t fired, .
Time elapsed: 1274 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1265/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1393699 t fired, 4976 attempts, .
49 EF STEQ 1265/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 449/461 3/32 Szymanski-PT-b04-CTLFireability-00 506990 m, 1193 m/sec, 1788018 t fired, .
Time elapsed: 1279 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1270/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1399258 t fired, 4995 attempts, .
49 EF STEQ 1270/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 454/461 3/32 Szymanski-PT-b04-CTLFireability-00 512766 m, 1155 m/sec, 1813625 t fired, .
Time elapsed: 1284 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1275/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1404843 t fired, 5012 attempts, .
49 EF STEQ 1275/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 459/461 3/32 Szymanski-PT-b04-CTLFireability-00 518523 m, 1151 m/sec, 1835082 t fired, .
Time elapsed: 1289 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: CANCELED task # 50 (type EXCL) for Szymanski-PT-b04-CTLFireability-00 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 2 0 2 1 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1280/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1410381 t fired, 5030 attempts, .
49 EF STEQ 1280/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
Time elapsed: 1294 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
lola: LAUNCH task # 53 (type EXCL) for 18 Szymanski-PT-b04-CTLFireability-06
lola: time limit : 461 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 50 (type EXCL) for 0 Szymanski-PT-b04-CTLFireability-00
lola: time limit : 2306 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1285/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1415947 t fired, 5051 attempts, .
49 EF STEQ 1285/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 5/2306 1/5 Szymanski-PT-b04-CTLFireability-00 5514 m, -102601 m/sec, 15381 t fired, .
53 LTL EXCL 5/461 1/32 Szymanski-PT-b04-CTLFireability-06 2105 m, 421 m/sec, 3121 t fired, .
Time elapsed: 1299 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1290/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1421491 t fired, 5069 attempts, .
49 EF STEQ 1290/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 10/2306 1/5 Szymanski-PT-b04-CTLFireability-00 10893 m, 1075 m/sec, 36855 t fired, .
53 LTL EXCL 10/384 1/32 Szymanski-PT-b04-CTLFireability-06 3241 m, 227 m/sec, 6261 t fired, .
Time elapsed: 1304 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1295/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1427018 t fired, 5092 attempts, .
49 EF STEQ 1295/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 15/2306 1/5 Szymanski-PT-b04-CTLFireability-00 16295 m, 1080 m/sec, 59355 t fired, .
53 LTL EXCL 15/384 1/32 Szymanski-PT-b04-CTLFireability-06 4289 m, 209 m/sec, 8914 t fired, .
Time elapsed: 1309 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1300/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1432547 t fired, 5108 attempts, .
49 EF STEQ 1300/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 20/2306 1/5 Szymanski-PT-b04-CTLFireability-00 21829 m, 1106 m/sec, 73477 t fired, .
53 LTL EXCL 20/384 1/32 Szymanski-PT-b04-CTLFireability-06 5325 m, 207 m/sec, 11963 t fired, .
Time elapsed: 1314 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1305/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1438132 t fired, 5128 attempts, .
49 EF STEQ 1305/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 25/2306 1/5 Szymanski-PT-b04-CTLFireability-00 27210 m, 1076 m/sec, 85501 t fired, .
53 LTL EXCL 25/384 1/32 Szymanski-PT-b04-CTLFireability-06 6280 m, 191 m/sec, 14692 t fired, .
Time elapsed: 1319 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1310/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1443681 t fired, 5143 attempts, .
49 EF STEQ 1310/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 30/2306 1/5 Szymanski-PT-b04-CTLFireability-00 32746 m, 1107 m/sec, 99813 t fired, .
53 LTL EXCL 30/384 1/32 Szymanski-PT-b04-CTLFireability-06 7397 m, 223 m/sec, 17454 t fired, .
Time elapsed: 1324 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1315/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1449100 t fired, 5162 attempts, .
49 EF STEQ 1315/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 35/2306 1/5 Szymanski-PT-b04-CTLFireability-00 38084 m, 1067 m/sec, 110744 t fired, .
53 LTL EXCL 35/384 1/32 Szymanski-PT-b04-CTLFireability-06 8422 m, 205 m/sec, 19840 t fired, .
Time elapsed: 1329 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1320/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1454588 t fired, 5179 attempts, .
49 EF STEQ 1320/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 40/2306 1/5 Szymanski-PT-b04-CTLFireability-00 43680 m, 1119 m/sec, 124809 t fired, .
53 LTL EXCL 40/384 1/32 Szymanski-PT-b04-CTLFireability-06 9389 m, 193 m/sec, 22364 t fired, .
Time elapsed: 1334 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1325/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1460078 t fired, 5194 attempts, .
49 EF STEQ 1325/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 45/2306 1/5 Szymanski-PT-b04-CTLFireability-00 49136 m, 1091 m/sec, 139838 t fired, .
53 LTL EXCL 45/384 1/32 Szymanski-PT-b04-CTLFireability-06 10451 m, 212 m/sec, 25648 t fired, .
Time elapsed: 1339 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1330/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1465559 t fired, 5212 attempts, .
49 EF STEQ 1330/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 50/2306 1/5 Szymanski-PT-b04-CTLFireability-00 54542 m, 1081 m/sec, 154734 t fired, .
53 LTL EXCL 50/384 1/32 Szymanski-PT-b04-CTLFireability-06 11486 m, 207 m/sec, 28617 t fired, .
Time elapsed: 1344 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1335/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1471146 t fired, 5236 attempts, .
49 EF STEQ 1335/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 55/2306 1/5 Szymanski-PT-b04-CTLFireability-00 60041 m, 1099 m/sec, 173303 t fired, .
53 LTL EXCL 55/384 1/32 Szymanski-PT-b04-CTLFireability-06 12466 m, 196 m/sec, 30374 t fired, .
Time elapsed: 1349 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1340/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1476746 t fired, 5255 attempts, .
49 EF STEQ 1340/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 60/2306 1/5 Szymanski-PT-b04-CTLFireability-00 65399 m, 1071 m/sec, 185520 t fired, .
53 LTL EXCL 60/384 1/32 Szymanski-PT-b04-CTLFireability-06 13413 m, 189 m/sec, 33315 t fired, .
Time elapsed: 1354 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1345/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1482324 t fired, 5281 attempts, .
49 EF STEQ 1345/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 65/2306 1/5 Szymanski-PT-b04-CTLFireability-00 70983 m, 1116 m/sec, 204208 t fired, .
53 LTL EXCL 65/384 1/32 Szymanski-PT-b04-CTLFireability-06 14369 m, 191 m/sec, 35921 t fired, .
Time elapsed: 1359 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1350/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1487868 t fired, 5301 attempts, .
49 EF STEQ 1350/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 70/2306 1/5 Szymanski-PT-b04-CTLFireability-00 76400 m, 1083 m/sec, 215195 t fired, .
53 LTL EXCL 70/384 1/32 Szymanski-PT-b04-CTLFireability-06 15615 m, 249 m/sec, 39576 t fired, .
Time elapsed: 1364 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1355/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1493439 t fired, 5320 attempts, .
49 EF STEQ 1355/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 75/2306 1/5 Szymanski-PT-b04-CTLFireability-00 81957 m, 1111 m/sec, 232404 t fired, .
53 LTL EXCL 75/384 1/32 Szymanski-PT-b04-CTLFireability-06 16848 m, 246 m/sec, 43572 t fired, .
Time elapsed: 1369 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1360/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1499064 t fired, 5337 attempts, .
49 EF STEQ 1360/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 80/2306 1/5 Szymanski-PT-b04-CTLFireability-00 87503 m, 1109 m/sec, 249765 t fired, .
53 LTL EXCL 80/384 1/32 Szymanski-PT-b04-CTLFireability-06 17726 m, 175 m/sec, 45149 t fired, .
Time elapsed: 1374 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1365/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1504629 t fired, 5359 attempts, .
49 EF STEQ 1365/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 85/2306 1/5 Szymanski-PT-b04-CTLFireability-00 93082 m, 1115 m/sec, 264197 t fired, .
53 LTL EXCL 85/384 1/32 Szymanski-PT-b04-CTLFireability-06 18823 m, 219 m/sec, 46900 t fired, .
Time elapsed: 1379 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1370/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1510205 t fired, 5384 attempts, .
49 EF STEQ 1370/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 90/2306 1/5 Szymanski-PT-b04-CTLFireability-00 98671 m, 1117 m/sec, 280725 t fired, .
53 LTL EXCL 90/384 1/32 Szymanski-PT-b04-CTLFireability-06 19644 m, 164 m/sec, 48330 t fired, .
Time elapsed: 1384 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1375/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1515796 t fired, 5403 attempts, .
49 EF STEQ 1375/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 95/2306 1/5 Szymanski-PT-b04-CTLFireability-00 104288 m, 1123 m/sec, 298489 t fired, .
53 LTL EXCL 95/384 1/32 Szymanski-PT-b04-CTLFireability-06 20596 m, 190 m/sec, 51597 t fired, .
Time elapsed: 1389 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1380/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1521390 t fired, 5422 attempts, .
49 EF STEQ 1380/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 100/2306 1/5 Szymanski-PT-b04-CTLFireability-00 109763 m, 1095 m/sec, 313806 t fired, .
53 LTL EXCL 100/384 1/32 Szymanski-PT-b04-CTLFireability-06 21450 m, 170 m/sec, 54222 t fired, .
Time elapsed: 1394 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1385/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1526980 t fired, 5436 attempts, .
49 EF STEQ 1385/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 105/2306 1/5 Szymanski-PT-b04-CTLFireability-00 115087 m, 1064 m/sec, 324056 t fired, .
53 LTL EXCL 105/384 1/32 Szymanski-PT-b04-CTLFireability-06 22404 m, 190 m/sec, 56162 t fired, .
Time elapsed: 1399 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1390/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1532553 t fired, 5458 attempts, .
49 EF STEQ 1390/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 110/2306 1/5 Szymanski-PT-b04-CTLFireability-00 120464 m, 1075 m/sec, 339777 t fired, .
53 LTL EXCL 110/384 1/32 Szymanski-PT-b04-CTLFireability-06 23610 m, 241 m/sec, 59441 t fired, .
Time elapsed: 1404 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1395/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1538130 t fired, 5474 attempts, .
49 EF STEQ 1395/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 115/2306 1/5 Szymanski-PT-b04-CTLFireability-00 125802 m, 1067 m/sec, 354009 t fired, .
53 LTL EXCL 115/384 1/32 Szymanski-PT-b04-CTLFireability-06 24795 m, 237 m/sec, 62190 t fired, .
Time elapsed: 1409 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1400/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1543709 t fired, 5495 attempts, .
49 EF STEQ 1400/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 120/2306 1/5 Szymanski-PT-b04-CTLFireability-00 131518 m, 1143 m/sec, 373436 t fired, .
53 LTL EXCL 120/384 1/32 Szymanski-PT-b04-CTLFireability-06 25816 m, 204 m/sec, 65006 t fired, .
Time elapsed: 1414 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1405/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1549279 t fired, 5513 attempts, .
49 EF STEQ 1405/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 125/2306 1/5 Szymanski-PT-b04-CTLFireability-00 137241 m, 1144 m/sec, 389877 t fired, .
53 LTL EXCL 125/384 1/32 Szymanski-PT-b04-CTLFireability-06 26720 m, 180 m/sec, 68060 t fired, .
Time elapsed: 1419 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1410/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1554908 t fired, 5533 attempts, .
49 EF STEQ 1410/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 130/2306 1/5 Szymanski-PT-b04-CTLFireability-00 142705 m, 1092 m/sec, 403983 t fired, .
53 LTL EXCL 130/384 1/32 Szymanski-PT-b04-CTLFireability-06 27846 m, 225 m/sec, 69929 t fired, .
Time elapsed: 1424 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1415/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1560549 t fired, 5548 attempts, .
49 EF STEQ 1415/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 135/2306 1/5 Szymanski-PT-b04-CTLFireability-00 148458 m, 1150 m/sec, 427159 t fired, .
53 LTL EXCL 135/384 1/32 Szymanski-PT-b04-CTLFireability-06 28895 m, 209 m/sec, 71684 t fired, .
Time elapsed: 1429 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1420/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1566157 t fired, 5566 attempts, .
49 EF STEQ 1420/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 140/2306 1/5 Szymanski-PT-b04-CTLFireability-00 154388 m, 1186 m/sec, 455789 t fired, .
53 LTL EXCL 140/384 1/32 Szymanski-PT-b04-CTLFireability-06 29773 m, 175 m/sec, 75101 t fired, .
Time elapsed: 1434 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1425/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1571745 t fired, 5584 attempts, .
49 EF STEQ 1425/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 145/2306 1/5 Szymanski-PT-b04-CTLFireability-00 160058 m, 1134 m/sec, 488067 t fired, .
53 LTL EXCL 145/384 1/32 Szymanski-PT-b04-CTLFireability-06 30605 m, 166 m/sec, 78341 t fired, .
Time elapsed: 1439 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1430/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1577316 t fired, 5603 attempts, .
49 EF STEQ 1430/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 150/2306 1/5 Szymanski-PT-b04-CTLFireability-00 166010 m, 1190 m/sec, 519060 t fired, .
53 LTL EXCL 150/384 1/32 Szymanski-PT-b04-CTLFireability-06 31484 m, 175 m/sec, 80152 t fired, .
Time elapsed: 1444 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1435/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1582911 t fired, 5624 attempts, .
49 EF STEQ 1435/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 155/2306 1/5 Szymanski-PT-b04-CTLFireability-00 171830 m, 1164 m/sec, 550496 t fired, .
53 LTL EXCL 155/384 1/32 Szymanski-PT-b04-CTLFireability-06 32389 m, 181 m/sec, 82821 t fired, .
Time elapsed: 1449 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1440/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1588506 t fired, 5644 attempts, .
49 EF STEQ 1440/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 160/2306 1/5 Szymanski-PT-b04-CTLFireability-00 177468 m, 1127 m/sec, 572214 t fired, .
53 LTL EXCL 160/384 1/32 Szymanski-PT-b04-CTLFireability-06 33229 m, 168 m/sec, 85956 t fired, .
Time elapsed: 1454 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1445/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1594106 t fired, 5657 attempts, .
49 EF STEQ 1445/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 165/2306 1/5 Szymanski-PT-b04-CTLFireability-00 183036 m, 1113 m/sec, 587146 t fired, .
53 LTL EXCL 165/384 1/32 Szymanski-PT-b04-CTLFireability-06 34231 m, 200 m/sec, 88518 t fired, .
Time elapsed: 1459 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1450/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1599690 t fired, 5675 attempts, .
49 EF STEQ 1450/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 170/2306 1/5 Szymanski-PT-b04-CTLFireability-00 188655 m, 1123 m/sec, 609801 t fired, .
53 LTL EXCL 170/384 1/32 Szymanski-PT-b04-CTLFireability-06 35700 m, 293 m/sec, 93429 t fired, .
Time elapsed: 1464 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1455/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1605277 t fired, 5691 attempts, .
49 EF STEQ 1455/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 175/2306 1/5 Szymanski-PT-b04-CTLFireability-00 194098 m, 1088 m/sec, 623913 t fired, .
53 LTL EXCL 175/384 1/32 Szymanski-PT-b04-CTLFireability-06 36675 m, 195 m/sec, 95549 t fired, .
Time elapsed: 1469 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1460/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1610861 t fired, 5711 attempts, .
49 EF STEQ 1460/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 180/2306 1/5 Szymanski-PT-b04-CTLFireability-00 199558 m, 1092 m/sec, 635189 t fired, .
53 LTL EXCL 180/384 1/32 Szymanski-PT-b04-CTLFireability-06 37570 m, 179 m/sec, 97148 t fired, .
Time elapsed: 1474 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1465/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1616455 t fired, 5730 attempts, .
49 EF STEQ 1465/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 185/2306 1/5 Szymanski-PT-b04-CTLFireability-00 205096 m, 1107 m/sec, 649980 t fired, .
53 LTL EXCL 185/384 1/32 Szymanski-PT-b04-CTLFireability-06 38634 m, 212 m/sec, 98936 t fired, .
Time elapsed: 1479 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1470/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1622055 t fired, 5746 attempts, .
49 EF STEQ 1470/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 190/2306 2/5 Szymanski-PT-b04-CTLFireability-00 210484 m, 1077 m/sec, 663623 t fired, .
53 LTL EXCL 190/384 1/32 Szymanski-PT-b04-CTLFireability-06 39481 m, 169 m/sec, 100425 t fired, .
Time elapsed: 1484 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1475/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1627635 t fired, 5768 attempts, .
49 EF STEQ 1475/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 195/2306 2/5 Szymanski-PT-b04-CTLFireability-00 215895 m, 1082 m/sec, 677418 t fired, .
53 LTL EXCL 195/384 1/32 Szymanski-PT-b04-CTLFireability-06 40325 m, 168 m/sec, 101862 t fired, .
Time elapsed: 1489 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1480/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1633212 t fired, 5789 attempts, .
49 EF STEQ 1480/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 200/2306 2/5 Szymanski-PT-b04-CTLFireability-00 221428 m, 1106 m/sec, 688682 t fired, .
53 LTL EXCL 200/384 1/32 Szymanski-PT-b04-CTLFireability-06 41179 m, 170 m/sec, 104686 t fired, .
Time elapsed: 1494 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1485/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1638765 t fired, 5807 attempts, .
49 EF STEQ 1485/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 205/2306 2/5 Szymanski-PT-b04-CTLFireability-00 226875 m, 1089 m/sec, 702867 t fired, .
53 LTL EXCL 205/384 1/32 Szymanski-PT-b04-CTLFireability-06 42052 m, 174 m/sec, 107834 t fired, .
Time elapsed: 1499 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1490/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1644340 t fired, 5825 attempts, .
49 EF STEQ 1490/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 210/2306 2/5 Szymanski-PT-b04-CTLFireability-00 232317 m, 1088 m/sec, 713113 t fired, .
53 LTL EXCL 210/384 1/32 Szymanski-PT-b04-CTLFireability-06 42989 m, 187 m/sec, 111014 t fired, .
Time elapsed: 1504 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1495/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1649906 t fired, 5845 attempts, .
49 EF STEQ 1495/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 215/2306 2/5 Szymanski-PT-b04-CTLFireability-00 237785 m, 1093 m/sec, 725841 t fired, .
53 LTL EXCL 215/384 1/32 Szymanski-PT-b04-CTLFireability-06 44212 m, 244 m/sec, 115372 t fired, .
Time elapsed: 1509 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1500/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1655515 t fired, 5860 attempts, .
49 EF STEQ 1500/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 220/2306 2/5 Szymanski-PT-b04-CTLFireability-00 243234 m, 1089 m/sec, 738431 t fired, .
53 LTL EXCL 220/384 1/32 Szymanski-PT-b04-CTLFireability-06 45637 m, 285 m/sec, 120785 t fired, .
Time elapsed: 1514 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1505/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1661129 t fired, 5880 attempts, .
49 EF STEQ 1505/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 225/2306 2/5 Szymanski-PT-b04-CTLFireability-00 248767 m, 1106 m/sec, 758383 t fired, .
53 LTL EXCL 225/384 1/32 Szymanski-PT-b04-CTLFireability-06 46923 m, 257 m/sec, 126778 t fired, .
Time elapsed: 1519 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1510/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1666725 t fired, 5898 attempts, .
49 EF STEQ 1510/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 230/2306 2/5 Szymanski-PT-b04-CTLFireability-00 254256 m, 1097 m/sec, 774717 t fired, .
53 LTL EXCL 230/384 1/32 Szymanski-PT-b04-CTLFireability-06 48337 m, 282 m/sec, 133394 t fired, .
Time elapsed: 1524 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1515/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1672326 t fired, 5920 attempts, .
49 EF STEQ 1515/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 235/2306 2/5 Szymanski-PT-b04-CTLFireability-00 259753 m, 1099 m/sec, 794451 t fired, .
53 LTL EXCL 235/384 1/32 Szymanski-PT-b04-CTLFireability-06 49690 m, 270 m/sec, 139532 t fired, .
Time elapsed: 1529 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1520/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1677897 t fired, 5939 attempts, .
49 EF STEQ 1520/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 240/2306 2/5 Szymanski-PT-b04-CTLFireability-00 265516 m, 1152 m/sec, 811421 t fired, .
53 LTL EXCL 240/384 1/32 Szymanski-PT-b04-CTLFireability-06 50947 m, 251 m/sec, 145074 t fired, .
Time elapsed: 1534 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1525/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1683509 t fired, 5957 attempts, .
49 EF STEQ 1525/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 245/2306 2/5 Szymanski-PT-b04-CTLFireability-00 271162 m, 1129 m/sec, 835953 t fired, .
53 LTL EXCL 245/384 1/32 Szymanski-PT-b04-CTLFireability-06 51888 m, 188 m/sec, 146597 t fired, .
Time elapsed: 1539 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1530/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1689112 t fired, 5978 attempts, .
49 EF STEQ 1530/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 250/2306 2/5 Szymanski-PT-b04-CTLFireability-00 276798 m, 1127 m/sec, 853080 t fired, .
53 LTL EXCL 250/384 1/32 Szymanski-PT-b04-CTLFireability-06 52804 m, 183 m/sec, 148158 t fired, .
Time elapsed: 1544 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1535/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1694695 t fired, 5997 attempts, .
49 EF STEQ 1535/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 255/2306 2/5 Szymanski-PT-b04-CTLFireability-00 282217 m, 1083 m/sec, 865098 t fired, .
53 LTL EXCL 255/384 1/32 Szymanski-PT-b04-CTLFireability-06 53545 m, 148 m/sec, 150020 t fired, .
Time elapsed: 1549 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1540/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1700303 t fired, 6012 attempts, .
49 EF STEQ 1540/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 260/2306 2/5 Szymanski-PT-b04-CTLFireability-00 287714 m, 1099 m/sec, 879057 t fired, .
53 LTL EXCL 260/384 1/32 Szymanski-PT-b04-CTLFireability-06 54388 m, 168 m/sec, 153276 t fired, .
Time elapsed: 1554 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1545/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1705919 t fired, 6032 attempts, .
49 EF STEQ 1545/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 265/2306 2/5 Szymanski-PT-b04-CTLFireability-00 293241 m, 1105 m/sec, 892388 t fired, .
53 LTL EXCL 265/384 1/32 Szymanski-PT-b04-CTLFireability-06 55244 m, 171 m/sec, 154905 t fired, .
Time elapsed: 1559 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1550/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1711508 t fired, 6054 attempts, .
49 EF STEQ 1550/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 270/2306 2/5 Szymanski-PT-b04-CTLFireability-00 299000 m, 1151 m/sec, 916281 t fired, .
53 LTL EXCL 270/384 1/32 Szymanski-PT-b04-CTLFireability-06 56221 m, 195 m/sec, 156763 t fired, .
Time elapsed: 1564 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1555/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1717106 t fired, 6072 attempts, .
49 EF STEQ 1555/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 275/2306 2/5 Szymanski-PT-b04-CTLFireability-00 304841 m, 1168 m/sec, 948136 t fired, .
53 LTL EXCL 275/384 1/32 Szymanski-PT-b04-CTLFireability-06 57681 m, 292 m/sec, 162553 t fired, .
Time elapsed: 1569 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1560/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1722697 t fired, 6092 attempts, .
49 EF STEQ 1560/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 280/2306 2/5 Szymanski-PT-b04-CTLFireability-00 310565 m, 1144 m/sec, 971258 t fired, .
53 LTL EXCL 280/384 1/32 Szymanski-PT-b04-CTLFireability-06 58980 m, 259 m/sec, 167681 t fired, .
Time elapsed: 1574 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1565/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1728259 t fired, 6113 attempts, .
49 EF STEQ 1565/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 285/2306 2/5 Szymanski-PT-b04-CTLFireability-00 316069 m, 1100 m/sec, 983580 t fired, .
53 LTL EXCL 285/384 1/32 Szymanski-PT-b04-CTLFireability-06 60206 m, 245 m/sec, 172436 t fired, .
Time elapsed: 1579 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1570/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1733867 t fired, 6133 attempts, .
49 EF STEQ 1570/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 290/2306 2/5 Szymanski-PT-b04-CTLFireability-00 321581 m, 1102 m/sec, 1007809 t fired, .
53 LTL EXCL 290/384 1/32 Szymanski-PT-b04-CTLFireability-06 60846 m, 128 m/sec, 174324 t fired, .
Time elapsed: 1584 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1575/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1739445 t fired, 6152 attempts, .
49 EF STEQ 1575/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 295/2306 2/5 Szymanski-PT-b04-CTLFireability-00 327205 m, 1124 m/sec, 1025574 t fired, .
53 LTL EXCL 295/384 1/32 Szymanski-PT-b04-CTLFireability-06 61810 m, 192 m/sec, 177755 t fired, .
Time elapsed: 1589 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1580/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1745048 t fired, 6176 attempts, .
49 EF STEQ 1580/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 300/2306 2/5 Szymanski-PT-b04-CTLFireability-00 332676 m, 1094 m/sec, 1037452 t fired, .
53 LTL EXCL 300/384 1/32 Szymanski-PT-b04-CTLFireability-06 62644 m, 166 m/sec, 179218 t fired, .
Time elapsed: 1594 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1585/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1750615 t fired, 6198 attempts, .
49 EF STEQ 1585/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 305/2306 2/5 Szymanski-PT-b04-CTLFireability-00 338411 m, 1147 m/sec, 1065733 t fired, .
53 LTL EXCL 305/384 1/32 Szymanski-PT-b04-CTLFireability-06 63665 m, 204 m/sec, 184433 t fired, .
Time elapsed: 1599 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1590/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1756194 t fired, 6215 attempts, .
49 EF STEQ 1590/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 310/2306 2/5 Szymanski-PT-b04-CTLFireability-00 344324 m, 1182 m/sec, 1096134 t fired, .
53 LTL EXCL 310/384 1/32 Szymanski-PT-b04-CTLFireability-06 64875 m, 242 m/sec, 189888 t fired, .
Time elapsed: 1604 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1595/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1761779 t fired, 6231 attempts, .
49 EF STEQ 1595/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 315/2306 2/5 Szymanski-PT-b04-CTLFireability-00 350275 m, 1190 m/sec, 1130238 t fired, .
53 LTL EXCL 315/384 1/32 Szymanski-PT-b04-CTLFireability-06 66236 m, 272 m/sec, 196195 t fired, .
Time elapsed: 1609 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1600/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1767352 t fired, 6244 attempts, .
49 EF STEQ 1600/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 320/2306 2/5 Szymanski-PT-b04-CTLFireability-00 356440 m, 1233 m/sec, 1166005 t fired, .
53 LTL EXCL 320/384 1/32 Szymanski-PT-b04-CTLFireability-06 67609 m, 274 m/sec, 202569 t fired, .
Time elapsed: 1614 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1605/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1772956 t fired, 6263 attempts, .
49 EF STEQ 1605/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 325/2306 2/5 Szymanski-PT-b04-CTLFireability-00 362605 m, 1233 m/sec, 1199446 t fired, .
53 LTL EXCL 325/384 1/32 Szymanski-PT-b04-CTLFireability-06 68964 m, 271 m/sec, 209093 t fired, .
Time elapsed: 1619 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1610/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1778519 t fired, 6286 attempts, .
49 EF STEQ 1610/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 330/2306 2/5 Szymanski-PT-b04-CTLFireability-00 368522 m, 1183 m/sec, 1232955 t fired, .
53 LTL EXCL 330/384 1/32 Szymanski-PT-b04-CTLFireability-06 70374 m, 282 m/sec, 215370 t fired, .
Time elapsed: 1624 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1615/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1784135 t fired, 6307 attempts, .
49 EF STEQ 1615/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 335/2306 2/5 Szymanski-PT-b04-CTLFireability-00 374607 m, 1217 m/sec, 1267977 t fired, .
53 LTL EXCL 335/384 1/32 Szymanski-PT-b04-CTLFireability-06 71183 m, 161 m/sec, 216711 t fired, .
Time elapsed: 1629 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1620/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1789726 t fired, 6328 attempts, .
49 EF STEQ 1620/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 340/2306 2/5 Szymanski-PT-b04-CTLFireability-00 380146 m, 1107 m/sec, 1302622 t fired, .
53 LTL EXCL 340/384 1/32 Szymanski-PT-b04-CTLFireability-06 72092 m, 181 m/sec, 220847 t fired, .
Time elapsed: 1634 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1625/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1795320 t fired, 6347 attempts, .
49 EF STEQ 1625/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 345/2306 2/5 Szymanski-PT-b04-CTLFireability-00 385826 m, 1136 m/sec, 1340337 t fired, .
53 LTL EXCL 345/384 1/32 Szymanski-PT-b04-CTLFireability-06 73110 m, 203 m/sec, 223139 t fired, .
Time elapsed: 1639 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1630/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1800913 t fired, 6368 attempts, .
49 EF STEQ 1630/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 350/2306 2/5 Szymanski-PT-b04-CTLFireability-00 391582 m, 1151 m/sec, 1376494 t fired, .
53 LTL EXCL 350/384 1/32 Szymanski-PT-b04-CTLFireability-06 74164 m, 210 m/sec, 225050 t fired, .
Time elapsed: 1644 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1635/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1806530 t fired, 6391 attempts, .
49 EF STEQ 1635/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 355/2306 2/5 Szymanski-PT-b04-CTLFireability-00 397305 m, 1144 m/sec, 1415450 t fired, .
53 LTL EXCL 355/384 1/32 Szymanski-PT-b04-CTLFireability-06 74864 m, 140 m/sec, 227144 t fired, .
Time elapsed: 1649 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1640/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1812048 t fired, 6408 attempts, .
49 EF STEQ 1640/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 360/2306 2/5 Szymanski-PT-b04-CTLFireability-00 402847 m, 1108 m/sec, 1428700 t fired, .
53 LTL EXCL 360/384 1/32 Szymanski-PT-b04-CTLFireability-06 75839 m, 195 m/sec, 229497 t fired, .
Time elapsed: 1654 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1645/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1817439 t fired, 6425 attempts, .
49 EF STEQ 1645/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 365/2306 2/5 Szymanski-PT-b04-CTLFireability-00 408379 m, 1106 m/sec, 1446486 t fired, .
53 LTL EXCL 365/384 1/32 Szymanski-PT-b04-CTLFireability-06 76707 m, 173 m/sec, 231023 t fired, .
Time elapsed: 1659 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1650/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1822777 t fired, 6444 attempts, .
49 EF STEQ 1650/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 370/2306 2/5 Szymanski-PT-b04-CTLFireability-00 413828 m, 1089 m/sec, 1458652 t fired, .
53 LTL EXCL 370/384 1/32 Szymanski-PT-b04-CTLFireability-06 77546 m, 167 m/sec, 233343 t fired, .
Time elapsed: 1664 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1655/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1828205 t fired, 6463 attempts, .
49 EF STEQ 1655/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 375/2306 2/5 Szymanski-PT-b04-CTLFireability-00 419420 m, 1118 m/sec, 1471489 t fired, .
53 LTL EXCL 375/384 1/32 Szymanski-PT-b04-CTLFireability-06 78414 m, 173 m/sec, 235112 t fired, .
Time elapsed: 1669 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1660/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1833842 t fired, 6478 attempts, .
49 EF STEQ 1660/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 380/2306 3/5 Szymanski-PT-b04-CTLFireability-00 425080 m, 1132 m/sec, 1492187 t fired, .
53 LTL EXCL 380/384 1/32 Szymanski-PT-b04-CTLFireability-06 79479 m, 213 m/sec, 238545 t fired, .
Time elapsed: 1674 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: CANCELED task # 53 (type EXCL) for Szymanski-PT-b04-CTLFireability-06 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 0 0 1 1 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1665/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1839465 t fired, 6497 attempts, .
49 EF STEQ 1665/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 385/2306 3/5 Szymanski-PT-b04-CTLFireability-00 430498 m, 1083 m/sec, 1505985 t fired, .
Time elapsed: 1679 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: LAUNCH task # 53 (type EXCL) for 18 Szymanski-PT-b04-CTLFireability-06
lola: time limit : 1921 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1670/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1843837 t fired, 6510 attempts, .
49 EF STEQ 1670/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 390/461 3/5 Szymanski-PT-b04-CTLFireability-00 435008 m, 902 m/sec, 1516694 t fired, .
53 LTL EXCL 5/1921 1/5 Szymanski-PT-b04-CTLFireability-06 1893 m, -15517 m/sec, 2776 t fired, .
Time elapsed: 1684 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1675/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1848042 t fired, 6520 attempts, .
49 EF STEQ 1675/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 395/461 3/5 Szymanski-PT-b04-CTLFireability-00 439638 m, 926 m/sec, 1538512 t fired, .
53 LTL EXCL 10/320 1/5 Szymanski-PT-b04-CTLFireability-06 2698 m, 161 m/sec, 4806 t fired, .
Time elapsed: 1689 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1680/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1852512 t fired, 6535 attempts, .
49 EF STEQ 1680/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 400/461 3/5 Szymanski-PT-b04-CTLFireability-00 443952 m, 862 m/sec, 1553083 t fired, .
53 LTL EXCL 15/320 1/5 Szymanski-PT-b04-CTLFireability-06 3540 m, 168 m/sec, 6874 t fired, .
Time elapsed: 1694 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1685/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1857286 t fired, 6548 attempts, .
49 EF STEQ 1685/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 405/461 3/5 Szymanski-PT-b04-CTLFireability-00 448259 m, 861 m/sec, 1568696 t fired, .
53 LTL EXCL 20/320 1/5 Szymanski-PT-b04-CTLFireability-06 4347 m, 161 m/sec, 9089 t fired, .
Time elapsed: 1699 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1690/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1861944 t fired, 6561 attempts, .
49 EF STEQ 1690/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 410/461 3/5 Szymanski-PT-b04-CTLFireability-00 452629 m, 874 m/sec, 1578634 t fired, .
53 LTL EXCL 25/320 1/5 Szymanski-PT-b04-CTLFireability-06 5170 m, 164 m/sec, 11492 t fired, .
Time elapsed: 1704 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1695/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1866239 t fired, 6580 attempts, .
49 EF STEQ 1695/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 415/461 3/5 Szymanski-PT-b04-CTLFireability-00 457014 m, 877 m/sec, 1589580 t fired, .
53 LTL EXCL 30/320 1/5 Szymanski-PT-b04-CTLFireability-06 6014 m, 168 m/sec, 13804 t fired, .
Time elapsed: 1709 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1700/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1870708 t fired, 6593 attempts, .
49 EF STEQ 1700/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 420/461 3/5 Szymanski-PT-b04-CTLFireability-00 461398 m, 876 m/sec, 1598942 t fired, .
53 LTL EXCL 35/320 1/5 Szymanski-PT-b04-CTLFireability-06 6861 m, 169 m/sec, 16401 t fired, .
Time elapsed: 1714 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1705/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1875320 t fired, 6610 attempts, .
49 EF STEQ 1705/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 425/461 3/5 Szymanski-PT-b04-CTLFireability-00 465573 m, 835 m/sec, 1610984 t fired, .
53 LTL EXCL 40/320 1/5 Szymanski-PT-b04-CTLFireability-06 7665 m, 160 m/sec, 18044 t fired, .
Time elapsed: 1719 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1710/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1879550 t fired, 6623 attempts, .
49 EF STEQ 1710/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 430/461 3/5 Szymanski-PT-b04-CTLFireability-00 469812 m, 847 m/sec, 1623348 t fired, .
53 LTL EXCL 45/320 1/5 Szymanski-PT-b04-CTLFireability-06 8533 m, 173 m/sec, 20060 t fired, .
Time elapsed: 1724 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1715/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1884103 t fired, 6634 attempts, .
49 EF STEQ 1715/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 435/461 3/5 Szymanski-PT-b04-CTLFireability-00 474063 m, 850 m/sec, 1634639 t fired, .
53 LTL EXCL 50/320 1/5 Szymanski-PT-b04-CTLFireability-06 9293 m, 152 m/sec, 22136 t fired, .
Time elapsed: 1729 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1720/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1888680 t fired, 6650 attempts, .
49 EF STEQ 1720/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 440/461 3/5 Szymanski-PT-b04-CTLFireability-00 478373 m, 862 m/sec, 1644811 t fired, .
53 LTL EXCL 55/320 1/5 Szymanski-PT-b04-CTLFireability-06 10161 m, 173 m/sec, 24817 t fired, .
Time elapsed: 1734 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1725/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1893154 t fired, 6661 attempts, .
49 EF STEQ 1725/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 445/461 3/5 Szymanski-PT-b04-CTLFireability-00 482658 m, 857 m/sec, 1654652 t fired, .
53 LTL EXCL 60/320 1/5 Szymanski-PT-b04-CTLFireability-06 10995 m, 166 m/sec, 27576 t fired, .
Time elapsed: 1739 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1730/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1897400 t fired, 6671 attempts, .
49 EF STEQ 1730/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 450/461 3/5 Szymanski-PT-b04-CTLFireability-00 487117 m, 891 m/sec, 1671315 t fired, .
53 LTL EXCL 65/320 1/5 Szymanski-PT-b04-CTLFireability-06 11808 m, 162 m/sec, 29336 t fired, .
Time elapsed: 1744 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1735/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1901878 t fired, 6689 attempts, .
49 EF STEQ 1735/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 455/461 3/5 Szymanski-PT-b04-CTLFireability-00 491850 m, 946 m/sec, 1698189 t fired, .
53 LTL EXCL 70/320 1/5 Szymanski-PT-b04-CTLFireability-06 12486 m, 135 m/sec, 30406 t fired, .
Time elapsed: 1749 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1740/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1906231 t fired, 6703 attempts, .
49 EF STEQ 1740/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 460/461 3/5 Szymanski-PT-b04-CTLFireability-00 496304 m, 890 m/sec, 1723879 t fired, .
53 LTL EXCL 75/320 1/5 Szymanski-PT-b04-CTLFireability-06 13284 m, 159 m/sec, 32869 t fired, .
Time elapsed: 1754 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: CANCELED task # 50 (type EXCL) for Szymanski-PT-b04-CTLFireability-00 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 2 0 2 1 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1745/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1910591 t fired, 6716 attempts, .
49 EF STEQ 1745/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
53 LTL EXCL 80/320 1/5 Szymanski-PT-b04-CTLFireability-06 14009 m, 145 m/sec, 35404 t fired, .
Time elapsed: 1759 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 50 (type EXCL) for 0 Szymanski-PT-b04-CTLFireability-00
lola: time limit : 1841 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1750/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1915114 t fired, 6730 attempts, .
49 EF STEQ 1750/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 5/1841 1/5 Szymanski-PT-b04-CTLFireability-00 4295 m, -98401 m/sec, 10589 t fired, .
53 LTL EXCL 85/384 1/5 Szymanski-PT-b04-CTLFireability-06 14783 m, 154 m/sec, 36715 t fired, .
Time elapsed: 1764 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1755/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1919546 t fired, 6740 attempts, .
49 EF STEQ 1755/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 10/1841 1/5 Szymanski-PT-b04-CTLFireability-00 8575 m, 856 m/sec, 27414 t fired, .
53 LTL EXCL 90/320 1/5 Szymanski-PT-b04-CTLFireability-06 15741 m, 191 m/sec, 39808 t fired, .
Time elapsed: 1769 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1760/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1923499 t fired, 6752 attempts, .
49 EF STEQ 1760/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 15/1841 1/5 Szymanski-PT-b04-CTLFireability-00 12946 m, 874 m/sec, 46045 t fired, .
53 LTL EXCL 95/320 1/5 Szymanski-PT-b04-CTLFireability-06 16684 m, 188 m/sec, 42825 t fired, .
Time elapsed: 1774 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1765/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1928026 t fired, 6767 attempts, .
49 EF STEQ 1765/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 20/1841 1/5 Szymanski-PT-b04-CTLFireability-00 17284 m, 867 m/sec, 61375 t fired, .
53 LTL EXCL 100/320 1/5 Szymanski-PT-b04-CTLFireability-06 17504 m, 164 m/sec, 44812 t fired, .
Time elapsed: 1779 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1770/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1932437 t fired, 6779 attempts, .
49 EF STEQ 1770/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 25/1841 1/5 Szymanski-PT-b04-CTLFireability-00 21775 m, 898 m/sec, 73271 t fired, .
53 LTL EXCL 105/320 1/5 Szymanski-PT-b04-CTLFireability-06 18293 m, 157 m/sec, 45993 t fired, .
Time elapsed: 1784 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1775/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1936691 t fired, 6795 attempts, .
49 EF STEQ 1775/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 30/1841 1/5 Szymanski-PT-b04-CTLFireability-00 25957 m, 836 m/sec, 81867 t fired, .
53 LTL EXCL 110/320 1/5 Szymanski-PT-b04-CTLFireability-06 19087 m, 158 m/sec, 47361 t fired, .
Time elapsed: 1789 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1780/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1941059 t fired, 6805 attempts, .
49 EF STEQ 1780/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 35/1841 1/5 Szymanski-PT-b04-CTLFireability-00 30335 m, 875 m/sec, 92890 t fired, .
53 LTL EXCL 115/320 1/5 Szymanski-PT-b04-CTLFireability-06 19693 m, 121 m/sec, 48502 t fired, .
Time elapsed: 1794 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1785/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1945297 t fired, 6822 attempts, .
49 EF STEQ 1785/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 40/1841 1/5 Szymanski-PT-b04-CTLFireability-00 34618 m, 856 m/sec, 103755 t fired, .
53 LTL EXCL 120/320 1/5 Szymanski-PT-b04-CTLFireability-06 20355 m, 132 m/sec, 50694 t fired, .
Time elapsed: 1799 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1790/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1949438 t fired, 6836 attempts, .
49 EF STEQ 1790/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 45/1841 1/5 Szymanski-PT-b04-CTLFireability-00 38595 m, 795 m/sec, 112215 t fired, .
53 LTL EXCL 125/320 1/5 Szymanski-PT-b04-CTLFireability-06 21001 m, 129 m/sec, 53065 t fired, .
Time elapsed: 1804 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1795/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1954043 t fired, 6851 attempts, .
49 EF STEQ 1795/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 50/1841 1/5 Szymanski-PT-b04-CTLFireability-00 43206 m, 922 m/sec, 124075 t fired, .
53 LTL EXCL 130/320 1/5 Szymanski-PT-b04-CTLFireability-06 21643 m, 128 m/sec, 54563 t fired, .
Time elapsed: 1809 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1800/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1958339 t fired, 6859 attempts, .
49 EF STEQ 1800/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 55/1841 1/5 Szymanski-PT-b04-CTLFireability-00 47549 m, 868 m/sec, 136590 t fired, .
53 LTL EXCL 135/320 1/5 Szymanski-PT-b04-CTLFireability-06 22450 m, 161 m/sec, 56302 t fired, .
Time elapsed: 1814 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1805/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1962790 t fired, 6876 attempts, .
49 EF STEQ 1805/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 60/1841 1/5 Szymanski-PT-b04-CTLFireability-00 51809 m, 852 m/sec, 145653 t fired, .
53 LTL EXCL 140/320 1/5 Szymanski-PT-b04-CTLFireability-06 23342 m, 178 m/sec, 58983 t fired, .
Time elapsed: 1819 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1810/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1967043 t fired, 6890 attempts, .
49 EF STEQ 1810/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 65/1841 1/5 Szymanski-PT-b04-CTLFireability-00 56227 m, 883 m/sec, 159817 t fired, .
53 LTL EXCL 145/320 1/5 Szymanski-PT-b04-CTLFireability-06 24375 m, 206 m/sec, 61000 t fired, .
Time elapsed: 1824 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1815/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1971431 t fired, 6908 attempts, .
49 EF STEQ 1815/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 70/1841 1/5 Szymanski-PT-b04-CTLFireability-00 60431 m, 840 m/sec, 173974 t fired, .
53 LTL EXCL 150/320 1/5 Szymanski-PT-b04-CTLFireability-06 25152 m, 155 m/sec, 63550 t fired, .
Time elapsed: 1829 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1820/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1975912 t fired, 6924 attempts, .
49 EF STEQ 1820/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 75/1841 1/5 Szymanski-PT-b04-CTLFireability-00 64773 m, 868 m/sec, 182561 t fired, .
53 LTL EXCL 155/320 1/5 Szymanski-PT-b04-CTLFireability-06 25904 m, 150 m/sec, 65359 t fired, .
Time elapsed: 1834 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1825/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1980201 t fired, 6938 attempts, .
49 EF STEQ 1825/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 80/1841 1/5 Szymanski-PT-b04-CTLFireability-00 69272 m, 899 m/sec, 196726 t fired, .
53 LTL EXCL 160/320 1/5 Szymanski-PT-b04-CTLFireability-06 26627 m, 144 m/sec, 67911 t fired, .
Time elapsed: 1839 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1830/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1984648 t fired, 6954 attempts, .
49 EF STEQ 1830/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 85/1841 1/5 Szymanski-PT-b04-CTLFireability-00 73592 m, 864 m/sec, 208553 t fired, .
53 LTL EXCL 165/320 1/5 Szymanski-PT-b04-CTLFireability-06 27465 m, 167 m/sec, 69297 t fired, .
Time elapsed: 1844 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1835/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1989170 t fired, 6969 attempts, .
49 EF STEQ 1835/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 90/1841 1/5 Szymanski-PT-b04-CTLFireability-00 77872 m, 856 m/sec, 221875 t fired, .
53 LTL EXCL 170/320 1/5 Szymanski-PT-b04-CTLFireability-06 28417 m, 190 m/sec, 70803 t fired, .
Time elapsed: 1849 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1840/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1993464 t fired, 6979 attempts, .
49 EF STEQ 1840/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 95/1841 1/5 Szymanski-PT-b04-CTLFireability-00 82275 m, 880 m/sec, 232983 t fired, .
53 LTL EXCL 175/320 1/5 Szymanski-PT-b04-CTLFireability-06 29078 m, 132 m/sec, 72403 t fired, .
Time elapsed: 1854 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1845/3586 0/5 Szymanski-PT-b04-CTLFireability-00 1997929 t fired, 6991 attempts, .
49 EF STEQ 1845/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 100/1841 1/5 Szymanski-PT-b04-CTLFireability-00 86539 m, 852 m/sec, 247792 t fired, .
53 LTL EXCL 180/320 1/5 Szymanski-PT-b04-CTLFireability-06 29811 m, 146 m/sec, 75278 t fired, .
Time elapsed: 1859 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1850/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2002257 t fired, 7004 attempts, .
49 EF STEQ 1850/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 105/1841 1/5 Szymanski-PT-b04-CTLFireability-00 90775 m, 847 m/sec, 257936 t fired, .
53 LTL EXCL 185/320 1/5 Szymanski-PT-b04-CTLFireability-06 30425 m, 122 m/sec, 77666 t fired, .
Time elapsed: 1864 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1855/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2006250 t fired, 7013 attempts, .
49 EF STEQ 1855/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 110/1841 1/5 Szymanski-PT-b04-CTLFireability-00 95353 m, 915 m/sec, 268567 t fired, .
53 LTL EXCL 190/320 1/5 Szymanski-PT-b04-CTLFireability-06 31162 m, 147 m/sec, 79672 t fired, .
Time elapsed: 1869 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1860/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2010718 t fired, 7028 attempts, .
49 EF STEQ 1860/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 115/1841 1/5 Szymanski-PT-b04-CTLFireability-00 99714 m, 872 m/sec, 282724 t fired, .
53 LTL EXCL 195/320 1/5 Szymanski-PT-b04-CTLFireability-06 31768 m, 121 m/sec, 80847 t fired, .
Time elapsed: 1874 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1865/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2015061 t fired, 7046 attempts, .
49 EF STEQ 1865/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 120/1841 1/5 Szymanski-PT-b04-CTLFireability-00 104291 m, 915 m/sec, 298494 t fired, .
53 LTL EXCL 200/320 1/5 Szymanski-PT-b04-CTLFireability-06 32484 m, 143 m/sec, 83134 t fired, .
Time elapsed: 1879 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1870/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2019435 t fired, 7060 attempts, .
49 EF STEQ 1870/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 125/1841 1/5 Szymanski-PT-b04-CTLFireability-00 108759 m, 893 m/sec, 311859 t fired, .
53 LTL EXCL 205/320 1/5 Szymanski-PT-b04-CTLFireability-06 33135 m, 130 m/sec, 85570 t fired, .
Time elapsed: 1884 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1875/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2023882 t fired, 7070 attempts, .
49 EF STEQ 1875/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 130/1841 1/5 Szymanski-PT-b04-CTLFireability-00 112778 m, 803 m/sec, 319291 t fired, .
53 LTL EXCL 210/320 1/5 Szymanski-PT-b04-CTLFireability-06 33878 m, 148 m/sec, 87886 t fired, .
Time elapsed: 1889 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1880/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2028248 t fired, 7082 attempts, .
49 EF STEQ 1880/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 135/1841 1/5 Szymanski-PT-b04-CTLFireability-00 117079 m, 860 m/sec, 329326 t fired, .
53 LTL EXCL 215/320 1/5 Szymanski-PT-b04-CTLFireability-06 34848 m, 194 m/sec, 90191 t fired, .
Time elapsed: 1894 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1885/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2032564 t fired, 7094 attempts, .
49 EF STEQ 1885/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 140/1841 1/5 Szymanski-PT-b04-CTLFireability-00 121307 m, 845 m/sec, 341335 t fired, .
53 LTL EXCL 220/320 1/5 Szymanski-PT-b04-CTLFireability-06 35856 m, 201 m/sec, 93705 t fired, .
Time elapsed: 1899 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1890/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2037192 t fired, 7107 attempts, .
49 EF STEQ 1890/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 145/1841 1/5 Szymanski-PT-b04-CTLFireability-00 125741 m, 886 m/sec, 353766 t fired, .
53 LTL EXCL 225/320 1/5 Szymanski-PT-b04-CTLFireability-06 36613 m, 151 m/sec, 95402 t fired, .
Time elapsed: 1904 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1895/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2041610 t fired, 7122 attempts, .
49 EF STEQ 1895/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 150/1841 1/5 Szymanski-PT-b04-CTLFireability-00 130215 m, 894 m/sec, 369467 t fired, .
53 LTL EXCL 230/320 1/5 Szymanski-PT-b04-CTLFireability-06 37334 m, 144 m/sec, 96694 t fired, .
Time elapsed: 1909 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1900/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2045932 t fired, 7135 attempts, .
49 EF STEQ 1900/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 155/1841 1/5 Szymanski-PT-b04-CTLFireability-00 134939 m, 944 m/sec, 384097 t fired, .
53 LTL EXCL 235/320 1/5 Szymanski-PT-b04-CTLFireability-06 38112 m, 155 m/sec, 98177 t fired, .
Time elapsed: 1914 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1905/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2050190 t fired, 7148 attempts, .
49 EF STEQ 1905/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 160/1841 1/5 Szymanski-PT-b04-CTLFireability-00 139401 m, 892 m/sec, 395823 t fired, .
53 LTL EXCL 240/320 1/5 Szymanski-PT-b04-CTLFireability-06 38797 m, 137 m/sec, 99228 t fired, .
Time elapsed: 1919 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1910/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2054553 t fired, 7162 attempts, .
49 EF STEQ 1910/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 165/1841 1/5 Szymanski-PT-b04-CTLFireability-00 143692 m, 858 m/sec, 405639 t fired, .
53 LTL EXCL 245/320 1/5 Szymanski-PT-b04-CTLFireability-06 39488 m, 138 m/sec, 100438 t fired, .
Time elapsed: 1924 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1915/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2058944 t fired, 7176 attempts, .
49 EF STEQ 1915/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 170/1841 1/5 Szymanski-PT-b04-CTLFireability-00 148342 m, 930 m/sec, 426711 t fired, .
53 LTL EXCL 250/320 1/5 Szymanski-PT-b04-CTLFireability-06 40144 m, 131 m/sec, 101479 t fired, .
Time elapsed: 1929 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1920/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2063288 t fired, 7188 attempts, .
49 EF STEQ 1920/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 175/1841 1/5 Szymanski-PT-b04-CTLFireability-00 153030 m, 937 m/sec, 448597 t fired, .
53 LTL EXCL 255/320 1/5 Szymanski-PT-b04-CTLFireability-06 40845 m, 140 m/sec, 103616 t fired, .
Time elapsed: 1934 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1925/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2067705 t fired, 7203 attempts, .
49 EF STEQ 1925/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 180/1841 1/5 Szymanski-PT-b04-CTLFireability-00 157434 m, 880 m/sec, 473188 t fired, .
53 LTL EXCL 260/320 1/5 Szymanski-PT-b04-CTLFireability-06 41461 m, 123 m/sec, 105655 t fired, .
Time elapsed: 1939 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1930/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2072320 t fired, 7216 attempts, .
49 EF STEQ 1930/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 185/1841 1/5 Szymanski-PT-b04-CTLFireability-00 162208 m, 954 m/sec, 499974 t fired, .
53 LTL EXCL 265/320 1/5 Szymanski-PT-b04-CTLFireability-06 42092 m, 126 m/sec, 107999 t fired, .
Time elapsed: 1944 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1935/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2076593 t fired, 7230 attempts, .
49 EF STEQ 1935/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 190/1841 1/5 Szymanski-PT-b04-CTLFireability-00 166840 m, 926 m/sec, 523455 t fired, .
53 LTL EXCL 270/320 1/5 Szymanski-PT-b04-CTLFireability-06 42837 m, 149 m/sec, 110427 t fired, .
Time elapsed: 1949 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1940/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2081044 t fired, 7244 attempts, .
49 EF STEQ 1940/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 195/1841 1/5 Szymanski-PT-b04-CTLFireability-00 171484 m, 928 m/sec, 548462 t fired, .
53 LTL EXCL 275/320 1/5 Szymanski-PT-b04-CTLFireability-06 43800 m, 192 m/sec, 113911 t fired, .
Time elapsed: 1954 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1945/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2085268 t fired, 7257 attempts, .
49 EF STEQ 1945/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 200/1841 1/5 Szymanski-PT-b04-CTLFireability-00 176093 m, 921 m/sec, 566392 t fired, .
53 LTL EXCL 280/320 1/5 Szymanski-PT-b04-CTLFireability-06 44753 m, 190 m/sec, 117056 t fired, .
Time elapsed: 1959 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1950/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2089469 t fired, 7269 attempts, .
49 EF STEQ 1950/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 205/1841 1/5 Szymanski-PT-b04-CTLFireability-00 180559 m, 893 m/sec, 582135 t fired, .
53 LTL EXCL 285/320 1/5 Szymanski-PT-b04-CTLFireability-06 45804 m, 210 m/sec, 121619 t fired, .
Time elapsed: 1964 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1955/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2093789 t fired, 7280 attempts, .
49 EF STEQ 1955/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 210/1841 1/5 Szymanski-PT-b04-CTLFireability-00 184593 m, 806 m/sec, 594924 t fired, .
53 LTL EXCL 290/320 1/5 Szymanski-PT-b04-CTLFireability-06 46841 m, 207 m/sec, 126378 t fired, .
Time elapsed: 1969 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1960/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2097950 t fired, 7297 attempts, .
49 EF STEQ 1960/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 215/1841 1/5 Szymanski-PT-b04-CTLFireability-00 189137 m, 908 m/sec, 611742 t fired, .
53 LTL EXCL 295/320 1/5 Szymanski-PT-b04-CTLFireability-06 47854 m, 202 m/sec, 130815 t fired, .
Time elapsed: 1974 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1965/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2102424 t fired, 7311 attempts, .
49 EF STEQ 1965/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 220/1841 1/5 Szymanski-PT-b04-CTLFireability-00 193478 m, 868 m/sec, 622727 t fired, .
53 LTL EXCL 300/320 1/5 Szymanski-PT-b04-CTLFireability-06 48869 m, 203 m/sec, 135828 t fired, .
Time elapsed: 1979 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1970/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2106827 t fired, 7323 attempts, .
49 EF STEQ 1970/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 225/1841 1/5 Szymanski-PT-b04-CTLFireability-00 197692 m, 842 m/sec, 631229 t fired, .
53 LTL EXCL 305/320 1/5 Szymanski-PT-b04-CTLFireability-06 49990 m, 224 m/sec, 141043 t fired, .
Time elapsed: 1984 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1975/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2111331 t fired, 7341 attempts, .
49 EF STEQ 1975/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 230/1841 1/5 Szymanski-PT-b04-CTLFireability-00 202027 m, 867 m/sec, 643558 t fired, .
53 LTL EXCL 310/320 1/5 Szymanski-PT-b04-CTLFireability-06 50938 m, 189 m/sec, 145059 t fired, .
Time elapsed: 1989 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1980/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2115697 t fired, 7355 attempts, .
49 EF STEQ 1980/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 235/1841 1/5 Szymanski-PT-b04-CTLFireability-00 206422 m, 879 m/sec, 652590 t fired, .
53 LTL EXCL 315/320 1/5 Szymanski-PT-b04-CTLFireability-06 51666 m, 145 m/sec, 146219 t fired, .
Time elapsed: 1994 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1985/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2120251 t fired, 7367 attempts, .
49 EF STEQ 1985/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 240/1841 2/5 Szymanski-PT-b04-CTLFireability-00 210696 m, 854 m/sec, 664765 t fired, .
53 LTL EXCL 320/320 1/5 Szymanski-PT-b04-CTLFireability-06 52442 m, 155 m/sec, 147595 t fired, .
Time elapsed: 1999 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: CANCELED task # 53 (type EXCL) for Szymanski-PT-b04-CTLFireability-06 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 0 0 1 1 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1990/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2124664 t fired, 7380 attempts, .
49 EF STEQ 1990/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 245/1841 2/5 Szymanski-PT-b04-CTLFireability-00 214979 m, 856 m/sec, 675520 t fired, .
Time elapsed: 2004 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: LAUNCH task # 53 (type EXCL) for 18 Szymanski-PT-b04-CTLFireability-06
lola: time limit : 1596 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 1995/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2128139 t fired, 7390 attempts, .
49 EF STEQ 1995/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 250/368 2/5 Szymanski-PT-b04-CTLFireability-00 218187 m, 641 m/sec, 682753 t fired, .
53 LTL EXCL 5/1596 1/5 Szymanski-PT-b04-CTLFireability-06 1682 m, -10152 m/sec, 2457 t fired, .
Time elapsed: 2009 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2000/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2131652 t fired, 7400 attempts, .
49 EF STEQ 2000/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 255/368 2/5 Szymanski-PT-b04-CTLFireability-00 222066 m, 775 m/sec, 690036 t fired, .
53 LTL EXCL 10/266 1/5 Szymanski-PT-b04-CTLFireability-06 2384 m, 140 m/sec, 3899 t fired, .
Time elapsed: 2014 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2005/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2135169 t fired, 7412 attempts, .
49 EF STEQ 2005/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 260/368 2/5 Szymanski-PT-b04-CTLFireability-00 225848 m, 756 m/sec, 700757 t fired, .
53 LTL EXCL 15/266 1/5 Szymanski-PT-b04-CTLFireability-06 3127 m, 148 m/sec, 6042 t fired, .
Time elapsed: 2019 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2010/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2138639 t fired, 7426 attempts, .
49 EF STEQ 2010/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 265/368 2/5 Szymanski-PT-b04-CTLFireability-00 229591 m, 748 m/sec, 707884 t fired, .
53 LTL EXCL 20/266 1/5 Szymanski-PT-b04-CTLFireability-06 3816 m, 137 m/sec, 7471 t fired, .
Time elapsed: 2024 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2015/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2142068 t fired, 7439 attempts, .
49 EF STEQ 2015/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 270/368 2/5 Szymanski-PT-b04-CTLFireability-00 233226 m, 727 m/sec, 716144 t fired, .
53 LTL EXCL 25/266 1/5 Szymanski-PT-b04-CTLFireability-06 4562 m, 149 m/sec, 9842 t fired, .
Time elapsed: 2029 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2020/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2145598 t fired, 7449 attempts, .
49 EF STEQ 2020/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 275/368 2/5 Szymanski-PT-b04-CTLFireability-00 236915 m, 737 m/sec, 724214 t fired, .
53 LTL EXCL 30/266 1/5 Szymanski-PT-b04-CTLFireability-06 5246 m, 136 m/sec, 11736 t fired, .
Time elapsed: 2034 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2025/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2149181 t fired, 7464 attempts, .
49 EF STEQ 2025/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 280/368 2/5 Szymanski-PT-b04-CTLFireability-00 240559 m, 728 m/sec, 733515 t fired, .
53 LTL EXCL 35/266 1/5 Szymanski-PT-b04-CTLFireability-06 5853 m, 121 m/sec, 13311 t fired, .
Time elapsed: 2039 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2030/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2152948 t fired, 7475 attempts, .
49 EF STEQ 2030/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 285/368 2/5 Szymanski-PT-b04-CTLFireability-00 244090 m, 706 m/sec, 740829 t fired, .
53 LTL EXCL 40/266 1/5 Szymanski-PT-b04-CTLFireability-06 6554 m, 140 m/sec, 15677 t fired, .
Time elapsed: 2044 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2035/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2156619 t fired, 7488 attempts, .
49 EF STEQ 2035/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 290/368 2/5 Szymanski-PT-b04-CTLFireability-00 247720 m, 726 m/sec, 753134 t fired, .
53 LTL EXCL 45/266 1/5 Szymanski-PT-b04-CTLFireability-06 7301 m, 149 m/sec, 17290 t fired, .
Time elapsed: 2049 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2040/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2160461 t fired, 7500 attempts, .
49 EF STEQ 2040/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 295/368 2/5 Szymanski-PT-b04-CTLFireability-00 251284 m, 712 m/sec, 766062 t fired, .
53 LTL EXCL 50/266 1/5 Szymanski-PT-b04-CTLFireability-06 7892 m, 118 m/sec, 18523 t fired, .
Time elapsed: 2054 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2045/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2164193 t fired, 7512 attempts, .
49 EF STEQ 2045/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 300/368 2/5 Szymanski-PT-b04-CTLFireability-00 255196 m, 782 m/sec, 778566 t fired, .
53 LTL EXCL 55/266 1/5 Szymanski-PT-b04-CTLFireability-06 8606 m, 142 m/sec, 20238 t fired, .
Time elapsed: 2059 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2050/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2168070 t fired, 7524 attempts, .
49 EF STEQ 2050/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 305/368 2/5 Szymanski-PT-b04-CTLFireability-00 258792 m, 719 m/sec, 792590 t fired, .
53 LTL EXCL 60/266 1/5 Szymanski-PT-b04-CTLFireability-06 9310 m, 140 m/sec, 22168 t fired, .
Time elapsed: 2064 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2055/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2171565 t fired, 7536 attempts, .
49 EF STEQ 2055/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 310/368 2/5 Szymanski-PT-b04-CTLFireability-00 262266 m, 694 m/sec, 800379 t fired, .
53 LTL EXCL 65/266 1/5 Szymanski-PT-b04-CTLFireability-06 10040 m, 146 m/sec, 24342 t fired, .
Time elapsed: 2069 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2060/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2175294 t fired, 7548 attempts, .
49 EF STEQ 2060/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 315/368 2/5 Szymanski-PT-b04-CTLFireability-00 266165 m, 779 m/sec, 813475 t fired, .
53 LTL EXCL 70/266 1/5 Szymanski-PT-b04-CTLFireability-06 10703 m, 132 m/sec, 26572 t fired, .
Time elapsed: 2074 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2065/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2178849 t fired, 7562 attempts, .
49 EF STEQ 2065/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 320/368 2/5 Szymanski-PT-b04-CTLFireability-00 269935 m, 754 m/sec, 830462 t fired, .
53 LTL EXCL 75/266 1/5 Szymanski-PT-b04-CTLFireability-06 11426 m, 144 m/sec, 28526 t fired, .
Time elapsed: 2079 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2070/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2182440 t fired, 7572 attempts, .
49 EF STEQ 2070/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 325/368 2/5 Szymanski-PT-b04-CTLFireability-00 273800 m, 773 m/sec, 847001 t fired, .
53 LTL EXCL 80/266 1/5 Szymanski-PT-b04-CTLFireability-06 12093 m, 133 m/sec, 29801 t fired, .
Time elapsed: 2084 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2075/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2186106 t fired, 7580 attempts, .
49 EF STEQ 2075/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 330/368 2/5 Szymanski-PT-b04-CTLFireability-00 277641 m, 768 m/sec, 855408 t fired, .
53 LTL EXCL 85/266 1/5 Szymanski-PT-b04-CTLFireability-06 12631 m, 107 m/sec, 30818 t fired, .
Time elapsed: 2089 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2080/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2189798 t fired, 7589 attempts, .
49 EF STEQ 2080/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 335/368 2/5 Szymanski-PT-b04-CTLFireability-00 281066 m, 685 m/sec, 863135 t fired, .
53 LTL EXCL 90/266 1/5 Szymanski-PT-b04-CTLFireability-06 13288 m, 131 m/sec, 32877 t fired, .
Time elapsed: 2094 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2085/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2193468 t fired, 7602 attempts, .
49 EF STEQ 2085/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 340/368 2/5 Szymanski-PT-b04-CTLFireability-00 284603 m, 707 m/sec, 868755 t fired, .
53 LTL EXCL 95/266 1/5 Szymanski-PT-b04-CTLFireability-06 13858 m, 114 m/sec, 34896 t fired, .
Time elapsed: 2099 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2090/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2197079 t fired, 7612 attempts, .
49 EF STEQ 2090/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 345/368 2/5 Szymanski-PT-b04-CTLFireability-00 288314 m, 742 m/sec, 880589 t fired, .
53 LTL EXCL 100/266 1/5 Szymanski-PT-b04-CTLFireability-06 14536 m, 135 m/sec, 36176 t fired, .
Time elapsed: 2104 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2095/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2200961 t fired, 7627 attempts, .
49 EF STEQ 2095/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 350/368 2/5 Szymanski-PT-b04-CTLFireability-00 292012 m, 739 m/sec, 889155 t fired, .
53 LTL EXCL 105/266 1/5 Szymanski-PT-b04-CTLFireability-06 15346 m, 162 m/sec, 38697 t fired, .
Time elapsed: 2109 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2100/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2204141 t fired, 7642 attempts, .
49 EF STEQ 2100/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 355/368 2/5 Szymanski-PT-b04-CTLFireability-00 295645 m, 726 m/sec, 899541 t fired, .
53 LTL EXCL 110/266 1/5 Szymanski-PT-b04-CTLFireability-06 15967 m, 124 m/sec, 40178 t fired, .
Time elapsed: 2114 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2105/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2207688 t fired, 7653 attempts, .
49 EF STEQ 2105/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 360/368 2/5 Szymanski-PT-b04-CTLFireability-00 300018 m, 874 m/sec, 921627 t fired, .
53 LTL EXCL 115/266 1/5 Szymanski-PT-b04-CTLFireability-06 16877 m, 182 m/sec, 43711 t fired, .
Time elapsed: 2119 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2110/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2211328 t fired, 7664 attempts, .
49 EF STEQ 2110/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 365/368 2/5 Szymanski-PT-b04-CTLFireability-00 303628 m, 722 m/sec, 939562 t fired, .
53 LTL EXCL 120/266 1/5 Szymanski-PT-b04-CTLFireability-06 17425 m, 109 m/sec, 44687 t fired, .
Time elapsed: 2124 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: CANCELED task # 50 (type EXCL) for Szymanski-PT-b04-CTLFireability-00 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 2 0 2 1 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2115/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2215021 t fired, 7677 attempts, .
49 EF STEQ 2115/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
53 LTL EXCL 125/266 1/5 Szymanski-PT-b04-CTLFireability-06 17955 m, 106 m/sec, 45505 t fired, .
Time elapsed: 2129 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 50 (type EXCL) for 0 Szymanski-PT-b04-CTLFireability-00
lola: time limit : 1471 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2120/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2218830 t fired, 7688 attempts, .
49 EF STEQ 2120/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 5/1471 1/5 Szymanski-PT-b04-CTLFireability-00 3500 m, -60025 m/sec, 7958 t fired, .
53 LTL EXCL 130/319 1/5 Szymanski-PT-b04-CTLFireability-06 18713 m, 151 m/sec, 46691 t fired, .
Time elapsed: 2134 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2125/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2222592 t fired, 7699 attempts, .
49 EF STEQ 2125/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 10/1471 1/5 Szymanski-PT-b04-CTLFireability-00 6984 m, 696 m/sec, 21027 t fired, .
53 LTL EXCL 135/266 1/5 Szymanski-PT-b04-CTLFireability-06 19337 m, 124 m/sec, 47785 t fired, .
Time elapsed: 2139 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2130/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2226212 t fired, 7711 attempts, .
49 EF STEQ 2130/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 15/1471 1/5 Szymanski-PT-b04-CTLFireability-00 10383 m, 679 m/sec, 34676 t fired, .
53 LTL EXCL 140/266 1/5 Szymanski-PT-b04-CTLFireability-06 19909 m, 114 m/sec, 49297 t fired, .
Time elapsed: 2144 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2135/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2229843 t fired, 7725 attempts, .
49 EF STEQ 2135/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 20/1471 1/5 Szymanski-PT-b04-CTLFireability-00 13597 m, 642 m/sec, 48914 t fired, .
53 LTL EXCL 145/266 1/5 Szymanski-PT-b04-CTLFireability-06 20439 m, 106 m/sec, 50956 t fired, .
Time elapsed: 2149 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2140/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2233351 t fired, 7732 attempts, .
49 EF STEQ 2140/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 25/1471 1/5 Szymanski-PT-b04-CTLFireability-00 17072 m, 695 m/sec, 60772 t fired, .
53 LTL EXCL 150/266 1/5 Szymanski-PT-b04-CTLFireability-06 21072 m, 126 m/sec, 53327 t fired, .
Time elapsed: 2154 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2145/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2236525 t fired, 7743 attempts, .
49 EF STEQ 2145/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 30/1471 1/5 Szymanski-PT-b04-CTLFireability-00 20530 m, 691 m/sec, 68764 t fired, .
53 LTL EXCL 155/266 1/5 Szymanski-PT-b04-CTLFireability-06 21565 m, 98 m/sec, 54438 t fired, .
Time elapsed: 2159 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2150/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2239818 t fired, 7751 attempts, .
49 EF STEQ 2150/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 35/1471 1/5 Szymanski-PT-b04-CTLFireability-00 23780 m, 650 m/sec, 76686 t fired, .
53 LTL EXCL 160/266 1/5 Szymanski-PT-b04-CTLFireability-06 22086 m, 104 m/sec, 55257 t fired, .
Time elapsed: 2164 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2155/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2242837 t fired, 7761 attempts, .
49 EF STEQ 2155/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 40/1471 1/5 Szymanski-PT-b04-CTLFireability-00 26666 m, 577 m/sec, 84213 t fired, .
53 LTL EXCL 165/266 1/5 Szymanski-PT-b04-CTLFireability-06 22907 m, 164 m/sec, 58172 t fired, .
Time elapsed: 2169 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2160/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2246417 t fired, 7770 attempts, .
49 EF STEQ 2160/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 45/1471 1/5 Szymanski-PT-b04-CTLFireability-00 30650 m, 796 m/sec, 93836 t fired, .
53 LTL EXCL 170/266 1/5 Szymanski-PT-b04-CTLFireability-06 23552 m, 129 m/sec, 59367 t fired, .
Time elapsed: 2174 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2165/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2250111 t fired, 7781 attempts, .
49 EF STEQ 2165/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 50/1471 1/5 Szymanski-PT-b04-CTLFireability-00 34385 m, 747 m/sec, 103357 t fired, .
53 LTL EXCL 175/266 1/5 Szymanski-PT-b04-CTLFireability-06 24392 m, 168 m/sec, 61048 t fired, .
Time elapsed: 2179 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2170/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2253841 t fired, 7795 attempts, .
49 EF STEQ 2170/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 55/1471 1/5 Szymanski-PT-b04-CTLFireability-00 37865 m, 696 m/sec, 110289 t fired, .
53 LTL EXCL 180/266 1/5 Szymanski-PT-b04-CTLFireability-06 25014 m, 124 m/sec, 63072 t fired, .
Time elapsed: 2184 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2175/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2257653 t fired, 7804 attempts, .
49 EF STEQ 2175/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 60/1471 1/5 Szymanski-PT-b04-CTLFireability-00 41825 m, 792 m/sec, 121758 t fired, .
53 LTL EXCL 185/266 1/5 Szymanski-PT-b04-CTLFireability-06 25680 m, 133 m/sec, 64567 t fired, .
Time elapsed: 2189 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2180/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2261732 t fired, 7814 attempts, .
49 EF STEQ 2180/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 65/1471 1/5 Szymanski-PT-b04-CTLFireability-00 45435 m, 722 m/sec, 130971 t fired, .
53 LTL EXCL 190/266 1/5 Szymanski-PT-b04-CTLFireability-06 26284 m, 120 m/sec, 66760 t fired, .
Time elapsed: 2194 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2185/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2265144 t fired, 7823 attempts, .
49 EF STEQ 2185/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 70/1471 1/5 Szymanski-PT-b04-CTLFireability-00 48606 m, 634 m/sec, 138525 t fired, .
53 LTL EXCL 195/266 1/5 Szymanski-PT-b04-CTLFireability-06 26845 m, 112 m/sec, 68241 t fired, .
Time elapsed: 2199 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2190/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2268645 t fired, 7833 attempts, .
49 EF STEQ 2190/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 75/1471 1/5 Szymanski-PT-b04-CTLFireability-00 51926 m, 664 m/sec, 146075 t fired, .
53 LTL EXCL 200/266 1/5 Szymanski-PT-b04-CTLFireability-06 27602 m, 151 m/sec, 69525 t fired, .
Time elapsed: 2204 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2195/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2272268 t fired, 7845 attempts, .
49 EF STEQ 2195/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 80/1471 1/5 Szymanski-PT-b04-CTLFireability-00 55338 m, 682 m/sec, 157315 t fired, .
53 LTL EXCL 205/266 1/5 Szymanski-PT-b04-CTLFireability-06 28407 m, 161 m/sec, 70782 t fired, .
Time elapsed: 2209 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2200/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2275855 t fired, 7859 attempts, .
49 EF STEQ 2200/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 85/1471 1/5 Szymanski-PT-b04-CTLFireability-00 59112 m, 754 m/sec, 169291 t fired, .
53 LTL EXCL 210/266 1/5 Szymanski-PT-b04-CTLFireability-06 28929 m, 104 m/sec, 71743 t fired, .
Time elapsed: 2214 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2205/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2279768 t fired, 7870 attempts, .
49 EF STEQ 2205/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 90/1471 1/5 Szymanski-PT-b04-CTLFireability-00 62518 m, 681 m/sec, 177741 t fired, .
53 LTL EXCL 215/266 1/5 Szymanski-PT-b04-CTLFireability-06 29538 m, 121 m/sec, 74174 t fired, .
Time elapsed: 2219 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2210/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2283454 t fired, 7885 attempts, .
49 EF STEQ 2210/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 95/1471 1/5 Szymanski-PT-b04-CTLFireability-00 66244 m, 745 m/sec, 187155 t fired, .
53 LTL EXCL 220/266 1/5 Szymanski-PT-b04-CTLFireability-06 30075 m, 107 m/sec, 76215 t fired, .
Time elapsed: 2224 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2215/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2287149 t fired, 7897 attempts, .
49 EF STEQ 2215/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 100/1471 1/5 Szymanski-PT-b04-CTLFireability-00 69946 m, 740 m/sec, 199908 t fired, .
53 LTL EXCL 225/266 1/5 Szymanski-PT-b04-CTLFireability-06 30656 m, 116 m/sec, 78530 t fired, .
Time elapsed: 2229 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2220/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2291231 t fired, 7911 attempts, .
49 EF STEQ 2220/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 105/1471 1/5 Szymanski-PT-b04-CTLFireability-00 73676 m, 746 m/sec, 208657 t fired, .
53 LTL EXCL 230/266 1/5 Szymanski-PT-b04-CTLFireability-06 31254 m, 119 m/sec, 79814 t fired, .
Time elapsed: 2234 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b04-CTLFireability-00: EF 0 0 3 0 2 0 0 0
Szymanski-PT-b04-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-05: F 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-06: SP ECTL 0 0 1 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-07: EG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
Szymanski-PT-b04-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b04-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-b04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2225/3586 0/5 Szymanski-PT-b04-CTLFireability-00 2294684 t fired, 7922 attempts, .
49 EF STEQ 2225/3586 0/5 Szymanski-PT-b04-CTLFireability-00 sara is running.
50 EF EXCL 110/1471 1/5 Szymanski-PT-b04-CTLFireability-00 77183 m, 701 m/sec, 218690 t fired, .
53 LTL EXCL 235/266 1/5 Szymanski-PT-b04-CTLFireability-06 31746 m, 98 m/sec, 80778 t fired, .
Time elapsed: 2239 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b04-CTLFireability-01: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-04: CTL false CTL model checker
Szymanski-PT-b04-CTLFireability-15: CTL false CTL model checker
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Szymanski-PT-b04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Szymanski-PT-b04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703100458"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Szymanski-PT-b04.tgz
mv Szymanski-PT-b04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;