About the Execution of LoLa+red for Szymanski-PT-a12
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1573.716 | 80888.00 | 86276.00 | 463.40 | TTFT?FT?FFTTFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703100442.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Szymanski-PT-a12, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703100442
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 7.2K Feb 26 16:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 26 16:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.8K Feb 26 16:49 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 26 16:49 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:19 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:19 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 17:19 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:19 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.7K Feb 26 16:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 26 16:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Feb 26 16:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 16:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:19 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:19 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 101K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Szymanski-PT-a12-CTLFireability-00
FORMULA_NAME Szymanski-PT-a12-CTLFireability-01
FORMULA_NAME Szymanski-PT-a12-CTLFireability-02
FORMULA_NAME Szymanski-PT-a12-CTLFireability-03
FORMULA_NAME Szymanski-PT-a12-CTLFireability-04
FORMULA_NAME Szymanski-PT-a12-CTLFireability-05
FORMULA_NAME Szymanski-PT-a12-CTLFireability-06
FORMULA_NAME Szymanski-PT-a12-CTLFireability-07
FORMULA_NAME Szymanski-PT-a12-CTLFireability-08
FORMULA_NAME Szymanski-PT-a12-CTLFireability-09
FORMULA_NAME Szymanski-PT-a12-CTLFireability-10
FORMULA_NAME Szymanski-PT-a12-CTLFireability-11
FORMULA_NAME Szymanski-PT-a12-CTLFireability-12
FORMULA_NAME Szymanski-PT-a12-CTLFireability-13
FORMULA_NAME Szymanski-PT-a12-CTLFireability-14
FORMULA_NAME Szymanski-PT-a12-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679188164966
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Szymanski-PT-a12
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 01:09:26] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 01:09:26] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 01:09:26] [INFO ] Load time of PNML (sax parser for PT used): 53 ms
[2023-03-19 01:09:26] [INFO ] Transformed 61 places.
[2023-03-19 01:09:26] [INFO ] Transformed 224 transitions.
[2023-03-19 01:09:26] [INFO ] Parsed PT model containing 61 places and 224 transitions and 900 arcs in 113 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 1 formulas.
Deduced a syphon composed of 12 places in 1 ms
Reduce places removed 12 places and 8 transitions.
FORMULA Szymanski-PT-a12-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Szymanski-PT-a12-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 37 out of 49 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 49/49 places, 216/216 transitions.
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 47 transition count 216
Applied a total of 2 rules in 13 ms. Remains 47 /49 variables (removed 2) and now considering 216/216 (removed 0) transitions.
[2023-03-19 01:09:26] [INFO ] Flow matrix only has 79 transitions (discarded 137 similar events)
// Phase 1: matrix 79 rows 47 cols
[2023-03-19 01:09:26] [INFO ] Computed 1 place invariants in 12 ms
[2023-03-19 01:09:26] [INFO ] Implicit Places using invariants in 167 ms returned []
[2023-03-19 01:09:26] [INFO ] Flow matrix only has 79 transitions (discarded 137 similar events)
[2023-03-19 01:09:26] [INFO ] Invariant cache hit.
[2023-03-19 01:09:26] [INFO ] State equation strengthened by 9 read => feed constraints.
[2023-03-19 01:09:26] [INFO ] Implicit Places using invariants and state equation in 87 ms returned []
Implicit Place search using SMT with State Equation took 278 ms to find 0 implicit places.
[2023-03-19 01:09:26] [INFO ] Flow matrix only has 79 transitions (discarded 137 similar events)
[2023-03-19 01:09:26] [INFO ] Invariant cache hit.
[2023-03-19 01:09:26] [INFO ] Dead Transitions using invariants and state equation in 138 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 47/49 places, 216/216 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 432 ms. Remains : 47/49 places, 216/216 transitions.
Support contains 37 out of 47 places after structural reductions.
[2023-03-19 01:09:27] [INFO ] Flatten gal took : 34 ms
[2023-03-19 01:09:27] [INFO ] Flatten gal took : 15 ms
[2023-03-19 01:09:27] [INFO ] Input system was already deterministic with 216 transitions.
Support contains 36 out of 47 places (down from 37) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 8 resets, run finished after 235 ms. (steps per millisecond=42 ) properties (out of 46) seen :23
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 23) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 22) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 19) seen :0
Running SMT prover for 19 properties.
[2023-03-19 01:09:27] [INFO ] Flow matrix only has 79 transitions (discarded 137 similar events)
[2023-03-19 01:09:27] [INFO ] Invariant cache hit.
[2023-03-19 01:09:27] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 01:09:27] [INFO ] After 27ms SMT Verify possible using state equation in real domain returned unsat :2 sat :1 real:16
[2023-03-19 01:09:27] [INFO ] State equation strengthened by 9 read => feed constraints.
[2023-03-19 01:09:27] [INFO ] After 6ms SMT Verify possible using 9 Read/Feed constraints in real domain returned unsat :2 sat :0 real:17
[2023-03-19 01:09:27] [INFO ] After 130ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:17
[2023-03-19 01:09:27] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 01:09:28] [INFO ] After 99ms SMT Verify possible using state equation in natural domain returned unsat :8 sat :11
[2023-03-19 01:09:28] [INFO ] After 45ms SMT Verify possible using 9 Read/Feed constraints in natural domain returned unsat :8 sat :11
[2023-03-19 01:09:28] [INFO ] After 122ms SMT Verify possible using trap constraints in natural domain returned unsat :8 sat :11
Attempting to minimize the solution found.
Minimization took 63 ms.
[2023-03-19 01:09:28] [INFO ] After 372ms SMT Verify possible using all constraints in natural domain returned unsat :8 sat :11
Fused 19 Parikh solutions to 11 different solutions.
Parikh walk visited 0 properties in 57 ms.
Support contains 14 out of 47 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 47/47 places, 216/216 transitions.
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 47 transition count 215
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 5 place count 43 transition count 199
Iterating global reduction 1 with 4 rules applied. Total rules applied 9 place count 43 transition count 199
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 1 with 16 rules applied. Total rules applied 25 place count 43 transition count 183
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 26 place count 42 transition count 179
Iterating global reduction 1 with 1 rules applied. Total rules applied 27 place count 42 transition count 179
Applied a total of 27 rules in 24 ms. Remains 42 /47 variables (removed 5) and now considering 179/216 (removed 37) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 24 ms. Remains : 42/47 places, 179/216 transitions.
Incomplete random walk after 10010 steps, including 3 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 11) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10000 steps, including 4 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 10) seen :1
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=769 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 9) seen :0
Running SMT prover for 9 properties.
[2023-03-19 01:09:28] [INFO ] Flow matrix only has 69 transitions (discarded 110 similar events)
// Phase 1: matrix 69 rows 42 cols
[2023-03-19 01:09:28] [INFO ] Computed 1 place invariants in 2 ms
[2023-03-19 01:09:28] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 01:09:28] [INFO ] After 48ms SMT Verify possible using state equation in real domain returned unsat :0 sat :3 real:6
[2023-03-19 01:09:28] [INFO ] State equation strengthened by 9 read => feed constraints.
[2023-03-19 01:09:28] [INFO ] After 10ms SMT Verify possible using 9 Read/Feed constraints in real domain returned unsat :0 sat :0 real:9
[2023-03-19 01:09:28] [INFO ] After 104ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:9
[2023-03-19 01:09:28] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-19 01:09:28] [INFO ] After 43ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :9
[2023-03-19 01:09:28] [INFO ] After 38ms SMT Verify possible using 9 Read/Feed constraints in natural domain returned unsat :0 sat :9
[2023-03-19 01:09:28] [INFO ] After 78ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :9
Attempting to minimize the solution found.
Minimization took 26 ms.
[2023-03-19 01:09:28] [INFO ] After 184ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :9
Parikh walk visited 0 properties in 15 ms.
Support contains 10 out of 42 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 42/42 places, 179/179 transitions.
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 42 transition count 178
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 41 transition count 174
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 41 transition count 174
Applied a total of 3 rules in 8 ms. Remains 41 /42 variables (removed 1) and now considering 174/179 (removed 5) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 8 ms. Remains : 41/42 places, 174/179 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=666 ) properties (out of 9) seen :0
Finished probabilistic random walk after 190510 steps, run visited all 9 properties in 324 ms. (steps per millisecond=587 )
Probabilistic random walk after 190510 steps, saw 136961 distinct states, run finished after 324 ms. (steps per millisecond=587 ) properties seen :9
Successfully simplified 8 atomic propositions for a total of 14 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA Szymanski-PT-a12-CTLFireability-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Szymanski-PT-a12-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Szymanski-PT-a12-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 01:09:29] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 10 ms
[2023-03-19 01:09:29] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA Szymanski-PT-a12-CTLFireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Szymanski-PT-a12-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Szymanski-PT-a12-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 11 ms
[2023-03-19 01:09:29] [INFO ] Input system was already deterministic with 216 transitions.
Support contains 24 out of 47 places (down from 29) after GAL structural reductions.
Computed a total of 9 stabilizing places and 36 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Applied a total of 10 rules in 3 ms. Remains 42 /47 variables (removed 5) and now considering 196/216 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 42/47 places, 196/216 transitions.
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 8 ms
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 12 ms
[2023-03-19 01:09:29] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 26 place count 42 transition count 180
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 28 place count 40 transition count 172
Iterating global reduction 0 with 2 rules applied. Total rules applied 30 place count 40 transition count 172
Applied a total of 30 rules in 16 ms. Remains 40 /47 variables (removed 7) and now considering 172/216 (removed 44) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 40/47 places, 172/216 transitions.
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 8 ms
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 8 ms
[2023-03-19 01:09:29] [INFO ] Input system was already deterministic with 172 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Applied a total of 10 rules in 2 ms. Remains 42 /47 variables (removed 5) and now considering 196/216 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 42/47 places, 196/216 transitions.
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 8 ms
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 9 ms
[2023-03-19 01:09:29] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Applied a total of 10 rules in 2 ms. Remains 42 /47 variables (removed 5) and now considering 196/216 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 42/47 places, 196/216 transitions.
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 8 ms
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 9 ms
[2023-03-19 01:09:29] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 26 place count 42 transition count 180
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 27 place count 41 transition count 176
Iterating global reduction 0 with 1 rules applied. Total rules applied 28 place count 41 transition count 176
Applied a total of 28 rules in 12 ms. Remains 41 /47 variables (removed 6) and now considering 176/216 (removed 40) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 41/47 places, 176/216 transitions.
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 6 ms
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 7 ms
[2023-03-19 01:09:29] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 26 place count 42 transition count 180
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 28 place count 40 transition count 172
Iterating global reduction 0 with 2 rules applied. Total rules applied 30 place count 40 transition count 172
Applied a total of 30 rules in 12 ms. Remains 40 /47 variables (removed 7) and now considering 172/216 (removed 44) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 40/47 places, 172/216 transitions.
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 6 ms
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 6 ms
[2023-03-19 01:09:29] [INFO ] Input system was already deterministic with 172 transitions.
Finished random walk after 21 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=21 )
FORMULA Szymanski-PT-a12-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 43 transition count 200
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 43 transition count 200
Applied a total of 8 rules in 2 ms. Remains 43 /47 variables (removed 4) and now considering 200/216 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 43/47 places, 200/216 transitions.
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 8 ms
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 8 ms
[2023-03-19 01:09:29] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 43 transition count 200
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 43 transition count 200
Applied a total of 8 rules in 2 ms. Remains 43 /47 variables (removed 4) and now considering 200/216 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 43/47 places, 200/216 transitions.
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 6 ms
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 6 ms
[2023-03-19 01:09:29] [INFO ] Input system was already deterministic with 200 transitions.
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 7 ms
[2023-03-19 01:09:29] [INFO ] Flatten gal took : 7 ms
[2023-03-19 01:09:29] [INFO ] Export to MCC of 7 properties in file /home/mcc/execution/CTLFireability.sr.xml took 1 ms.
[2023-03-19 01:09:29] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 47 places, 216 transitions and 860 arcs took 2 ms.
Total runtime 3426 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Szymanski-PT-a12
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
FORMULA Szymanski-PT-a12-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-a12-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-a12-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-a12-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-a12-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679188245854
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 16 (type EXCL) for 15 Szymanski-PT-a12-CTLFireability-12
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 16 (type EXCL) for Szymanski-PT-a12-CTLFireability-12
lola: result : false
lola: markings : 116
lola: fired transitions : 129
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 Szymanski-PT-a12-CTLFireability-06
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:664
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 10 (type EXCL) for Szymanski-PT-a12-CTLFireability-06
lola: result : true
lola: markings : 580
lola: fired transitions : 749
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 Szymanski-PT-a12-CTLFireability-04
lola: time limit : 720 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/720 8/32 Szymanski-PT-a12-CTLFireability-04 1680756 m, 336151 m/sec, 4796846 t fired, .
Time elapsed: 5 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/720 13/32 Szymanski-PT-a12-CTLFireability-04 3048354 m, 273519 m/sec, 9877679 t fired, .
Time elapsed: 10 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/720 19/32 Szymanski-PT-a12-CTLFireability-04 4322672 m, 254863 m/sec, 15185523 t fired, .
Time elapsed: 15 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/720 24/32 Szymanski-PT-a12-CTLFireability-04 5607476 m, 256960 m/sec, 20188534 t fired, .
Time elapsed: 20 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/720 29/32 Szymanski-PT-a12-CTLFireability-04 6889599 m, 256424 m/sec, 25492936 t fired, .
Time elapsed: 25 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 7
lola: CANCELED task # 7 (type EXCL) for Szymanski-PT-a12-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a12-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 7
lola: LAUNCH task # 19 (type EXCL) for 18 Szymanski-PT-a12-CTLFireability-15
lola: time limit : 892 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for Szymanski-PT-a12-CTLFireability-15
lola: result : false
lola: markings : 24
lola: fired transitions : 52
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 Szymanski-PT-a12-CTLFireability-01
lola: time limit : 1190 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for Szymanski-PT-a12-CTLFireability-01
lola: result : true
lola: markings : 116
lola: fired transitions : 128
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 3 Szymanski-PT-a12-CTLFireability-03
lola: time limit : 1785 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for Szymanski-PT-a12-CTLFireability-03
lola: result : false
lola: markings : 518
lola: fired transitions : 669
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 Szymanski-PT-a12-CTLFireability-07
lola: time limit : 3570 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-01: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-03: SP ECTL true LTL model checker
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
Szymanski-PT-a12-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/3570 5/32 Szymanski-PT-a12-CTLFireability-07 1036354 m, 207270 m/sec, 4754008 t fired, .
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-01: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-03: SP ECTL true LTL model checker
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
Szymanski-PT-a12-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/3570 9/32 Szymanski-PT-a12-CTLFireability-07 1968077 m, 186344 m/sec, 9225052 t fired, .
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-01: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-03: SP ECTL true LTL model checker
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
Szymanski-PT-a12-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/3570 12/32 Szymanski-PT-a12-CTLFireability-07 2869729 m, 180330 m/sec, 13608134 t fired, .
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-01: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-03: SP ECTL true LTL model checker
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
Szymanski-PT-a12-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/3570 16/32 Szymanski-PT-a12-CTLFireability-07 3756488 m, 177351 m/sec, 17939096 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-01: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-03: SP ECTL true LTL model checker
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
Szymanski-PT-a12-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/3570 19/32 Szymanski-PT-a12-CTLFireability-07 4630213 m, 174745 m/sec, 22232195 t fired, .
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-01: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-03: SP ECTL true LTL model checker
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
Szymanski-PT-a12-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/3570 23/32 Szymanski-PT-a12-CTLFireability-07 5499485 m, 173854 m/sec, 26504526 t fired, .
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-01: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-03: SP ECTL true LTL model checker
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
Szymanski-PT-a12-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/3570 26/32 Szymanski-PT-a12-CTLFireability-07 6357857 m, 171674 m/sec, 30751964 t fired, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-01: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-03: SP ECTL true LTL model checker
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
Szymanski-PT-a12-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/3570 30/32 Szymanski-PT-a12-CTLFireability-07 7213132 m, 171055 m/sec, 34983436 t fired, .
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 7
lola: CANCELED task # 13 (type EXCL) for Szymanski-PT-a12-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-01: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-03: SP ECTL true LTL model checker
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
Szymanski-PT-a12-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a12-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 7
lola: Portfolio finished: no open tasks 7
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a12-CTLFireability-01: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-03: SP ECTL true LTL model checker
Szymanski-PT-a12-CTLFireability-04: CTL unknown AGGR
Szymanski-PT-a12-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-a12-CTLFireability-07: CTL unknown AGGR
Szymanski-PT-a12-CTLFireability-12: CTL false CTL model checker
Szymanski-PT-a12-CTLFireability-15: CTL false CTL model checker
Time elapsed: 75 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Szymanski-PT-a12"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Szymanski-PT-a12, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703100442"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Szymanski-PT-a12.tgz
mv Szymanski-PT-a12 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;